TW201030412A - Display device and television system - Google Patents

Display device and television system Download PDF

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Publication number
TW201030412A
TW201030412A TW98132356A TW98132356A TW201030412A TW 201030412 A TW201030412 A TW 201030412A TW 98132356 A TW98132356 A TW 98132356A TW 98132356 A TW98132356 A TW 98132356A TW 201030412 A TW201030412 A TW 201030412A
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TW
Taiwan
Prior art keywords
circuit
output
self
signal
display
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TW98132356A
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Chinese (zh)
Inventor
Shinsuke Anzai
Yoshihiro Nakatani
Hiroaki Fujino
Hirofumi Matsui
Toshio Watanabe
Masami Mori
Kohichi Hosokawa
Masafumi Katsutani
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Sharp Kk
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Publication of TW201030412A publication Critical patent/TW201030412A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

To provide a display device that displays video even during self detection and self repair of a driving circuit. A display 90 of a liquid crystal television 400 includes: a display panel 80; a source driver 10a that drives the display panel 80, and the source driver 10a has a comparing and determining circuit 50 for detecting a failure and a switching circuit 60 for repairing the failure; and a source driver 10b that drives the display panel 80, and the source driver 10b is different from the source driver 10a. While the failure of the source driver 10a is detected and repaired, the source driver 10b drives the display panel 80.

Description

201030412 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種使用有進行DA(Digital/Analog，數位 類比）轉換器輸出電路中之不良之自我檢測及自我修復的 驅動電路之顯示裝置。 【先前技術】 近年來’伴隨著液晶面板等之大型化及高精細化，於液 晶驅動用半導體積體電路中’液晶驅動用輸出端子之端子 數不斷增加、及自輸出端子輸出之多值電壓不斷多灰階 化。例如當前主流之液晶驅動用半導體積體電路中，存在 包含可輸出256灰階之電壓之約500個輸出端子數者。進 而’當前亦進行了包含1000個以上之輸出端子數之液晶驅 動用半導體積體電路之開發。又，伴隨著液晶面板之多色 化，亦進行可輸出1024灰階之灰階輸出電壓之液晶驅動用 半導體積體電路之開發。 於此，以下參照圖43，對先前之液晶驅動用半導體積體 電路之構成進行說明。圖43係表示先前之液晶駆動用半導 體積體電路之構成之區塊。 该圖所示之液晶驅動用半導體積體電路1〇1係可分別自n 個液晶驅動用信號輸出端子輸出階之輸出電壓。首 先，對液晶驅動用半導體積體電路1〇1之構成加以說明。 液BB驅動用半導體積體電路1〇丨於外部包含時脈輸入端子 102、包含複數個信號輸入端子之灰階資料輸入端子1〇3、 LOAD(載入）信號輸入端子1〇4、以及作為基準電源端子之 I43488.doc 201030412 VO端子105、VI端子106、V2端子i〇7、V3端子l〇8、V4端 子109。進而’液晶驅動用半導體積體電路ι〇1包含^個液 晶驅動用信號輸出端子m — (以下，將液晶驅動用 信號輸出端子稱為信號輸出端子。進而，於對液晶驅動用 信號輸出端子111-1〜lU_n進行總稱之情形時，稱為信號 輸出端子111)。又’液晶驅動用半導體積體電路1〇ι包含 基準電源修正電路121、指標用移位暫存器電路123、鎖存 電路部124、保持電路125、D/A轉換器（Dighal Anal〇g Converter :以下稱為DAC)電路126、以及輸出緩衝器 127。又，指標用移位暫存器電路123包含n段移位暫存器 電路123-1〜123-n。進而，鎖存電路部124包含11個鎖存電 路124-1〜124-n ’以及保持電路125包含η個保持電路125· 1 125 η 又 ’ DAC 電路 126 包含 η個 DAC 電路 1 26-1~126_ η此外，輸出緩衝器127包含η個輸出緩衝器127-1至127-η，且各輸出緩衝器包含運算放大器。 其_人，對液晶驅動用半導體積體電路1〇1之動作加以說 明。指標用移位暫存器電路123根據自時脈輸入端子1〇2輸 入之時脈輸人6號’自第-個鎖存電路124-1至第η個鎖存 24 η為止進行依序選擇。由指標用移位暫存器電路 123選擇之鎖存電路124儲存來自灰階資料輸入端子1〇3之 灰1%輸出貝料。再者，灰階輸出資料係對應於每個鎖存電 路124、換s之係對應於每個信號輸出端子I"之、與上述 時脈輸人信_步之資料。因此，各鎖存電路MW% 11可儲存對應於每個信號輸出端子111之各自值相異之灰階 143488.doc 201030412 輸出資料。鎖存電路124-1〜124-n中所儲存之灰階輸出資 料係根據資料LOAD信號，而向各自對應之n個保持電路 125-1〜125-11傳輸。進而，保持電路將自鎖存 • 電路丨24·1〜124_n輸入之灰階輸出資料作為數位資料而輸 出至DAC電路126-1〜126-n。 to 於此，DAC電路126-1〜126-n根據來自保持電路125之灰 階輸出資料，選擇m種灰階電壓中之一種電壓值並輸出至 ❹ 輸出緩衝器127_卜。再者，DAC電路126根據自基準 電源端子V0端子105〜V4端子109輸入之電壓，可輸出„1種 灰階電壓。繼而，輸出緩衝器127將來自DAC電路126之灰 階電壓加以緩衝’並作為液晶面板驅動用信號而輸出至信 號輸出端子111·1〜Ill-η。 如上所述’移位暫存器電路123、鎖存電路124、保持電 路12 5、DAC電路126以及輸出緩衝器127之個數必需與液 晶駆動用信號輸出端子111之個數相同，若液晶驅動用信 0 號輸出端子111為1000個端子，則上述各電路124〜127亦分 別需要1000個。 如上所述’近年來’液晶面板等之顯示裝置不斷大型 •化、高精細化，於Fullspec之高精細電視（HDTV : High Definition Television)中，資料線數成為1920根。藉此， 顯示驅動用半導體積體電路必需對每個資料線提供 R*G*B(Red«Green«Blue，紅•綠•藍）之灰階電壓之信號，其 結果，顯示驅動用半導體積體電路必需1920根x3(R，G.B) =5760根輸出數，換言之必需包含5760個液晶驅動用信號 143488.doc 201030412 輸出端子。於此，在將一個顯示驅動用半導體積體電路之 輸出數設為720根之情形時，必需8個顯示驅動用半導體積 體電路。 通常，顯示驅動用半導體積體電路於晶圓階段進行測 試，於封裝後進行出廠測試，於搭載在液晶面板上後進行 顯示測試。進而，利用預燒或應力測試之篩選測試，除去 可能產生初始不良之半導體積體電路。因此，搭載有可能 產生顯示不良之顯示驅動用半導體積體電路之顯示裝置不 會發貨至市場中。然而’極少會因於出廠前之測試或筛選 測試時未判斷為不良之極微小之缺陷或異物之附著混入， 而於使用顯不裝置之期間產生顯不不良。例如，即便顯干 驅動用半導體積體電路之一根資料線於出廠後產生顯示不 良之比例為0.01 ppmU億分之U，於資料線數為576〇根之 Fullspec之HDTV中，顯示不良之產生比例亦為57 6 (100萬分之57.6)。即，約17361台中有1台產生顯示不良， 且越變彳于更大型化、更高精細化，顯示不良之產生比例就 越尚。 於產生如上所述之顯示不良之情形時，必需迅速地回收 顯示裝置而進行顯示驅動用半導體積體電路之維修，但回 收修理需要大量成本自不用說，且會導致商品形象之下 降。 於此，於先前技術中揭示有：於顯示驅動用半導體積體 電路中設置成為缺陷之電路所具有之預備電路，將存在缺 陷之電路切換為預備電路，藉此避免顯示驅動用半導體積 143488.doc 201030412 體電路之不良。 具體而言，專利文獻i中揭示有如下方法：顯示驅動用 半導體積體電路係於移位暫存器之各段中包含預備之並聯 電路’進行録暫㈣之自餘查，絲據㈣查結果而 選擇並聯電路之無缺陷之—方，藉此避免由缺陷之移位暫 存器所引起之顯示不良。進而，專利文獻2中揭示有如下 方法·於DAC電路之輸人端與輸出端設置有選擇器根據 記憶有存在缺陷之DAC電路之位置的RAM(Rand〇mBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using a driving circuit for performing self-detection and self-repair in a DA (Digital/Analog) converter output circuit. [Prior Art] In recent years, the number of terminals of the liquid crystal driving output terminal and the multi-value voltage output from the output terminal have been increasing in the semiconductor integrated circuit for liquid crystal driving in accordance with the increase in size and definition of the liquid crystal panel. Constantly more graying. For example, in the current mainstream semiconductor integrated circuit for liquid crystal driving, there are a number of about 500 output terminals including a voltage capable of outputting 256 gray scales. Further, the development of a semiconductor integrated circuit for liquid crystal driving including 1000 or more output terminals has been carried out. Further, along with the multi-coloring of the liquid crystal panel, development of a liquid crystal driving semiconductor integrated circuit capable of outputting a gray scale output voltage of 1024 gray scales has been carried out. Here, the configuration of the conventional liquid crystal driving semiconductor integrated circuit will be described below with reference to Fig. 43. Fig. 43 is a view showing the constitution of the conventional liquid crystal semiconductor half-conductor body circuit. The liquid crystal driving semiconductor integrated circuit 1〇1 shown in the figure can output the output voltage of the step from the n liquid crystal driving signal output terminals. First, the configuration of the liquid crystal driving semiconductor integrated circuit 1〇1 will be described. The liquid BB driving semiconductor integrated circuit 1 includes a clock input terminal 102, a gray scale data input terminal 1〇3 including a plurality of signal input terminals, a LOAD signal input terminal 1〇4, and Reference power supply terminal I43488.doc 201030412 VO terminal 105, VI terminal 106, V2 terminal i〇7, V3 terminal l〇8, V4 terminal 109. Further, the liquid crystal driving semiconductor integrated circuit ι 1 includes a liquid crystal driving signal output terminal m (hereinafter, the liquid crystal driving signal output terminal is referred to as a signal output terminal. Further, the liquid crystal driving signal output terminal 111 is provided. When -1 to lU_n is collectively referred to, it is referred to as a signal output terminal 111). Further, the liquid crystal drive semiconductor integrated circuit 1 includes a reference power supply correction circuit 121, an index shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D/A converter (Dighal Anal〇g Converter). : Hereinafter referred to as DAC) circuit 126, and output buffer 127. Further, the index shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n. Further, the latch circuit unit 124 includes eleven latch circuits 124-1 to 124-n' and the hold circuit 125 includes n hold circuits 125·1 125 η and 'the DAC circuit 126 includes n DAC circuits 1 26-1~ 126_n In addition, the output buffer 127 includes n output buffers 127-1 to 127-n, and each output buffer includes an operational amplifier. The operation of the semiconductor integrated circuit 1〇1 for liquid crystal driving will be described. The index shift register circuit 123 sequentially selects the clock input from the clock input terminal 1〇2 from the first latch circuit 124-1 to the nth latch 24n. . The latch circuit 124 selected by the index shift register circuit 123 stores the ash 1% output bead from the gray scale data input terminal 1〇3. Furthermore, the gray scale output data corresponds to each of the latch circuits 124, and the s series corresponds to the data of each of the signal output terminals I" and the clock input signal. Therefore, each latch circuit MW% 11 can store grayscale 143488.doc 201030412 output data corresponding to the respective values of each of the signal output terminals 111. The gray scale output data stored in the latch circuits 124-1 to 124-n is transmitted to the respective n holding circuits 125-1 to 125-11 based on the data LOAD signal. Further, the hold circuit outputs the gray scale output data input from the latch circuits 丨24·1 to 124_n as digital data to the DAC circuits 126-1 to 126-n. To this, the DAC circuits 126-1 to 126-n select one of the m kinds of gray scale voltages based on the gray scale output data from the hold circuit 125 and output it to the output buffer 127_b. Furthermore, the DAC circuit 126 can output "one type of gray scale voltage" based on the voltage input from the reference power supply terminal V0 terminals 105 to V4 terminal 109. Then, the output buffer 127 buffers the gray scale voltage from the DAC circuit 126'. The liquid crystal panel driving signals are output to the signal output terminals 111·1 to Ill-n. As described above, the 'shift register circuit 123, the latch circuit 124, the holding circuit 12 5, the DAC circuit 126, and the output buffer 127 The number of the liquid crystal output signal output terminals 111 must be the same as the number of the liquid crystal display signal output terminals 111. If the liquid crystal drive signal output terminal 111 is 1000 terminals, each of the above circuits 124 to 127 also needs 1000. In the high-definition television (HDTV: High Definition Television) of Fullspec, the number of data lines is 1920. In this case, it is necessary to display the semiconductor integrated circuit for driving. A signal of the gray scale voltage of R*G*B (Red«Green«Blue, red•green•blue) is supplied for each data line, and as a result, it is necessary to display 1920 x3 for the semiconductor integrated circuit for driving ( R, GB) = 5760 output numbers, in other words, 5760 liquid crystal drive signals 143488.doc 201030412 output terminals. When the number of outputs of one display drive semiconductor integrated circuit is 720, In general, the semiconductor integrated circuit for display driving is required to be tested at the wafer stage, and after being packaged, the factory test is performed, and after being mounted on the liquid crystal panel, the display test is performed. Further, the burn-in is performed. Or the screening test of the stress test removes the semiconductor integrated circuit that may cause initial failure. Therefore, the display device equipped with the display integrated semiconductor integrated circuit that may cause display failure is not shipped to the market. It is not judged to be a very small defect or adhesion of foreign matter during the test or screening test before leaving the factory, but it is not bad during the use of the display device. For example, even the semiconductor integrated circuit for the dry drive is used. The ratio of a data line to poor display at the factory is 0.01 ppm UU, and the number of data lines is 576. In the HDTV of FullSpec, the ratio of display failure is also 57 6 (57.6 million). That is, one of the approximately 17,361 units has a poor display, and the display becomes more large and finer. In the case where the display failure is as described above, it is necessary to promptly collect the display device and perform maintenance of the semiconductor integrated circuit for display driving, but recovery and repair require a large amount of cost, and it will be In the prior art, a preparatory circuit provided in a circuit for forming a defect in a semiconductor integrated circuit for driving display is switched, and a circuit having a defect is switched to a preliminary circuit, thereby avoiding display. Driving semiconductor product 143488.doc 201030412 Poor body circuit. Specifically, Patent Document i discloses a method in which the display driving semiconductor integrated circuit is included in each segment of the shift register including a preliminary parallel circuit 'to perform a temporary recording (4), and the data is based on (4) As a result, the defect-free side of the parallel circuit is selected, thereby avoiding display defects caused by the defective shift register. Further, Patent Document 2 discloses the following method: A RAM is provided in the input end and the output end of the DAC circuit according to the position of the DAC circuit in which the memory is defective (Rand〇m)

Mem〇ry，隨機存取記憶體）之資訊’切換選擇器而選擇使 用無缺陷之DAC電路。 [先前技術文獻] [專利文獻] [專利文獻1 ]日本公開專利公報「日本專利特開平6_ 208346號公報（1994年7月26日公開）」 [專利文獻2]日本公開專利公報「曰本專利特開平8_ 278771號公報（1996年10月22日公開）」 【發明内容】 [發明所欲解決之問題] 然而，具有自我檢測及自我修復功能之顯示用驅動電路 具有如下特性：於進行自我檢測動作之情形時，必需使將 影像信號供給至顯示裝置之輸出電路自顯示裝置分離因 此於此期間無法顯示圖像。因此，專利文獻i及專利文獻2 中所揭示之自我檢測及自我修復之構成中，例如於正在執 行自我檢測及自我修復中’當使用者未注意到此而嘗試操 143488.doc 201030412 作顯示裝置時，由於正在執行自我檢測及自我修復中故持 續無法顯示任何圖像，於此情形時存在給使用者造成顯示 裝置是否產生故障之誤解之問題。 再者’專利文獻1及專利文獻2中，完全未揭示對Dac電 路等輸出電路中之缺陷進行檢測之自我檢測之方法。 本發明係鑒於上述之問題點而完成者，其目的在於提供 一種顯示裝置，該顯示裝置具有能夠對輸出電路或輸出電 路周邊之輸出區塊之缺陷進行自我檢測及自我修復的驅動 電路’於進行自我檢測及自我修復時能夠於畫面中顯示映 it ° * [解決問題之技術手段] 為了解決上述課題，本發明之顯示裝置之特徵在於包 含：顯示面板；第1驅動電路，其係驅動上述顯示面板之 驅動電路，且具有對該驅動電路之不良進行檢測並修復之 自我檢測與自我修復機構；及第2驅動電路，其係驅動上 述顯示面板之驅動電路，且不同於上述第1驅動電路。 根據上述構成’第丨驅動電路驅動顯示面板。而且，第丄 驅動電路具有能夠檢測第i驅動電路自身之不良並對檢測 出之不良進行修復之自我檢測與自我修復機構。 又，根據上述構成，第2驅動電路不同於第丨驅動電路。 而且，第2驅動電路亦又驅動顯示面板。再者第2驅動電 路亦可包含自我檢測與自我修復機構，或者亦可為與第1 驅動電路相比僅進行簡單顯示之構成之驅動電路，對其並 未作特別限定。 H3488.do, 201030412 藉此，本發明之顯示裝置中’藉由第1驅動電路及第2驅 動電路之任一驅動電路均可驅動顯示面板。因此，當自我 檢測與自我修復機構對第1驅動電路之不良進行檢測並修 復時，即便於無法藉由第1驅動電路驅動顯示面板之情形 時，亦可藉由第2驅動電路驅動顯示面板，從而可於顯示 面板中顯示映像。Mem〇ry, random access memory) 'switches the selector and chooses to use a defect-free DAC circuit. [Patent Document 1] [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 6-208346 (published on July 26, 1994). [Patent Document 2] Japanese Laid-Open Patent Publication [Problem to be Solved by the Invention] However, a display driving circuit having a self-detecting and self-repairing function has the following characteristics: self-detection In the case of an operation, it is necessary to separate the output circuit that supplies the video signal to the display device from the display device, and thus the image cannot be displayed during this period. Therefore, in the composition of self-detection and self-repair disclosed in Patent Document i and Patent Document 2, for example, in performing self-detection and self-repair, 'when the user does not notice this, the user attempts to operate 143488.doc 201030412 as a display device. In the case where self-detection and self-repair are being performed, any image cannot be displayed continuously. In this case, there is a problem that the user is misunderstood whether the display device is malfunctioning. Further, in Patent Document 1 and Patent Document 2, a method of self-detection for detecting defects in an output circuit such as a Dac circuit is not disclosed at all. The present invention has been made in view of the above problems, and an object thereof is to provide a display device having a drive circuit capable of self-detecting and self-repairing defects of an output block or an output block around an output circuit. In the case of self-detection and self-repair, it is possible to display the image on the screen. [Technical means for solving the problem] In order to solve the above problems, the display device of the present invention includes a display panel, and a first drive circuit that drives the display. a driving circuit of the panel, and a self-detecting and self-repairing mechanism for detecting and repairing the defect of the driving circuit; and a second driving circuit for driving the driving circuit of the display panel, which is different from the first driving circuit. According to the above configuration, the second driving circuit drives the display panel. Further, the 丄 drive circuit has a self-detection and self-repair mechanism capable of detecting the defect of the ith drive circuit itself and repairing the detected defect. Further, according to the above configuration, the second drive circuit is different from the second drive circuit. Moreover, the second drive circuit drives the display panel again. Further, the second driving circuit may include a self-detecting and self-repairing mechanism, or may be a driving circuit configured to display only a simple display as compared with the first driving circuit, and is not particularly limited. H3488.do, 201030412 Thus, in the display device of the present invention, the display panel can be driven by any of the first drive circuit and the second drive circuit. Therefore, when the self-detection and self-repair mechanism detects and repairs the defect of the first drive circuit, even when the display panel cannot be driven by the first drive circuit, the display panel can be driven by the second drive circuit. Thereby the image can be displayed in the display panel.

本發明之顯示裝置中，上述第2驅動電路宜於上述自我 檢測與自我修復機構對上述第1驅動電路之不良進行檢測 並修復時，驅動上述顯示面板。 根據上述構成’上述第2驅動電路於上述自我檢測與自 我修復機構對上述第1驅動電路之不良進行檢測並修復 時，驅動上述顯示面板。 藉此，當自我檢測與自我修復機構進行第〗驅動電路之 不良檢測及修復而無法藉由第〗驅動電路驅動顯示面板 時，第2驅動電路驅動顯示面板。因此，於第丨驅動電路之 自我檢測與自我修復過程中，可藉由第2驅動電路驅動顯 示面板，而於顯示面板中作為映像來顯示當前狀態（即正 在進行第m動電路之不良檢職修復）之說明，因此不會 讓使用者誤解為顯示裝置出現故障，從而可使對使用者而 言之便利性提高。 本發明之顯示裝置中，卜势 珉置1f上述第1驅動電路宜具有 以驅動上述顯示面板之輸出 预口疏之輸出電路，上述 測與自我修復機構具有對上 ...^ ^ W出電路疋否不良進行判定 之判疋機構，於上述判宕嫩 J疋機構之判定結果為不良之情形 143488.doc 201030412In the display device of the present invention, the second driving circuit is adapted to drive the display panel when the self-detecting and self-healing means detects and repairs the defect of the first driving circuit. According to the above configuration, the second drive circuit drives the display panel when detecting and repairing the failure of the first drive circuit by the self-detection and self-repair mechanism. Thereby, when the self-detection and self-repair mechanism performs the failure detection and repair of the first drive circuit and the display panel cannot be driven by the first drive circuit, the second drive circuit drives the display panel. Therefore, in the self-detection and self-repair process of the second driving circuit, the display panel can be driven by the second driving circuit, and the current state is displayed as an image in the display panel (ie, the bad operation of the mth dynamic circuit is being performed. The description of the repair) does not cause the user to misunderstand that the display device is malfunctioning, so that the convenience for the user is improved. In the display device of the present invention, the first driving circuit preferably has an output circuit for driving the output of the display panel, and the self-repairing mechanism has a pair of upper and lower circuits. If the judgment mechanism of the judgment is unfavorable, the judgment result of the judgment is not good. 143488.doc 201030412

時，以將lT當> I 之輸出信號輸出至上述顯示面板之 驅動電路進行自我修復。 式對該 根據上述構成，第1驅動電路具有輸出用以驅動顯— ::輸出信號之輸出電路。輸出電路將例如映像資料：： '”、火階電壓並作為驅動顯示面板之輸出信號加以輪出。、 出二it:構成，自我檢測與自我修復機構具有•輸 又進行判定之判定機構，於判定機構之 結果為不良之情形時，以將正常之輸出信號輸出至顯八： 板之方式對驅動電路進行自我修復。 下 電 我 藉此，本發明之顯示裝置中，可檢測驅動電路之輸出 路之缺陷’並可於輸㈣路中存在缺陷之情 ^ 修復。 仃自 本發明之顯示|置中，上述^驅動電路宜具有可 述輸出4號輸出至上述顯示面板之預備輸出電路，上述自 我檢測與自我修復機構具有切換機構於上述判 判定結果為不良之•产开,# . u + 秦 艮之清形時，將來自上述成為不良之輸出電 路之輸出信號切換為來自上述預備輸出電路的輸出信號而 作為向上述顯示面板之輸出信號。 根據上述構成’第1驅動電路具有可將輸出㈣輸出至 ^丁面板之預備輸出電路。預備輸出電路與輸出電路相 同，可將例如映像資料轉換為灰階電壓並作為驅動顯示面 板之輸出信號加以輸出。 a又，根據上述構成，自我檢測與自我修復機構具有將判 疋機構判定為不良之輸出電路切換為預備輸出電路之切換 I43488.doc 201030412 機構。 藉此’本發明之顯示裝置中，於輸出電路存在缺陷之情 形時’可藉由將存在缺陷之輸出電路切換為預備輸出電路 . 而谷易地進行驅動電路之自我修復。 、 又’本發明之顯示裝置中，上述判定機構宜具有對來自 上述輸出電路之輸出信號、與來自上述預備輸出電路之輸 出信號進行比較的比較機構，且根據上述比較機構之比較 Φ 結果而判定上述輸出電路是否不良。 根據上述構成’判定機構具有比較機構。又，比較機構 對來自輸出電路之輸出信號、與來自預備輸出電路之輸出 信號進行比較。而且，判定機構根據比較機構之比較結果 而判定輸出電路是否不良。 藉此，本發明之顯示裝置中，可藉由對輸出電路之輸出 與預備輸出電路之輸出進行比較而判定輸出電路之不良， 因此可以簡單之構成容易地檢測輸出電路之不良。 • 又，本發明之顯示裝置中，宜進一步具有對輸入至上述 輸出電路及上述預備輸出電路之輸入信號進行控制之控制 機構，上述控制機構對上述輸出電路與上述預備輸出電路 ’輸入大小相異之輸入信號，並且輸出與上述大小相異之輸 入信號相對應之、來自上述比較機構之比較結果之期望 值’上述判定機構於上述比較結果與上述期望值相異之情 形時，判定上述輸出電路為不良。 根據上述構成，控制機構對輸入至輸出電路與預備輸出 電路之輸入信號進行控制，且輸出大小相異之輸入信號。 143488.doc 201030412 又，控制機構輸出與大小相異之輸入信號相對應之、來自 比較機構之比較結果之期望值。而且，判定機構於來自比 較機構之實際之比較結果與來自控制機構之期望值相異的 情形時’判定為輸出電路不良。 八體而„例如’對輸出電路輸入灰階m之輸入信號， 對預備輸出電路輸入灰階m+1之輪入信號。再者，灰階爪 之灰階電壓係較灰階m+1之灰階電壓更低之電壓。於此， 若輸出電路正常，則比較機構輸出表示自預備輪出電路輸 入之灰階電壓較高之信號。另一方面，於輸出電路中存在❹ 缺陷’即便輸入灰階m之信號而輸出電路亦僅能輸出較高 之灰1¾電壓之情形時，比較機構輸出表示自輸出電路輸入 之灰階電壓較高之信號。 如此’本發明之驅動電路中，比較機構對自輪出電路及 預備輸出電路所輸出之灰階電壓進行比較，並於輸出電路 中存在缺陷之情形時及不存在缺陷之情形時，輸出 之信號。 、 其^，判錢構根據自比較機構輸出之信號而㈣輸出© 電路疋否不良。具體而言，如上所述，於對輸出電路輸入 灰階m之輸人信號，對預備輸出電路輸人灰階nrn之輸入 信號之情形時’當自比較機構輸入有表示來自輸出電路之. 灰階電a較高之信號時，判定為輸出電料良。另—方. 面S自比較機構輸入有表示來自預備輸出電路之 壓較高之信號時，判定機構判定為輸出電路正常。 藉此，本發明之顯示裝置中，藉由容易地檢測輸出電路 143488.doc -12· 201030412 於輸出電路存在缺陷之情形時能夠 之缺陷之具體之機構， 進行自我修復。 本發明之顯示裝置中， 选批加认 中上返判定機構宜包含對來自上述 複數個輸出電路中、 夕兩個輸出電路之輸出信號進行比 較的比較機構，且根攄^ ^ d .. 據上述比較機構之比較結果而判定上 述輸出電路是否不良。 斜：？上述構成’判定機構包含比較機構。又，比較機構At the time, the output signal of lT is > I is output to the drive circuit of the above display panel for self-repair. According to the above configuration, the first drive circuit has an output circuit for outputting a display-::output signal. The output circuit will, for example, image data:: ', the fire level voltage and the output signal of the driving display panel, and the second output: the self-detection and self-repair mechanism has a decision mechanism for the transmission and determination. When the result of the judging mechanism is bad, the driving circuit is self-repaired by outputting the normal output signal to the display board. The power supply is used to detect the output of the driving circuit in the display device of the present invention. The defect of the road can be repaired by the defect in the (four) road. 修复 The display of the present invention, the above-mentioned driving circuit should have a ready output circuit capable of outputting the output of No. 4 to the display panel, The self-detecting and self-repairing mechanism has a switching mechanism that switches the output signal from the above-mentioned defective output circuit to the preparatory output circuit from the above-mentioned preliminary output circuit when the above-mentioned judgment result is defective. The output signal is used as an output signal to the display panel. According to the above configuration, the first driving circuit has an output (four). The preparatory output circuit of the panel is the same as the output circuit, and the image data can be converted into a gray scale voltage and output as an output signal for driving the display panel. a Further, according to the above configuration, self-detection and self-repair The mechanism has a mechanism for switching the output circuit determined to be defective by the judgment mechanism to the preparatory output circuit. The mechanism of the display device of the present invention may be defective in the case where the output circuit is defective. The output circuit is switched to the preliminary output circuit. The display device of the present invention preferably has an output signal from the output circuit and from the preliminary output circuit. The comparison means for comparing the output signals, and determining whether the output circuit is defective based on the result of the comparison Φ of the comparison means. According to the above configuration, the "determination means has a comparison means. Further, the comparison means outputs signals from the output circuit, and Prepare the output of the output circuit The comparison means determines whether the output circuit is defective or not based on the comparison result of the comparison means. Thus, in the display device of the present invention, the output can be determined by comparing the output of the output circuit with the output of the preliminary output circuit. In addition, the display device of the present invention preferably further has a control mechanism for controlling an input signal input to the output circuit and the preliminary output circuit, in a simple configuration. The control unit inputs an input signal different in size from the output circuit and the preliminary output circuit, and outputs an expected value of the comparison result from the comparison means corresponding to the input signal different in size. When the comparison result differs from the above-described expected value, it is determined that the output circuit is defective. According to the above configuration, the control means controls the input signals input to the output circuit and the preliminary output circuit, and outputs input signals of different sizes. 143488.doc 201030412 Further, the control unit outputs an expected value of the comparison result from the comparison means corresponding to the input signal of a different magnitude. Further, the judging means judges that the output circuit is defective when the actual comparison result from the comparison means is different from the expected value from the control means. Eight bodies and so on, for example, input the input signal of the gray scale m to the output circuit, and input the round-in signal of the gray scale m+1 to the preliminary output circuit. Furthermore, the gray scale voltage of the gray scale claw is grayscale m+1. The voltage of the gray scale voltage is lower. Here, if the output circuit is normal, the comparison mechanism outputs a signal indicating a higher gray scale voltage input from the preparatory wheel circuit. On the other hand, there is a defect in the output circuit 'even if input When the signal of the gray scale m is output and the output circuit can only output a higher gray voltage, the comparison mechanism outputs a signal indicating a higher gray scale voltage input from the output circuit. Thus, in the driving circuit of the present invention, the comparison mechanism Comparing the gray-scale voltage outputted from the wheel-out circuit and the preliminary output circuit, and outputting the signal when there is a defect in the output circuit and when there is no defect, the ^^, the judgment is based on self-comparison The signal output by the mechanism and (4) The output © circuit is not defective. Specifically, as described above, the input signal of the gray scale m is input to the output circuit, and the input of the gray output nrn is input to the preliminary output circuit. In the case of a signal, when the self-comparison mechanism input has a signal indicating that the gray-scale power a is higher from the output circuit, it is judged that the output material is good. The other side, the surface S from the comparison mechanism input has a representation from the preliminary output circuit. When the signal of the higher voltage is higher, the determining means determines that the output circuit is normal. Therefore, in the display device of the present invention, it is possible to easily detect that the output circuit 143488.doc -12· 201030412 is defective in the output circuit. The specific mechanism of the defect is self-repairing. In the display device of the present invention, the selection and approval medium up-and-down determination mechanism preferably includes a comparison mechanism for comparing the output signals from the plurality of output circuits and the two output circuits. And the root 摅 ^ ^ d .. determines whether the output circuit is defective according to the comparison result of the comparison means. Oblique: ? The above-mentioned configuration "determination mechanism includes a comparison mechanism. Further, the comparison mechanism

、1複數個輸出電路中之至少兩個輸出電路之輸出信號 ' 較而且，判定機構根據比較機構之比較結果而判 定輸出電路是否不良。 藉此’本發明之顯示裝置中’可藉由對輸出電路之輸出 進行比較而料輸出電路之不良，因此可以簡單之構成而 容易地檢測輸出電路之不良。 本發月之顯不裝置中’宜進一步包含對輸入至上述複數 個輸出電路中之至少兩個輸出電路之輸入信號進行控制的 控制機構’上述控制機構對上述至少兩個輸出電路輸入大 小相異之輸入信號，並且輸出與上述大小相異之輸入信號 相對應之、來自上述比較機構之比較結果之期望值，上述 判定機構於上述比較結果與上述期望值相異之情形時，判 定為上述至少兩個輸出電路中之任一者不良。 根據上述構成，控制機構對輸入至複數個輸出電路中之 至少兩個輸出電路之輸入信號進行控制，且輸入大小相異 之輸入信號。又，控制機構輸出與大小相異之輸入信號相 對應之、來自比較機構之比較結果之期望值。而且，判定 143488.doc •13- 201030412 機構於來自比較機構之實際之比較結果與來自控制機構之 期望值相異之情形時，判定為輸出電路不良。 具體而言，例如，於對^輸出電路與第2輸出電路此兩 個輸出電路輸入相異之輸入信號的情形時，對第丨輸出 路輸入㈣m之輸人信號’而對第2輪出電路輸人灰階㈣ 之輸入信號。再者，灰階爪之灰階電壓為較灰階…之灰 階電壓更低之電壓。於此，若第！輸出電路正常，則比較 機構輸出表示自第2輸出電路輸入之灰階電壓較高之信 ❹ 號。另一方面，於第i輸出電路存在缺陷，即便輸入灰階m 之仏號而第A出電路亦僅能輸出較高之灰階電壓之情形 時，比較機構輸出表示自第！輸出電路輸入之灰 高之信號。 =，本發明之驅動電路中，比較機構對自複數個輸出 中之至少兩個輸出電路輸出之灰階電壓進行比較，且 中存在缺陷之情形時及不存在缺陷之情形時， W出相異值之信號。 ❹ =，判定機構根據自比較機構輸出之信號而判定輸出 疋否不良。具體而言，於如上所述對第1輸出電路與 時2輸出電路此兩個輸出電路輪入相異之輸入信號之情形 輸出電路輸入灰階m+1之輸入作骑夕* }第2 構輪入有表示來自第時，當自比較機 2判定機構判定為第】輪出電路與第2輸出電路之至2 "出電路不良。此時’第1輸出電路與第2輸出電路被切 】43488.doc -14- 201030412 換為預備之輸出電路。另一方面，於自比較機構輪入有表 不來自第2輸出雷> 电路之灰階電壓較高之信號之情形時，判 定機構判定為輪出電路正常。 藉此本發明之顯示裳置中，包含容易地檢測輸出電路 缺陷之具體之機構’且於輸出電路中存在缺陷之情形時 能進行自我修復》 本發月之顯示裝置中，上述輸出電路宜包含運算放大器 參 Φ ㈣為輸出緩衝器，上述比較機構宜係包含上述運算放大 器而構成之比較器。 ,根據上述構成’輸出電路包含運算放大器來作為輪出緩 衝器。又，比較機構係包含運算放大器之比較器。 般而s，將來自驅動顯示面板之輸出電路之輸出信號 加以緩衝後輸出至輸出端子。於此，運算放大器藉由使自 身之輸出負反饋至自身之負極性輸入端子而成為電壓隨動 器電路，從而具有作為緩衝器電路之功能。 因此，如上所述，使比較機構為包含運算放大器而構成 之比較器，藉此使得運算放大器兼具對來自輸出電路之輸 出信號進行緩衝之緩衝器電路與比較機構此雙方之作用。 由此’本發明之驅動電路無需另行包含用以對來自輸出電 ^輸出信號進行緩衝之緩衝器電路，從而可發揮降低成 本之效果。 本發明之顯示裝置中，上述運算放大器宜於驅動顯示面 板之情形時作為電壓隨動器進行動作。 本發明之顯示裝置中，上述第丨驅動電路宜安裝於上述 143488.doc 201030412 顯示面板之1邊上’上述第2驅動電路宜於上述顯示面板 上，安裝於安裝有上述第1驅動電路之邊之對邊。 根據上述構成’上述第1驅動電路安裝於上述顯示面板 之1邊上，上述第2驅動電路於上述顯示面板上，安裝於安 裝有上述第1驅動電路之邊之對邊。 藉此’可節省顯示面板之厚度方向之空間，故可實現薄 型化。 本發明之顯示裝置中’上述第丨驅動電路及上述第2驅動 電路宜安裝於上述顯示面板之相同邊上。 根據上述構成’第i驅動電路及第2驅動電路安裝於顯示 面板之相同邊上。 藉此’可節省顯示面板之面方向之空間，故可實現小型 化0 本發明之顯示裝置中，上述第丨驅動電路、及上述第2驅 動電路宜係驅動上述顯示面板之源極線之源極驅動器。 進而，本發明之電視系統亦可為具有上述任一項中記載 之顯示裝置之構成。 [發明之效果] 本發明之顯示裝置之特徵在於包含：顯示面板；第1驅 動電路，其係驅動上述顯示面板之驅動電路，且具有對該 驅動電路之不良進行檢測並修復之自我檢測與自我修復機 構；及第2驅動電路，其係驅動上述顯示面板之驅動電 路’且不同於上述第1驅動電路。 因此，於自我檢測與自我修復機構對第i駆動電路之不 143488.doc -16 - 201030412 良進行檢測並修復時，即便於無法藉由第1驅動電路而驅 動顯示面板之情形時，亦可藉由第2驅動電路而驅動顯示 面板來於顯示面板中顯示映像。 【實施方式】 以下，根據圖式對本發明之實施形態進行說明。 [實施形態1] 以下，參照圖1〜圖17 ’對本發明之第1實施形態進行說 明。 (液晶電視400) 作為使用有顯示用驅動電路之顯示裝置之代表性者，可 舉出由液晶電視所代表之薄型電視。液晶電視（液晶顯示 裝置）係於顯示面板上安裝有複數個以半導體積體電路 (LSI(Large-SCale Integration，大型積體電路））製作成之驅 動電路而進行顯示。此種顯示裝置中，於顯示用驅動電路 產生不良之情形時，將會直接作為顯示不良而由使用者識 別出。於產生此種不良之情形時，必需迅速進行不良部位 之修理，理想的是儘可能於使用者使用之場所以短時間完 成修理。若為如對顯示信號進行處理般之控制基板，則因 以連接器與顯示面板進行連接而容易進行更換但因顯示 驅動用電路係直接連接於顯示面板而未以連接器等進行連 接故於使用者使用製品之場所難以進行更換。 因此，本申請人提出一種具有對顯示用驅動電路自身之 不良進行自我診斷自我修復之功能（自我檢測及自我修復 功能）的顯示驅動用電路（例如日本專利特願膽_i 3〇848、 143488.doc -17· 201030412 曰本專利特願2〇08-〇4864〇、曰本專利特願2〇〇8_〇48639以 及曰本專利特願2008·054130 :均未於本案申請前之確認 時間點公開）。 圖1係表示本發明之液晶電視4〇〇之構成之方塊圖。如圖 1所示’液晶電視400 包含 TFT-LCD(Thin Film Transist〇r_And the output signal of at least two of the plurality of output circuits is greater than, and the determining means determines whether the output circuit is defective based on the comparison result of the comparing means. According to the 'display device of the present invention', the output circuit can be defective by comparing the outputs of the output circuits, so that the defects of the output circuits can be easily detected with a simple configuration. The display device of the present month should further include a control mechanism for controlling an input signal input to at least two of the plurality of output circuits. The control mechanism has different input sizes to the at least two output circuits. And inputting a signal, and outputting an expected value of the comparison result from the comparison means corresponding to the input signal different in size, wherein the determining means determines that the at least two are different when the comparison result is different from the expected value Any of the output circuits is defective. According to the above configuration, the control means controls the input signals input to at least two of the plurality of output circuits, and inputs the input signals of different sizes. Further, the control means outputs an expected value of the comparison result from the comparison means corresponding to the input signal of a different magnitude. Further, it is judged that the output circuit is defective when the actual comparison result from the comparison means differs from the expected value from the control means in the determination 143488.doc • 13- 201030412. Specifically, for example, when a different input signal is input to the two output circuits of the output circuit and the second output circuit, the input signal of the (fourth) m is input to the second output circuit and the second round circuit is output. Enter the input signal of the grayscale (4). Furthermore, the gray scale voltage of the gray scale claw is a voltage lower than the gray scale voltage of the gray scale. Here, if the first! When the output circuit is normal, the comparison mechanism outputs a signal indicating a higher gray scale voltage input from the second output circuit. On the other hand, there is a defect in the ith output circuit. Even if the 第 of the gray scale m is input and the A-out circuit can output only a high gray-scale voltage, the comparison mechanism output is expressed from the first! The gray input signal of the output circuit input. In the driving circuit of the present invention, the comparing means compares the gray scale voltages outputted from at least two of the plurality of output circuits, and in the case where there is a defect and when there is no defect, the difference is W The signal of the value. ❹ =, the judging unit judges whether the output is defective or not based on the signal output from the comparison mechanism. Specifically, in the case where the first output circuit and the time 2 output circuit are rotated into different input signals as described above, the output circuit inputs the input of the gray scale m+1 as the yoke* } 2nd structure When the rounding is indicated from the first time, the comparator 2 determines that the second rounding circuit and the second output circuit are defective. At this time, the "first output circuit and the second output circuit are cut" 43488.doc -14- 201030412 are replaced by the preparatory output circuit. On the other hand, when the self-comparing mechanism is in the case where there is a signal indicating that the gray scale voltage of the second output lightning > circuit is high, the determining means determines that the rounding circuit is normal. Therefore, in the display device of the present invention, the specific mechanism that easily detects the defect of the output circuit is included, and the self-repair can be performed when there is a defect in the output circuit. In the display device of the present month, the output circuit preferably includes The operational amplifier reference Φ (4) is an output buffer, and the comparison mechanism is preferably a comparator including the above operational amplifier. According to the above configuration, the output circuit includes an operational amplifier as a wheel-out buffer. Further, the comparison mechanism is a comparator including an operational amplifier. Generally, the output signal from the output circuit that drives the display panel is buffered and output to the output terminal. Here, the operational amplifier functions as a buffer circuit by negatively feeding back its own output to its own negative input terminal and becoming a voltage follower circuit. Therefore, as described above, the comparator is a comparator including an operational amplifier, whereby the operational amplifier functions as both a buffer circuit for buffering the output signal from the output circuit and a comparator. Therefore, the drive circuit of the present invention does not need to separately include a buffer circuit for buffering the output electric output signal, thereby achieving the effect of reducing the cost. In the display device of the present invention, the operational amplifier is preferably operated as a voltage follower when the display panel is driven. In the display device of the present invention, the second driving circuit is preferably mounted on one side of the display panel of the above-mentioned 143488.doc 201030412. The second driving circuit is preferably mounted on the display panel and mounted on the side of the first driving circuit. On the opposite side. According to the above configuration, the first driving circuit is mounted on one side of the display panel, and the second driving circuit is mounted on the display panel on the side opposite to the side on which the first driving circuit is mounted. Thereby, the space in the thickness direction of the display panel can be saved, so that the thickness can be reduced. In the display device of the present invention, the second driving circuit and the second driving circuit are preferably mounted on the same side of the display panel. According to the above configuration, the ith drive circuit and the second drive circuit are mounted on the same side of the display panel. Therefore, in the display device of the present invention, the second driving circuit and the second driving circuit are preferably driven to source the source line of the display panel. Extreme drive. Furthermore, the television system of the present invention may be configured as any of the display devices described in any one of the above. [Effect of the Invention] The display device of the present invention includes: a display panel; a first driving circuit that drives the driving circuit of the display panel, and has self-detection and self-detection and repair of the defect of the driving circuit a repair mechanism; and a second drive circuit that drives the drive circuit of the display panel and is different from the first drive circuit. Therefore, when the self-detection and self-healing mechanism detects and repairs the illuminating circuit 143488.doc -16 - 201030412, even if the display panel cannot be driven by the first driving circuit, The display panel is driven by the second drive circuit to display an image on the display panel. [Embodiment] Hereinafter, embodiments of the present invention will be described based on the drawings. [Embodiment 1] Hereinafter, a first embodiment of the present invention will be described with reference to Figs. 1 to 17'. (Liquid Crystal TV 400) As a representative of a display device using a display drive circuit, a thin type television represented by a liquid crystal television can be cited. In a liquid crystal display (liquid crystal display device), a plurality of driving circuits fabricated by a semiconductor integrated circuit (LSI (Large-SCale Integration)) are mounted on a display panel and displayed. In such a display device, when a failure occurs in the display drive circuit, it is directly recognized by the user as a display failure. In the event of such a defect, it is necessary to quickly repair the defective part, and it is desirable to complete the repair in a short time as much as possible at the place where the user uses it. In the case of controlling the substrate as the display signal is processed, the connector is easily connected to the display panel, but the display driving circuit is directly connected to the display panel and is not connected by a connector or the like. It is difficult to replace the place where the product is used. Therefore, the present applicant has proposed a display driving circuit having a self-diagnosis self-repair function (self-detection and self-repair function) for the failure of the display drive circuit itself (for example, Japanese Patent Special Purpose _i 3〇848, 143488) .doc -17· 201030412 曰 专利 专利 特 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 639 Point public). BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the construction of a liquid crystal television 4 of the present invention. As shown in Figure 1, 'LCD TV 400 contains TFT-LCD (Thin Film Transist〇r_

Liquid Crystal Display，薄膜電晶體液晶顯示器）模組（顯 示部）9〇、開關按鈕401、DVD裝置402、hdd裝置403、以 及DVD與HDD控制裝置404。進而，顯示部9〇包含源極驅 動器（驅動電路、積體電路）l〇a、預備源極驅動器1〇b、 TFT-LCD面板（顯示面板）8〇、閘極驅動器99以及控制器 1〇〇。而且，源極驅動器l〇a即積體電路1〇a為上述之具有 自我檢測及自我修復功能之顯示用驅動用電路、再者，預 備源極驅動器10b即預備積體電路1〇b亦可為具有自我檢測 及自我修復功能之構成。又，以下，於僅記作積體電路1〇 或源極驅動器10之情形時，表示積體電路i 〇a及J 〇b即源極 驅動器10a及10b之總稱。 以下，對顯示部90中之自我檢測及自我修復之基本動作 進行說明之後，對液晶電視4〇〇中之自我檢測及自我修復 之特徵性構成、即以不會給使用者造成產生故障之誤解之 方式而可執行自我檢測及自我修復之構成進行具體說明。 (顯示部90) 首先，參照圖2，對本發明之顯示部90之概略構成進行 說明。圖2係表示顯示部9〇之概略構成之方塊圖。如圖之所 不，顯不部90包含顯示面板8〇、及根據自外部輸入之灰階 M3488.doc -18- 201030412 貝料而對顯示面板80進行驅動之顯示驅動用半導體積體電 路（以下稱為積體電路或源極驅動器）1〇。又，源極驅動器 即積體電路10(驅動電路）包含切換電路6〇(自我檢測與自我 修復機構、切換機構）、切換電路61(自我檢測與自我修復 機構、切換機構）、輸出電路區塊30(輸出電路）、預備輸出 電路區塊40(預備輸出電路）以及比較判定電路5〇(比較機 構、判定機構、自我檢測與自我修復機構）。又，顯示面 板80包含施加有來自積體電路1〇之灰階電壓之像素7〇。 其次，對顯示部90之基本動作進行說明。首先，就顯示 邛90而s ，作為基本動作而包含兩個基本動作。具體而 。，顯示部90包含以下兩個基本動作：積體電路1〇將自外 部輸入之灰階資料轉換為灰階電壓（輸出信號），根據該灰 階電壓而於顯示面板80上顯示影像之一般動作；及對積體 電路10中所包含之輸出電路區塊3〇是否不良進行檢測，於 輸出電路區塊30存在不良之情形時，積體電路1〇對自身進 行自我修復之自我檢測修復動作。 以下，對積體電路10所進行之自我檢測修復動作之概略 加以說明。首先，於進行自我檢測修復動作之情形時，自 外部經由切換電路61而將動作確認用之灰階資料輸入至輸 出電路區塊30與預備輸出電路區塊4〇。 輸出電路區塊30及預備輸出電路區塊4〇之各自將所輸入 之灰階資料轉換為灰階電壓並輸出至比較判定電路。比較 判定電路5 0將來自輸出電路區塊之灰階電壓與來自預備輸 出電路區塊之灰階電壓進行比較’根據該比較結果而對輸 143488.doc 201030412 出電路區塊是否不良進行判定β 進而，比較判定電路50將表示輸出電路區塊是否不良之 判定結果(不良檢測資訊)輸出至切換電路6 i及切換電路 6〇。切換電路61根據來自比較判定電路5〇之判定結果，而 切換來自外部之灰階資料之輸出目的地。另一方面，切換 電路60中自輸出電路區塊3〇及預備輸出電路區塊4()之各自 輸入有灰階電壓後，根據來自比較判定電路之判定結果， 而自所輸入之灰階電壓中選擇輸出至顯示面板8〇之灰階電 壓。 若加以更具體地說明，切換電路61中輸入有表示輸出電 路區塊30為不良之狀結果之後，將與輸出至判定為不良 之輸出電路區塊30之灰階資料相同的灰階資料亦輸入至預 備輸出電路區塊40。另一方面，切換電路6〇中輪入有表示 輸出電路區塊30為不良之判定結果之後，將來自預備輸出 電路40之灰階電壓代替來自判定為不良之輸出電路區塊 之灰階電壓而輸出至顯示面板8〇。藉此，積體電路1〇中， 即便輸出電路區塊30變為不良，仍可代替其而使用預備輪 出電路區塊，將正常之灰階電壓輸出至顯示面板8〇。 如上所述，本實施形態之積體電路1〇包含比較判定電路 50、切換電路6〇以及切換電路61，藉此可對自身之不良進 行檢測，進而可對自身之不良進行自我修復。換言之，積 體電路10包含對自身之不良進行檢測、進而對自身之不良 進行自我修復之自我修復電路（自我修復機構）。再者下 文對源極驅動器1〇即積體電路10之構成及自我檢測以及自 143488.doc -20· 201030412 我修復動作之詳細内容加以敍述。 (自我檢測動作開始開關） 圖3係表示液晶電視400之外觀之圖。如圖3所示，液晶 電視400包含用以使自我檢測動作開始之開關按鈕4〇丨（指 示機構）。以下，對開關按鈕401進行詳細說明。 圖4係表不構成液晶電視400中所包含之積體電路1〇之輸 出電路區塊30產生異常時的顯示之一例之圖。如圖4所 示，於輸出電路區塊30存在異常之情形時，顯示中存在縱 w 線。 通常，源極驅動器於作為LSI出廠時，充分地進行了功 能測試，於顯示裝置中亦充分進行了顯示之確認，因此產 生顯不異常之可能性非常低。即，於顯示裝置之一般使用 範圍内，產生顯示不良之可能性非常低。然而，有時因突 發性因素例如製造驅動器時之異物混入或損傷而導致於輸 出信號之路徑中產生之損壞，會於顯示裝置之使用期間擴 • 大而使得源極驅動器之輸出電路產生異常，從而引起顯示 不良。因此’源極驅動器必需進行輸出電路區塊之不良之 自我檢測。於此，亦考慮有例如於每次電源接通時進行輪 •出電路區塊之自我檢測之構成，但如上所述，由於產生顯 不不良之可能性非常低，因此源極驅動器無需以如此高之 頻率進行輸出電路區塊之自我檢測。 因此，液晶電視400中，包含用以指示自我檢測及自我 修復之開始之開關按鈕401。藉此，使用者可於任意之時 間使液晶電視4〇〇中之自我檢測及自我修復開始β 143488.doc -21· 201030412 圖5係表示液晶電視400中之自我檢測及自我修復動作之 不例之圖，圖5(a)係表示自我檢測及自我修復動作開始前 之液晶電視400之圖，圖5(b)係表示自我檢測及自我修復動 作進行中之液晶電視400之圖，圖5(c)係表示自我檢測及自 我修復動作結束後之液晶電視400之圖。 如圖5(a)所示，於產生液晶電視4〇〇之畫面中存在縱線之 顯示不良之情形時，使用者按下開關按鈕4〇1。藉此，液 晶電視400中開始進行自我檢測及自我修復動作。自我檢 測及自我修復動作開始後，如圖5(b)所示，顯示自液晶電 視400之畫面暫時消失。於此期間，源極驅動器1〇即積體 電路10進行自我檢測，自輸出電路區塊3〇中找出不良之輸 出電路區塊冑’調換不良之輸出電路區塊與預備輸出電路 區塊40。然後，自我檢測及自我修復動作結•束之後如圖 5(c)所不，液晶電視4〇〇再次進行顯示。此時，將不良之輸 出電路區塊更換成正常之預備輸出電路區塊，從而顯示不 良消失。 再者，如上所述’按下開關按鈕4〇1即接通開始開關 後，如圖5(b)所示，顯示暫時消失。因此，於使用者可能 誤解為故障之情形時，將該現象清楚記載於使用說 ^ 曰 中，並且可於進行自我檢測及自我修復動作之期間由顯示 面板80(通知機構）於畫面上顯示暫時消失顯示之内容，或 者亦可為藉由揚聲器（通知機構）以聲音通告等進行通知後 關閉顯示之構成。 藉此，液晶電視400申，無需於每次電源接通時進行自 143488.doc -22- 201030412 我檢測及自我修復，因此與每次 ..» . ^ 电，原接通時均進行自我檢 測及自我修復之構成相比，縮 .L j目電源接通至進行顯示 為止之時間，並且亦節約了自我檢測所消耗之電力。 • 再者，亦可將開關按㈣1用作液晶電視400自身之维護 用之開關。例如於按下開關按鈕4〇1之情形時，控制器 =魏表顯示控制機構)將液晶電視彻之維護功能表(例 如時鐘叹定、畫面之色調整、畫 杜一 _ 畺面之調整等操作功能表） •=不於顯示面板8。上。圖6係表示液晶電視_中之維護功 能表之顯示例之圖。該維罐 _ 維m表巾設置有進行自我檢測 自我修復之功能表’於產生顯示不良之情形時可進行選 使用者自顯不於顯示面板8G上之維護功能表中 選擇開始自我檢測及自我修復動作之功能表（圖崎示之例 中為「3.畫面之調整，、始 登」）後，開始進行源極驅動器1〇a中之 自我檢測及自我修復動作。進而，於已選擇自我檢測及自 我Ο復之If开/時，以晝面顯示或聲音通告等通知顯示暫時 豢 肖失之後’開始進行自我檢測及自我修復動作。 又’本實施形態中’表示將開關按鈕4〇ι設置於液晶電 視400上之構成’但亦可為將開關按鈕術設置於遙控器上 之構成。即，按下設置於遙控器上之開關按紐401後，對 液曰曰電視400發送指示進行自我檢測及自我修復之信號， 於液明電視400中，根據所接收之信號，進行驅動電路之 自我檢測及自我修復。 (預備源極驅動器） 圖7係表示液晶電視4〇〇中之自我檢測及自我修復動作之 143488.doc -23· 201030412 示例之圖，圖7(a)係表示自我檢測及自我修復動作開始前 之液晶電視400之圖，圖7(b)係表示自我檢測及自我修復動 作進行中之液晶電視400之圖，圖7(c)係表示自我檢測及自 我修復動作結束後之液晶電視400之圖。 如圖7(b)所示，液晶電視400於自我檢測及自我修復進 行中，可進行自我檢測及自我修復進行中之意思之畫面顯 示，而向使用者通知當前之狀況。再者，因液晶電視400 於自我檢測及自我修復動作進行中將源極驅動器即積體電 路10與液晶面板之連接電性切斷，故無法藉由積體電路10 而進行圖7(b)所示之自我檢測及自我修復進行中之意思之 畫面顯示。因此，液晶電視400包含用以進行圖7(b)所示之 畫面顯示之預備源極驅動器，於自我檢測及自我修復動作 進行中，使用預備源極驅動器進行自我檢測及自我修復進 行中之意思之畫面顯示。 圖8係表示構成液晶電視400之TFT-LCD模組即顯示部90 中安裝有對顯示面板80進行驅動之源極驅動器10a之示例 的圖。如圖8所示，顯示部90包含源極驅動器10a、閘極驅 動器 99、FPC(Flexible Printed Circuit，撓性印刷電路）（薄 膜電纜）98、PWD(Printed Wiring Board，印刷電路板）（印 刷基板）97、玻璃基板96、源極線95、閘極線94、TFT (Thin Film Transistor，薄膜電晶體）93、像素92以及對向 電極91。 玻璃基板96上形成有源極線95、閘極線94、TFT 93、像 素92以及對向電極91而構成液晶面板80。而且，源極驅動 143488.doc -24- 201030412 器10a與閘極驅動器99分別安裝於液晶面板80之玻璃基板 96之一邊上。源極驅動器i〇a經由源極線95而將顯示電壓 即表示圖像之灰階電壓傳輸至像素92。閘極驅動器99經由 閘極線94，而供給表示TFT 93之導通時序即將灰階電壓傳 輸至像素之時序之閘極信號。源極驅動器l〇a與閘極驅動 器99之輸入端連接於印刷基板97，經由印刷基板97之配線 而提供控制信號或電源電壓以及GND(接地）。控制信號或 電源電壓以及GND等係自經由薄膜電纜98而連接之控制基 板（未圖示）即控制器1〇〇進行供給。 如上所述’顯示部90亦可成為包含預備源極驅動器之構 成°圖9係表示構成液晶電視4〇〇之tFt-LCD模組即顯示部 90中安裝有對顯示面板80進行驅動之源極驅動器10a及預 備源極驅動器l〇b之示例的圖。圖9中，源極驅動器i〇a(第 1驅動電路）安裝於構成顯示面板80之玻璃基板96之一邊。 又’預備源極驅動器l〇b(第2驅動電路）安裝於源極驅動器 1〇a之對邊’且與源極驅動器l〇a同樣地，於輸入側連接於 印刷基板97而供給有控制信號等。 又’亦可以圖1〇〜圖12所示之安裝形態，安裝源極驅動 器即源極驅動器1〇a及1〇b。圖1〇係表示使用捲帶式載體 89 ’將具有自我檢測及自我修復功能之源極驅動器1如與 預備源極驅動器1〇b並聯安裝於玻璃基板96上之狀態的概 略圖。 圖10中’對於具有與構成圖8及圖9所示之顯示部90之構 件相同功能之構件附上相同之編號。如圖1〇所示，源極驅 143488.doc •25· 201030412 動器10a及預備源極驅動器1 〇b係於輸入側連接於印刷基板 97’於輸出侧連接於構成顯示面板之玻璃基板96。於如 圖10所示安裝成筒狀之情形時，源極驅動器10a及源極驅 動器10b均可連接於印刷基板97，且可自共用之基板97供 給輸入信號。 圖11係表示將圖10所示之捲帶式載體89打開之狀態之 圖。如圖11所示，源極驅動器10a係以除去了捲帶式載體 89之薄膜基材83之元件孔部87而連接於輸入側配線88及輸 出侧配線86。又’預備源極驅動器1 〇b係與源極驅動器1 〇a 朝向相反方向地連接於薄膜基材83之輸入側配線88及輸出 側配線86。如圖U所示，薄膜基材83中，藉由將源極驅動 器10a與預備源極驅動器1〇b安裝成表背面相反，而於捲帶 式載體89上可共用地連接輸出端子。藉此，如圖所示， 源極驅動器10a及源極驅動器10b可安裝於構成顯示面板8〇 之玻璃基板96之相同邊。 圖12係表示自方向A觀察圖n所示之安裝有源極驅動器 l〇a及l〇b之捲帶式載體89的俯視圖。如圖n所示，於捲帶 式載體89之兩端形成有連接於輸入側配線8S之輸入端子 及動作切換輸入端子82。通常對動作切換輸入端子82輸入 「L」信號後源極驅動器10a造行動作，顯示部9〇中進行一 般之顯示。此時，預備源極驅動器1〇b不進行動作。與此 相對，於源極驅動器10a中進行自我檢測及自我修復動作 之情形時’控制器(控制基板)將「H」信號輸入至動作切 換輸入端子82 *藉此， 我檢 源極驅動器l〇a中開始進行 143488.doc •26- 201030412 測及自我修德&从 並且預備源極驅動器l〇b開始動作， 於顯示部9〇中谁# 6 運仃自我檢測及自我修復動作進行中音思 之顯示。 再者目預備源極驅動n 1()b χ I $㈣$ < _ $ _ 可故，、亦可由灰階數較少之便宜之驅動器所構成。例如 於源極驅動器10a可顯示1〇24灰階之情形時，亦可使用8灰 階之驅動器作為預備源極驅動器⑽。 入Liquid Crystal Display, thin film transistor (liquid crystal display) module (display portion) 9A, switch button 401, DVD device 402, hdd device 403, and DVD and HDD control device 404. Further, the display unit 9A includes a source driver (drive circuit, integrated circuit) 10a, a preliminary source driver 1B, a TFT-LCD panel (display panel) 8A, a gate driver 99, and a controller 1A. Hey. Further, the source driver 10a, that is, the integrated circuit 1A is the above-described display driving circuit having a self-detecting and self-repairing function, and the preparatory source driver 10b, that is, the preliminary integrated circuit 1b can also be used. It is composed of self-testing and self-healing functions. In the following, when only the integrated circuit 1 or the source driver 10 is referred to, the integrated circuits i 〇 a and J 〇 b are collectively referred to as the source drivers 10a and 10b. Hereinafter, after describing the basic operations of self-detection and self-repair in the display unit 90, the characteristic configuration of the self-detection and self-repair in the liquid crystal television, that is, the misunderstanding of not causing a malfunction to the user. The method of performing self-detection and self-repair can be specifically described. (Display Unit 90) First, a schematic configuration of the display unit 90 of the present invention will be described with reference to Fig. 2 . Fig. 2 is a block diagram showing a schematic configuration of the display unit 9A. As shown in the figure, the display unit 8 includes a display panel 8A and a display driving semiconductor integrated circuit that drives the display panel 80 based on the externally input grayscale M3488.doc -18-201030412 beaker (hereinafter It is called an integrated circuit or a source driver). Further, the source driver, that is, the integrated circuit 10 (drive circuit) includes a switching circuit 6 (self-detection and self-repair mechanism, switching mechanism), a switching circuit 61 (self-detection and self-repair mechanism, switching mechanism), and an output circuit block. 30 (output circuit), preliminary output circuit block 40 (prepared output circuit), and comparison determination circuit 5 (comparison mechanism, determination mechanism, self-detection, and self-repair mechanism). Further, the display panel 80 includes pixels 7A to which the gray scale voltage from the integrated circuit 1 is applied. Next, the basic operation of the display unit 90 will be described. First, 邛90 and s are displayed, and two basic actions are included as basic actions. Specifically. The display unit 90 includes the following two basic operations: the integrated circuit 1 converts the gray scale data input from the outside into a gray scale voltage (output signal), and displays the general motion of the image on the display panel 80 according to the gray scale voltage. And detecting whether the output circuit block 3〇 included in the integrated circuit 10 is defective, and when the output circuit block 30 is defective, the integrated circuit 1 performs a self-repairing self-repairing operation for itself. Hereinafter, the outline of the self-detection repair operation performed by the integrated circuit 10 will be described. First, when the self-detection repair operation is performed, gray scale data for operation confirmation is input from the outside to the output circuit block 30 and the preliminary output circuit block 4 via the switching circuit 61. Each of the output circuit block 30 and the preliminary output circuit block 4 converts the input gray scale data into a gray scale voltage and outputs it to the comparison determination circuit. The comparison decision circuit 50 compares the gray scale voltage from the output circuit block with the gray scale voltage from the preliminary output circuit block. 'According to the comparison result, the output block is determined to be defective β 488.doc 201030412 The comparison determination circuit 50 outputs a determination result (bad detection information) indicating whether or not the output circuit block is defective to the switching circuit 6i and the switching circuit 6A. The switching circuit 61 switches the output destination of the gray scale data from the outside based on the determination result from the comparison determination circuit 5A. On the other hand, in the switching circuit 60, after the gray scale voltage is input from each of the output circuit block 3 and the preliminary output circuit block 4 (), the gray scale voltage is input from the comparison result from the comparison determination circuit. The grayscale voltage output to the display panel 8〇 is selected. More specifically, after the switching circuit 61 inputs a result indicating that the output circuit block 30 is defective, the same gray scale data as the gray scale data outputted to the output circuit block 30 determined to be defective is also input. To the preliminary output circuit block 40. On the other hand, after the switching circuit 6 has a determination result indicating that the output circuit block 30 is defective, the gray scale voltage from the preliminary output circuit 40 is substituted for the gray scale voltage from the output circuit block determined to be defective. Output to the display panel 8〇. As a result, even if the output circuit block 30 becomes defective, the integrated circuit block can be used instead of the normal circuit voltage to output the normal gray scale voltage to the display panel 8A. As described above, the integrated circuit 1A of the present embodiment includes the comparison determination circuit 50, the switching circuit 6A, and the switching circuit 61, whereby the defect of itself can be detected, and the defect of itself can be self-repaired. In other words, the integrated circuit 10 includes a self-repairing circuit (self-repairing mechanism) that detects the defect of itself and repairs itself against the defect. Furthermore, the composition of the source driver 1 and the self-detection of the integrated circuit 10 and the details of the repair operation of 143488.doc -20· 201030412 will be described below. (Self-Detection Operation Start Switch) FIG. 3 is a view showing the appearance of the liquid crystal television 400. As shown in Fig. 3, the liquid crystal television 400 includes a switch button 4 (indicating means) for starting a self-detecting operation. Hereinafter, the switch button 401 will be described in detail. Fig. 4 is a view showing an example of a display when an abnormality occurs in the output circuit block 30 which does not constitute the integrated circuit 1 included in the liquid crystal television 400. As shown in Fig. 4, when there is an abnormality in the output circuit block 30, there is a vertical w line in the display. In general, when the source driver is shipped as an LSI, the function test is sufficiently performed, and the display is sufficiently confirmed in the display device. Therefore, the possibility of occurrence of abnormality is extremely low. That is, the possibility of display failure is extremely low within the general use range of the display device. However, sometimes the damage caused in the path of the output signal due to sudden factors such as foreign matter incorporation or damage during the manufacture of the driver may increase during the use of the display device, causing an abnormality in the output circuit of the source driver. , causing poor display. Therefore, the 'source driver must perform poor self-detection of the output circuit block. Herein, it is also considered that, for example, the self-detection of the wheel-out circuit block is performed every time the power is turned on, but as described above, since the possibility of occurrence of a defect is very low, the source driver does not need to be so. The high frequency performs self-detection of the output circuit block. Therefore, the liquid crystal television 400 includes a switch button 401 for indicating the start of self-detection and self-repair. Therefore, the user can self-detect and self-repair in the LCD TV at any time. β 143488.doc -21· 201030412 FIG. 5 shows an example of self-detection and self-repair in the LCD TV 400. Figure 5 (a) shows the LCD TV 400 before the start of self-detection and self-repair, and Figure 5 (b) shows the LCD TV 400 in the process of self-detection and self-repair, Figure 5 (Figure 5 ( c) is a diagram showing the LCD TV 400 after the self-test and self-repair actions are completed. As shown in Fig. 5(a), when there is a display failure of the vertical line in the screen on which the liquid crystal television 4 is generated, the user presses the switch button 4〇1. Thereby, self-detection and self-repairing operations are started in the liquid crystal television 400. After the self-detection and self-repair actions are started, as shown in Fig. 5(b), the screen displayed from the liquid crystal television 400 temporarily disappears. During this period, the source driver 1 or the integrated circuit 10 performs self-detection, and the defective output circuit block 胄 'transformed bad output circuit block and the preliminary output circuit block 40 are found out from the output circuit block 3〇. . Then, after the self-detection and self-repair action are completed, as shown in Fig. 5(c), the LCD TV 4 is displayed again. At this time, the defective output circuit block is replaced with the normal preliminary output circuit block, so that the display disappears. Further, as described above, when the start button is turned on by pressing the switch button 4〇1, the display temporarily disappears as shown in Fig. 5(b). Therefore, when the user may misunderstand the situation as a failure, the phenomenon is clearly described in the usage statement, and the display panel 80 (notification means) can be temporarily displayed on the screen during the self-detection and self-repairing operations. The content of the display may be disappeared, or the display may be turned off by a notification by a speaker (notification means) by voice announcement or the like. Therefore, the LCD TV 400 does not need to be tested and self-repaired every time the power is turned on, so it is self-tested every time..». ^ Compared with the self-repairing structure, the power is turned on until the display is performed, and the power consumed by the self-detection is also saved. • In addition, the switch can be used as a switch for maintenance of the LCD TV 400 by pressing (4) 1. For example, when the switch button 4〇1 is pressed, the controller=Wei table display control mechanism) will completely maintain the LCD TV maintenance function table (for example, clock sigh, screen color adjustment, drawing Du _ 畺 之 adjustment, etc. Operation function table) •=Not for display panel 8. on. Fig. 6 is a view showing a display example of the maintenance function table in the liquid crystal television. The maintenance tank _ dimension m towel is provided with a self-test self-repair function table. In the case of a display failure, the user can select the user to display the self-detection and self-display in the maintenance function table on the display panel 8G. After the function table of the repair operation (in the example of the diagram, "3. Screen adjustment, start"), the self-detection and self-repair operation in the source driver 1A are started. Further, after the self-detection and the self-recovery of the If/on, the self-detection and self-repair actions are started after the notification of the face display or the voice announcement is displayed. Further, in the present embodiment, the configuration in which the switch button 4 is set on the liquid crystal television 400 is shown, but the switch button can be placed on the remote controller. That is, after pressing the switch button 401 provided on the remote controller, a signal for self-detection and self-repair is sent to the liquid helium television 400, and in the liquid crystal television 400, the drive circuit is driven according to the received signal. Self-testing and self-healing. (Prepared source driver) Fig. 7 is a diagram showing an example of self-detection and self-repair in a liquid crystal television 4 143488.doc -23· 201030412, and Fig. 7(a) shows the self-detection and self-repair actions before the start Figure of the LCD TV 400, Figure 7(b) shows the LCD TV 400 in the process of self-detection and self-repair, and Figure 7(c) shows the LCD TV 400 after the self-test and self-repair operation. . As shown in Fig. 7(b), in the self-detection and self-repair process, the liquid crystal television 400 can display a screen for self-detection and self-repair, and notify the user of the current situation. Further, since the liquid crystal television 400 electrically disconnects the connection between the integrated circuit 10 and the liquid crystal panel during the self-detection and self-repair operation, the integrated circuit 10 cannot be used in FIG. 7(b). The screen shown in the self-test and self-repair in progress is shown. Therefore, the liquid crystal television 400 includes a preliminary source driver for performing the screen display shown in FIG. 7(b), and performs self-detection and self-repair using the preliminary source driver during the self-detection and self-repairing operations. The screen is displayed. Fig. 8 is a view showing an example in which the source driver 10a for driving the display panel 80 is mounted in the display unit 90 which is a TFT-LCD module constituting the liquid crystal television 400. As shown in FIG. 8, the display unit 90 includes a source driver 10a, a gate driver 99, an FPC (Flexible Printed Circuit) (film cable) 98, and a PWD (Printed Wiring Board) (printed circuit board). 97, a glass substrate 96, a source line 95, a gate line 94, a TFT (Thin Film Transistor) 93, a pixel 92, and a counter electrode 91. On the glass substrate 96, a source line 95, a gate line 94, a TFT 93, a pixel 92, and a counter electrode 91 are formed to constitute a liquid crystal panel 80. Further, the source driver 143488.doc - 24 - 201030412 device 10a and the gate driver 99 are respectively mounted on one side of the glass substrate 96 of the liquid crystal panel 80. The source driver i〇a transmits a display voltage, that is, a grayscale voltage representing an image, to the pixel 92 via the source line 95. The gate driver 99 supplies a gate signal indicating the timing at which the on-time of the TFT 93 is transmitted to the pixel by the on-time of the TFT 93 via the gate line 94. The source driver 10a and the input terminal of the gate driver 99 are connected to the printed circuit board 97, and a control signal or a power supply voltage and GND (ground) are supplied via the wiring of the printed substrate 97. The control signal, the power supply voltage, and the GND are supplied from the controller 1A, which is a control board (not shown) connected via the film cable 98. As described above, the display unit 90 may be configured to include the preliminary source driver. FIG. 9 shows that the display unit 90, which is a tFt-LCD module constituting the liquid crystal television, is mounted with a source for driving the display panel 80. A diagram of an example of the driver 10a and the preliminary source driver 100b. In Fig. 9, the source driver i〇a (first driving circuit) is mounted on one side of the glass substrate 96 constituting the display panel 80. Further, the 'prepared source driver 10b (second driving circuit) is mounted on the opposite side of the source driver 1a, and is connected to the printed circuit board 97 on the input side in the same manner as the source driver 10a. Signals, etc. Further, the source drivers of the source drivers 1a and 1b may be mounted in the mounting form shown in Figs. 1 to 12 . Fig. 1 is a schematic view showing a state in which a source driver 1 having a self-detecting and self-healing function is mounted on a glass substrate 96 in parallel with a preparatory source driver 1b using a tape carrier 89'. In Fig. 10, the same reference numerals are attached to the members having the same functions as those of the members constituting the display portion 90 shown in Figs. 8 and 9. As shown in FIG. 1A, the source driver 143488.doc • 25·201030412 actuator 10a and the preparatory source driver 1 〇b are connected to the printed substrate 97' on the input side and connected to the glass substrate 96 constituting the display panel on the output side. . When mounted in a cylindrical shape as shown in Fig. 10, the source driver 10a and the source driver 10b may be connected to the printed circuit board 97, and the input signal may be supplied from the shared substrate 97. Fig. 11 is a view showing a state in which the tape carrier 89 shown in Fig. 10 is opened. As shown in Fig. 11, the source driver 10a is connected to the input side wiring 88 and the output side wiring 86 by the element hole portion 87 of the film substrate 83 from which the tape carrier 89 is removed. Further, the preparatory source driver 1 〇b is connected to the input side wiring 88 and the output side wiring 86 of the film substrate 83 in the opposite direction to the source driver 1 〇a. As shown in Fig. U, in the film substrate 83, the source driver 10a and the preliminary source driver 1b are mounted opposite to each other on the front and back sides, and the output terminals are commonly connected to the tape carrier 89. Thereby, as shown in the figure, the source driver 10a and the source driver 10b can be mounted on the same side of the glass substrate 96 constituting the display panel 8A. Fig. 12 is a plan view showing the tape carrier 89 to which the source drivers 1a and 10b are mounted as viewed from the direction A. As shown in Fig. n, an input terminal connected to the input side wiring 8S and an operation switching input terminal 82 are formed at both ends of the tape carrier 89. Normally, the source driver 10a is operated by inputting an "L" signal to the operation switching input terminal 82, and the display unit 9A performs general display. At this time, the preparatory source driver 1〇b does not operate. On the other hand, when the self-detection and self-repair operation are performed in the source driver 10a, the controller (control board) inputs the "H" signal to the operation switching input terminal 82. * By this, I check the source driver. Start in a. 143488.doc •26- 201030412 Test and self-cultivation & from the start of the source drive l〇b, in the display section 9〇 Who # 6 仃 self-detection and self-healing action for the midrange Think of the display. In addition, the source driver n 1()b χ I $(4)$ < _ $ _ can be used, or it can be composed of a cheaper driver with a smaller number of gray levels. For example, when the source driver 10a can display a gray scale of 1 〇 24, an 8 gray scale driver can also be used as the preliminary source driver (10). Enter

_ 動器i〇b之顯示控制係與源極驅動器10a之控 制=樣地：亦可根據自控制器發送之控制信號及顯示用資 料號來進行’但若於預備源極驅動器⑽之内部設置有 顯不用讀、體並縣記憶有顯示内容，則無需將顯示用資 料=終持續供給至預備源極驅動器隱。^於預備源極驅 動态10b進行顯示之前使顯示用記憶體記憶顯示用資料， 則可使用記憶體内之顯示f料來進行顯示控制。若決定了 顯不内今，則使顯示用記憶體成為R〇M(Read 0nly M_ry’唯讀記憶體）或〇Tp(〇ne Time pr〇m ,—欠性可 編程記憶體)而使顯示内容成為固定後，&需自外部將顯 不資料傳輸至預備源極驅動器1〇b，能夠以簡單之 易地進行顯示控制。 成 (旗標儲存用外部記憶體） 於自我檢測及自我修復中，由比較判定電路5()進行輸出 電路區塊30之；^判定，判定結果㈣為敎旗標（不良 檢測資訊）而記憶於源極驅動器内之記憶體中。顯示部 根據該判定旗標進行自我純，較於未對餘驅動器供 143488.doc •27· 201030412 給電源之情形時’亦需要預先記憶判定旗標。gP，若失去 判定旗標，則無法指定不良之輸出電路，因此需要再次進 行自我檢測，而使得每次之自我修復動作需要較長之時 間。 若源極驅動器之記憶體為非揮發性則不存在問題，但將 非揮發性之記憶體内置於源極驅動器内會引起成本上升， 因此通常，源極驅動器内之記憶體通常為揮發性之記憶 體。因此，於切斷電源時，記憶於源極驅動器之内部之記 憶體的判定旗標會消失。 因此，液晶電視400中，包含如下構造：於切斷電源 時將源極驅動器之判定旗標之内容傳輸至外部之記憶體 81 (。己隐裝置）’於電源接通時，反之將判定旗標自外部之 s己憶體81讀入源極驅動器内之記憶體中。 圖13係表示構成液晶電視4〇〇tTFT_LCD模組即顯示部 9〇中，將記憶體81安裝於連接著源極驅動器1〇&之輸入端 之印刷基板97上之示例的圖。源極驅動器i 〇a包含：將内 部之各輸出電路區塊中所設置之判定旗標儲存用之揮發性 記憶體之值作為串列資料加以輸入輸出的串列1/〇 (inpm/〇utput，輸入/輸出）端子；用以設定向記憶體81之 資料之寫入的端子；以及設定自記憶體81之資料之讀出的 端子。 串列I/O端子連接於記憶體8丨，可於源極驅動 器10a之内 部之揮發性記憶體與外部之記憶體8丨之間進行資料之讀出 及讀入。 143488.doc -28- 201030412 於藉由使用者之操作或電源斷開之定時器等而將液晶電 視400之電源切斷時（即，顯示部9〇之電源切斷時），自控制 器1〇〇(寫入控制機構）’對設定向記憶體81之資料之寫入的 . 端子供給指示向記憶體81之資料之寫入的信號，且將源極 驅動器10a設定為向記憶體81寫入資料之狀態。然後，根 據來自控制器100之指示，將判定旗標之資料自源極驅動 器l〇a寫入至外部之記憶體81中，記憶體81記憶判定旗 φ 標。對各源極驅動器10a進行該操作而使所有源極驅動器 之判定旗標記憶於記憶體81中。 另一方面，於啟動電源時，自控制器1〇〇對設定自記憶 體81讀出資料之端子，供給指示自記憶體81讀出資料之信 號，且將源極驅動器l〇a設定為進行自記憶體81讀出資料 之狀態。藉此，自外部之記憶體81，將判定旗標之資料讀 入至源極驅動器10a中，源極驅動器1〇a之内部之揮發性記 憶體記憶判定旗標。對各源極驅動器1〇a進行該操作而使 • 判定旗標記憶於所有源極驅動器内部之記憶體中。然後， 切換電路60及6丨根據讀出之判定旗標，於不良之輪出電路 區塊30與預備之輸出電路區塊4〇之間進行切換，而進行源 極驅動器10a之自我修復。 .圖14係表示於構成液晶電視4〇〇2TFT_lcd模組即顯示 部90中，將記憶體81安裝於連接著源極驅動器丨如之輸入 端之印刷基板9 7上之另一例的圖。 圖U所示之構成中，將源極驅動器之用以輸人輸出源極 驅動器10a之判定旗標之資料的端子彼此連接，藉此可串 143488.doc -29- 201030412 列地寫出或讀入所安裝之源極驅動器之判定旗標全體。 再者，本實施形態中，記憶體81使用作為非揮發性之記 憶體之快閃記憶體，但亦可成為揮發性之ram。此時，作 為始終對RAM之電源供給電壓之電路構成’而需要設置有 防備突然之電源切斷之後備用之電容器或電池。 又，圖13及圖14之示例中，記憶體81設置於印刷基板97 上，但亦可為設置於例如控制基板等其他基板上並經由薄 膜電纜98而進行連接之構成。 其次，使用圖15對在顯示部90之電源斷開時進行自我檢 測之構成進行說明。圖15係表示於顯示部9〇之電源斷開時 進打源極驅動器10a之自我檢測之順序的流程圖。該構成 中，於電源接通時僅進行自我修復而不進行自我檢測，代 替此而於電源斷開時進行自我檢測。 顯示部90接通電源後（S1501)，自儲存有判定旗標之外 部5己憶體81，將判定旗標傳輸至源極驅動器J 内部之纪 憶體（S1502)。然後，源極驅動器1〇a根據該判定旗標進行 自我修復（S1503)後，開始於顯示面板8〇上進行顯示圖像 等之一般動作（S 1 504)。顯示部90於一般動作中，以—定 之時間間隔進行是否接收到電源斷開指令之判定 (S1505)。而且，顯示部90於未感測到電源斷開指令之期 間（S 1505 . No)，反覆進行是否接收到電源斷開指令之判 定。 而且，當顯示部90感測到自開關或遙控器對液晶電視 400(或顯示部90)發送了電源斷開之指令後（sl5〇5 : 143488.doc -30- 201030412 (疋)）Μ閉於顯示面板80上之圖像之顯示⑻遍)。此 時，不將顯示部90自身及包含顯示部9〇而構成之系統 之電源斷開。其次’顯示部9〇中，比較判 ._驅動器W之各輸出電路是否為不良進行判定^成 ―部90進行源極驅動器⑽之自我檢測，將表示判定結 果之内各之判定旗標保存於源極驅動器之内部之記情 ，中（S 1507)。然、後’對所有源極驅動器他判定自我檢測 0 是否結束（S1508)。於並非所有源極驅動 器10a均結束自我 檢測之情形時（S1508 : No(否）），於以5〇7中，對未進行自 我檢測之剩餘之源極驅動器1〇a亦同樣地反覆進行自我檢 測並將判定旗標儲存於内部之記憶體中之處理。於所有源 極驅動器10a結束自我檢測之情形時（sl5〇8:㈣，將源 極驅動器10a之内部之記憶體中所儲存的判定旗標健存於 源極驅動器1〇a之外部之非揮發性之記憶體81中（815〇9)。 繼而，將自我檢測之判定旗標儲存於源極驅動器1〇&之外 • 部之記憶體後，顯示部9〇將源極驅動器1〇a及周邊電路之 電源斷開（S1510)。 藉由以上處理，顯示部9〇中，於源極驅動器1〇&中所包 含之輸出電路區塊產生異常而產生顯示不良之情形時，將 電源斷開後再次接通電源，藉此恢復顯示。 (DVD裝置 402) 圖16係表示液晶電視4〇〇中之自我檢測及自我修復動作 之一例之圖’圖16(a)係表示自我檢測及自我修復動作前之 液晶電視400之圖’圖16(b)係表示自我檢測及自我修復動 143488.doc 31 201030412 作中之液晶電視400之圖，圖16(c)係表示自我檢測及自我 修復動作結束後之液晶電視400之圖。 如圖1所示，液晶電視400中搭載有DVD(Digital Versatile Disc or Digital Video Disc)裝置 402。DVD裝置 402具有利用DVD進行再生及錄影等之功能。液晶電視400 中，根據來自使用者之指示，DVD與HDD控制部404對 DVD裝置402(影像再生裝置）之各種動作進行控制。 DVD需要定期對讀出信號之磁頭進行清潔。因此，如圖 16(a)所示，***清潔碟片進行讀頭之清潔。DVD裝置402 偵測出清潔碟片之***後，根據與使用者之指示相對應之 來自DVD與HDD控制部404之控制信號而開始進行清潔動 作。 又，如圖16(a)所示，液晶電視400中產生有於顯示晝面 上存在縱線之不良。而且，液晶電視400之特徵在於如下 構成之方面，即於進行一體地包含之DVD裝置402之清潔 之時間點，一併進行源極驅動器1 〇a之自我檢測。若加以 更詳細地說明，則DVD與HDD控制部404自DVD裝置402接 收到表示已開始清潔之信號後，對控制器100供給表示開 始進行源極驅動器1 〇a之自我檢測及自我修復之指示之信 號。然後，根據來自控制器1〇〇之指示，源極驅動器l〇a開 始進行自我檢測及自我修復動作。再者，DVD裝置402亦 可為自液晶電視400獨立而設置之構成。 如圖16(b)所示，於進行通知正在清潔之意思之顯示的 情形時，對使用者而言之便利性提昇，但一般之圖像顯示 143488.doc -32- 201030412 用之源極㈣器1Qa會於進行清潔之同時進行自我檢判動 作，因此如上所述需要預先具有預備之源極驅動器⑽。 而且’將表示源極驅動器10a之自我檢測之判定結果的判 定旗標保持於源極驅動器10a之内部之記憶體中，源極驅 動器l〇a根據保持於内部之記憶體中之判定旗標而進行自 我修復動作。藉此，如圖16⑷所示，消除了於圖16⑷之 顯不畫面上存在縱線之不良。於電源斷開時，將上述判定 旗標自源極驅動器1 〇a之内部之記憶體儲存於外部之記憶 體81中，於接通電源時再次讀入至源極驅動器1〇&之内部 之記憶體中而再次進行自我修復。 (HDD裝置 403) 圖17係表示液晶電視400中之自我檢測及自我修復動作 之一例的圖，圖1 7(a)係表示自我檢測及自我修復動作前之 液晶電視400之圖，圖17(b)係表示自我檢測及自我修復動 作中之液晶電視400之圖，圖17(匀係表示自我檢測及自我 修復動作結束後之液晶電視400之圖。 如圖1所示’液晶電視4〇〇中内置有jjDD(Hard Disk Drive)裝置403。HDD裝置403具有利用HDD進行再生及錄 影等之功能。液晶電視400中’根據來自使用者之指示， DVD與HDD控制部404對HDD裝置403(影像再生裝置）之各 種動作進行控制。 HDD需要進行記憶區域之整理等（例如重組等之記憶區 域之優化或碟片之錯誤檢查等）之維護，HDD裝置403根據 與使用者之指示相對應之來自DVD與HDD控制部404之控 143488.doc •33- 201030412 制信號，開始維護動作。錢行維護中無法進行錄影及再 生因此HDD裝置4〇3之記憶區域之維護需要於使用者 不進行使用之時間進行。 因此，液晶電視400中，如圖17⑷所示，成為由使用者 指定不㈣之時間（例如深夜）並於所指定之時間進行维護 之構成。即’ _裝置具有可於預先設定之時刻進行 維護之計時器功能。又，如圖17⑷所示，液晶電視彻 中’產生於顯示畫面上存在縱線之不良。*且，液晶電視 400之特徵在於如下構成之方面，即於進行—體地包含之 腳之維叙時m騎源極驅㈣心之自我檢 測。若進行更詳細地說明，則DVD與HDD控制部404自 HDD農置4G3接收到表示已開始記憶區域之優化之信號 後’對控制器100供給表示已開始源極驅動器ι〇&之自我檢 測及自我修復之指示之信號。然、後，根據來自控制器1〇〇 之指示，源極驅動器心開始進行自我檢測及自我修復動 作再者HDD裝置403亦可為自液晶電視4〇〇獨立而設置 之構成。 自我檢測係於使用者不使用之時間進行，因此無需進行 正在維護HDD之意思之顯示，如圖17(b)所示關閉顯示亦 .、、、妨但亦考慮到使用者忘記正在進行維護HDD而欲使其 進行顯示之情形，因此亦可為搭載有上述預備之源極驅動 器l〇b而進行簡單之顯示之構成。 將表示自我檢測之結果之判定旗標保持於源極驅動器 之内部之記憶體中，根據該判定旗標而進行自我修復 143488.doc .34- 201030412 動作。圖17(c)係維護結束後再次進行顯示時之畫面之狀 態，告知使用者維護已結束。如圖17⑷所示，消除了圖 17(a)之顯示晝面上存在縱線之不良。 • 而且，於斷開電源時，將記憶於源極驅動器1〇a之内部 之記憶體中的判定旗標儲存於外部記憶體中，於接通電源 時再次讀入至源極驅動器10a内之記憶體中而再次進行自 我修復。 • (積體電路10之構成） 其次，參照圖18對本發明之源極驅動器1〇a之構成加以 說明。再者，如上所述，預備源極驅動器1〇b亦可成為較 源極驅動器10a更簡單之構成’但亦可成為與源極驅動器 l〇a相同之構成。以下，將可執行與源極驅動器1〇a相同之 自我檢測及自我修復動作之電路稱作積體電路丨〇而進行說 明。 圖18係表示積體電路1〇(驅動電路）之構成之說明圖。如 0 該圖所示’積體電路10包含：η個取樣電路6-1〜6-n(以下， 於總稱之情形時稱作取樣電路6)，其自灰階資料輸入端子 (未圖不）經由資料匯流排而輸入與η個液晶驅動用信號輸出 端子OUT1〜〇UTn(以下稱作輸出端子OUT1〜OUTn)之各自 . 相對應之灰階資料；η個保持電路7—^7^(以下，於總稱之 情形時稱作保持電路7) ; η個DAC電路8-1〜8-η(以下，於總 稱之情形時稱作DAC電路8)，其將灰階資料轉換為灰階電 壓信號；η個運算放大器1-1〜1_η(以下，於總稱之情形時稱 作運算放大器1)，其對來自DAC電路8之灰階電壓信號具 143488.doc -35· 201030412 有緩衝器電路之作用；η個判定電路3-1〜3-n(以下，於總稱 之情形時稱作判定電路3) ; η個判定旗標4-1〜4-n(以下，於 總稱之情形時稱作判定旗標4);以及η個上拉與下拉電路5· 1〜5-η(以下，於總稱之情形時稱作上拉與下拉電路勾。 進雨，如該圖所示，積艎電路10包含：根據test(測試） 信號而於ON(開）與OFF(關）之間進行切換之複數個開關 2a;根據test B信號而於〇]^與〇1?17之間進行切換之複數個 開關2b ;以及根據來自判定旗標4之輸出信號即 Flagl〜Flagn而於〇]^與〇1^之間進行切換之複數個開關 2c(連接切換機構）及2d(連接切換機構）。再者，開關。、 2b、2d係於輸入有「H」信號之情形時成為〇N，而於輸入 有「L」信號之情形時成為〇FF^另一方面，開關及係於 輸入有Η」k號之情形時成為off,而於輸入有「η」信 號之情形時成為ON。 又，積體電路10包含各為一個之如下電路：預備之取樣 電路26，預備之保持電路27 ;預備之DAC電路28(預備輸 出電路）；以及預備之運算放大器21。 再者，圖18中，取樣電路6、保持電路7以及DA(：電路8 相當於圖2所示之輸出電路區塊3〇，取樣電路％、保持電 路27以及DAC電路28相當於圖2所示之預備電路區塊4〇， 運算放大器1、判定電路3以及判定旗標4相當於圖2所示之 比較判定電路50，與輸出端子〇UT1〜〇UTn連接之開關2d 及開關2c相當於圖2所示之切換電路6〇，與取樣電路6連接 之開關2d相當於圖2所示之切換電路61。再者，圖18所示 143488.doc • 36 - 201030412 之積體電路ίο係經由輸出端子OUT1〜〇UTn而與圖2所示之 顯示面板80相連接，圖18中，省略了顯示面板8〇之圖示。 (積體電路10之一般動作） 其次’以下參照圖18對積體電路10中之將灰階電壓輸出 至顯示面板80(參照圖2)之一般動作進行說明。 首先，於一般動作之情形時，test信號為「L」，test β 信號成為「Η」。當test信號為「L」時，開關2a成為 OFF，開關2b成為ON。藉此，將來自未圖示之指標用移位 暫存器之信號即STR1〜STRn信號（以下，於總稱之情形時 稱作STR信號）輸入至對應之各取樣電路6。取樣電路6根據 所輸入之STR信號，自灰階資料輸入端子經由資料匯流排 而取付與自身相對應之灰階資料。保持電路7根據資料 LOAD信號’自取樣電.路6輸入取樣電路6所取得之灰階資 料。然後’ DAC電路8(輸出電路）自保持電路7輸入灰階資 料。DAC電路8將所輸入之灰階資料轉換為灰階電壓信號 後輸出至運异放大|§1(比較機構）之正極性輸入端子。於 此，因開關2b為ON，故運算放大器1之輸出成為向自身之 負極性輸入端子之負反饋。藉此，運算放大器1作為電壓 隨動器進行動作。藉此，運算放大器1對來自DAC電路8之 灰階電壓而具有緩衝器電路之作用，將輸入至自身之正極 性輸入端子之灰階電壓信號輸出至對應之輸出端子 OUT1〜OUTn。再者，於此，使開關2c為ON，使開關2(1為 OFF。下文對開關2c及2d之動作加以敍述。將上述之串聯 連接於每個輸出端子之、包含取樣電路6、保持電路7、 143488.doc • 37· 201030412 DAC電路8以及運算放大器1之區塊作為輸出電路區塊，該 輸出電路區塊係用來將自灰階資料輸入端子輸入之灰階資 料轉換為用以驅動顯示面板80之灰階電壓後，經由輸出端 子將轉換之灰階電壓輸出至顯示面板80。 (向動作確認測試之切換） 其次’向進行DAC電路8之動作確認之動作確認測試的 切換，使test信號為「H」，使test B信號為「[」。首先， 藉由開關2a成為ON ’而將動作確認測試用之str信號即 TSTR號輸入至預備之取樣電路26，將動作確認測試用 之STR信號即TSTR2信號輸入至取樣電路6。進而，將來自 預備之DAC電路28之灰階電壓輸入至運算放大器1之負極 性輸入端子。又’藉由開關2b成為OFF，而阻斷運算放大 器1之輸出負反饋至自身之負極性輸入端子。其結果，運 算放大器1成為對來自_聯連接於自身之正極性輸入端子 之DAC電路8之輸出電壓、與來自預備之Dac電路28之輸 出電壓進行比較的比較器。 再者，test信號及test B信號從控制動作確認測試之切換 及動作確認測試之動作之控制電路（未圖示）輸出。又，該 控制電路（控制機構）亦可為對動作確認測試_之經由資料 匯流排而輸入之灰階資料及資料L0AD信號進行控制之電 路。進而，該控制電路可與對一般動作中之灰階資料、資 料load信號、移位時脈用輸入信號進行控制之控制電路 相同’亦可為不同之控制電路。 (實施形態1之動作確認測試1) 143488.doc -38 - 201030412 其次，以下參照圖19對動作確認測試之第一順序進行說 明。圖19係表示第丨實施形態之動作確認測試之第一順序 之流程圖。 . 該圖所示之步驟Μ1(以下簡稱作S21)中，使test信號為 「H」，使test b信號為「L」。如已進行之上述般，藉由 • S21’運算放大器1具有比較器之作用。 接著，S22中，將未圖示之控制電路所包含之計數器瓜 φ 初始化為〇。進而，控制電路使TSTR1信號有效，而將與 計數器m之值相對應之灰階m之灰階資料、於此為灰階〇之 灰階資料經由資料匯流排儲存於預備之取樣電路26中。進 而，控制電路使TSTR2信號有效，而將計數器m之值加上夏 所得之灰階m+1之灰階資料、於此為灰階〗之灰階資料經 由資料匯流排儲存於取樣電路6中。接著，預備之保持電 路27根據資料L〇AD信號，自取樣電路26取得灰階〇之灰階 資料。進而，DAC電路28自保持電路27輸入灰階資料，將 Φ 灰階〇之灰階電壓輸出至運算放大器1之負極性輸入端子 (S23)。另一方面，保持電路7根據資料L〇AD信號，自取 樣電路6取得灰階1之灰階資料。進而，DAC電路8自保持 •電路7輸入灰階資料。&DAC電路8將灰階丨之灰階電壓輸 出至與自身串聯連接之各運算放大器丨之正極性輸入端子 (S23)。再者，本發明之積體電路1〇輸出n灰階之灰階電 壓，灰階為〇之灰階電壓為最低之電壓值，灰階為11之灰階 電壓為最高之電壓值。 繼而’運算放大器1將輸入至正極性輸入端子之來自 143488.doc -39- 201030412 DAC電路8之灰階電壓、與輸入至負極性輸入端子之來自 DAC電路28之灰階電壓進行比較（S24)。具體而言，運算 放大器1將灰階為1之灰階電壓輸入至自身之正極性輸入端 子，將灰階為0之灰階電壓輸入至自身之負極性輸入端 子。於此’若DAC電路8正常，則灰階為丨之灰階電壓較灰 階為0之灰階電壓更高，因此運算放大器j輸出「H」位準 之信號。於此，於運算放大器之輸出為「L」位準之信號 之情形時，DAC電路8為不良。 然後，判定電路3(判定機構）輸入來自運算放大器丨之輸 出信號’且將所輸入之信號之位準與自身所記憶之期望值 進仃比較。再者’判定電路3所記憶之期望值係自控制電 路提供者。於該動作確認測⑴中，判定電路3將期望值作 為「Η」位準而加以記憶。 +於此右自運算放大器W入之信號與判定電路3自身所 έ己憶之期望值同為「Μ . ^ 路8 .方」料，則判定電路3判定為DAC電 「L :進 面，若自運算放大器1輸入之信號為 「Η」旗標輸出至判定::4广為罐電路8不良，並將 旗標之情形時，判_人二:電:3:「H: 之内部記憶體中。(S25) H」旗標§己憶於自身 再者’判定電路3亦可為如 器1之輸出信號，若所幹入夕構成·輸入來自運算放大 「L·」旗標瞥 乜號為H」位準，則將 '、輸出至判定旗標 準，則將「U 右輪入之信號為「Lj位 J旗標輸出至判㈣標4。料，於判定旗標 143488.doc 201030412 旗標之情形時，之後即 判定旗標4仍持續保持 4自判定電路3即便輸入一次 便自判定電路3輸入r L」旗標， 「H」旗標。 又，判定電路3亦可成為如下構成··於判斷為不良而判 定旗標4成為「H」之情形時，不進行其後之判定動作。Control of the display control system and the source driver 10a of the actuator i〇b=sample: It can also be based on the control signal sent from the controller and the data number for display. 'But if it is set inside the preliminary source driver (10) There is no need to read, the body and the county memory have display content, then there is no need to continuously display the display data = final supply to the preparatory source driver. ^ Before the display source drive dynamics 10b is displayed, the display memory memory display data can be displayed using the display material in the memory. If it is determined that the display is not present, the display memory is displayed in R〇M (Read 0nly M_ry' read-only memory) or 〇Tp (〇ne Time pr〇m, - under-programmable memory). After the content is fixed, & it is necessary to transfer the display data to the preparatory source driver 1b from the outside, and the display control can be performed easily and easily. In the self-detection and self-repair, the comparison determination circuit 5() performs the output circuit block 30; the judgment is made, and the determination result (4) is the 敎 flag (bad detection information) and is memorized. In the memory in the source driver. The display unit performs self-purity based on the determination flag, and it is also necessary to memorize the determination flag in advance when the power supply is not supplied to the remaining drive 143488.doc •27·201030412. gP, if the judgment flag is lost, the bad output circuit cannot be specified, so it is necessary to perform self-detection again, so that each self-repair operation takes a long time. If the memory of the source driver is non-volatile, there is no problem, but placing the non-volatile memory in the source driver causes an increase in cost. Therefore, the memory in the source driver is usually volatile. Memory. Therefore, when the power is turned off, the judgment flag of the memory stored in the source driver disappears. Therefore, the liquid crystal television 400 includes a configuration in which the content of the determination flag of the source driver is transmitted to the external memory 81 (the hidden device) when the power is turned off, and the flag is judged when the power is turned on. The suffix 81 marked from the outside is read into the memory in the source driver. Fig. 13 is a view showing an example in which a memory 81 is mounted on a printed circuit board 97 to which an input terminal of a source driver 1 is mounted, which is a display unit 9 constituting a liquid crystal television. The source driver i 〇a includes: a string 1/〇 (inpm/〇utput) for inputting and outputting the value of the volatile memory used for the determination flag set in each of the internal output circuit blocks as the serial data. , an input/output terminal; a terminal for setting a write to the data of the memory 81; and a terminal for reading the data from the memory 81. The serial I/O terminal is connected to the memory 8A, and data can be read and read between the volatile memory inside the source driver 10a and the external memory 8丨. 143488.doc -28- 201030412 When the power of the liquid crystal television 400 is turned off by a user's operation or a power-off timer, etc. (that is, when the power of the display unit 9 is turned off), the controller 1 〇〇 (write control means) 'puts a write to the data set to the memory 81. The terminal supplies a signal indicating the writing to the data of the memory 81, and sets the source driver 10a to write to the memory 81. The status of the data. Then, based on the instruction from the controller 100, the data of the determination flag is written from the source driver 10a to the external memory 81, and the memory 81 memorizes the judgment flag. This operation is performed for each of the source drivers 10a so that the decision flags of all the source drivers are memorized in the memory 81. On the other hand, when the power is turned on, the controller 1 〇〇 sets a signal for reading data from the memory 81, supplies a signal indicating that data is read from the memory 81, and sets the source driver 10a to perform. The state of the data is read from the memory 81. Thereby, the data of the determination flag is read from the external memory 81 into the source driver 10a, and the volatile memory memory inside the source driver 1a remembers the determination flag. This operation is performed for each source driver 1a so that the decision flag is stored in the memory inside all the source drivers. Then, the switching circuits 60 and 6 are switched between the defective round-out circuit block 30 and the preliminary output circuit block 4A based on the read determination flag, and the source driver 10a is self-repaired. Fig. 14 is a view showing another example in which the memory unit 81 is mounted on the printed circuit board 97 to which the input terminal of the source driver is connected, in the display unit 90 which constitutes the liquid crystal television 4〇〇2 TFT_lcd module. In the configuration shown in FIG. U, the terminals of the source driver for inputting the data of the decision flag of the output source driver 10a are connected to each other, whereby the string 143488.doc -29-201030412 can be written or read. Enter the judgment flag of the source driver installed. Further, in the present embodiment, the memory 81 uses a flash memory which is a non-volatile memory, but may be a volatile ram. At this time, as a circuit configuration for always supplying a voltage to the power supply of the RAM, it is necessary to provide a capacitor or a battery that is prepared to be used after the sudden power supply is turned off. Further, in the examples of Figs. 13 and 14, the memory 81 is provided on the printed circuit board 97, but may be provided on another substrate such as a control board and connected via the film cable 98. Next, a configuration for performing self-detection when the power of the display unit 90 is turned off will be described with reference to Fig. 15 . Fig. 15 is a flow chart showing the procedure of self-detection of the incoming source driver 10a when the power of the display unit 9 is turned off. In this configuration, only self-repair is performed without self-detection when the power is turned on, and self-detection is performed when the power is turned off instead. When the display unit 90 is powered on (S1501), the determination flag is stored in the external memory unit J, and the determination flag is transmitted to the internal memory of the source driver J (S1502). Then, the source driver 1a performs self-repair based on the determination flag (S1503), and starts a general operation of displaying an image or the like on the display panel 8A (S1, 504). In the normal operation, the display unit 90 determines whether or not the power-off command has been received at a predetermined time interval (S1505). Further, the display unit 90 repeatedly determines whether or not the power-off command has been received during the period in which the power-off command is not sensed (S 1505 . No). Moreover, when the display unit 90 senses that the self-switch or the remote controller sends a power-off command to the liquid crystal television 400 (or the display unit 90) (sl5〇5: 143488.doc -30- 201030412 (疋)) The display of the image on the display panel 80 is (8) times). At this time, the power of the display unit 90 itself and the system including the display unit 9A are not turned off. Next, in the display unit 9, it is judged whether or not each of the output circuits of the driver W is defective. The determination unit 90 performs self-detection of the source driver (10), and stores the determination flags indicating the determination results. The internal memory of the source driver, medium (S 1507). Then, after all the source drivers, it is determined whether the self-detection 0 is over (S1508). When not all of the source drivers 10a have finished self-detection (S1508: No), the remaining source drivers 1a that are not self-tested are repeated in the same manner in 5〇7. The process of detecting and storing the determination flag in the internal memory. When all the source drivers 10a end self-detection (sl5〇8: (4), the determination flag stored in the memory inside the source driver 10a is stored in the non-volatile outside the source driver 1〇a. In the memory 81 (815〇9). Then, after the self-detection determination flag is stored in the memory of the source driver 1 〇 & the display unit 9 〇 the source driver 1 〇 a And the power supply of the peripheral circuit is disconnected (S1510). By the above processing, when the output circuit block included in the source driver 1 〇 & generates an abnormality in the display portion 9 显示, the power is turned off. After the power is turned off, the power is turned on again to restore the display. (DVD device 402) FIG. 16 is a diagram showing an example of self-detection and self-repairing operations in the liquid crystal television. FIG. 16(a) shows self-detection and Figure of the LCD TV 400 before self-healing action Figure 16 (b) shows the self-test and self-repair movement 143488.doc 31 201030412 The picture of the LCD TV 400 in the picture, Figure 16 (c) shows self-test and self-repair LCD TV 400 after the action As shown in Fig. 1, a DVD (Digital Versatile Disc or Digital Video Disc) device 402 is mounted on the liquid crystal television 400. The DVD device 402 has a function of reproducing and recording a DVD, etc. In the liquid crystal television 400, according to the user. In response to the instruction, the DVD and HDD control unit 404 controls various operations of the DVD device 402 (video reproducing device). The DVD needs to periodically clean the head of the read signal. Therefore, as shown in Fig. 16 (a), the cleaning disk is inserted. The sheet is cleaned by the read head. After detecting the insertion of the cleaning disc, the DVD device 402 starts the cleaning operation based on the control signal from the DVD and HDD control unit 404 corresponding to the user's instruction. (a) shows that the liquid crystal television 400 has a defect that a vertical line exists on the display pupil surface. Moreover, the liquid crystal television 400 is characterized by the following configuration, that is, the cleaning time of the DVD device 402 integrally included. At the same time, the self-detection of the source driver 1 〇a is performed. As will be explained in more detail, the DVD and HDD control section 404 receives a signal indicating that the cleaning has started from the DVD device 402. The controller 100 is supplied with a signal indicating that the self-detection and self-repair of the source driver 1 〇a is started. Then, according to the instruction from the controller 1, the source driver 10a starts self-detection and self. Further, the DVD device 402 may be configured separately from the liquid crystal television 400. As shown in Fig. 16(b), when the notification of the meaning of the cleaning is being performed, the user is Convenience is improved, but the general image display 143488.doc -32- 201030412 The source (4) device 1Qa will perform self-checking operation while cleaning, so it is necessary to have a preparatory source driver (10) as described above. Further, 'the determination flag indicating the determination result of the self-detection of the source driver 10a is held in the memory inside the source driver 10a, and the source driver 10a is based on the determination flag held in the internal memory. Perform a self-healing action. Thereby, as shown in Fig. 16 (4), the defect of the vertical line on the display screen of Fig. 16 (4) is eliminated. When the power is turned off, the memory of the above-mentioned determination flag from the source driver 1 〇a is stored in the external memory 81, and is read again into the source driver 1 〇 & Self-repairing again in the memory. (HDD device 403) Fig. 17 is a view showing an example of self-detection and self-repairing operation in the liquid crystal television 400, and Fig. 17(a) is a view showing the liquid crystal television 400 before the self-detection and self-repair operation, Fig. 17 ( b) shows the LCD TV 400 in the self-test and self-repair action, Figure 17 (the picture shows the LCD TV 400 after the self-test and self-repair action is completed. As shown in Figure 1 'LCD TV 4〇〇 A jjDD (Hard Disk Drive) device 403 is built in. The HDD device 403 has a function of reproducing, recording, and the like by using the HDD. In the liquid crystal television 400, the DVD and HDD control unit 404 pairs the HDD device 403 (in accordance with an instruction from the user). The various operations of the playback device are controlled. The HDD needs to perform maintenance of a memory area or the like (for example, optimization of a memory area such as reorganization or error check of a disc, etc.), and the HDD device 403 comes from the user's instruction. DVD and HDD control unit 404 control 143488.doc •33- 201030412 signal, start maintenance operation. The video line can not be recorded and reproduced during maintenance, so the memory area of the HDD device 4〇3 Therefore, in the liquid crystal television 400, as shown in Fig. 17 (4), the user specifies a time (e.g., late at night) which is not (4), and is maintained at the designated time. The '_ device has a timer function that can be maintained at a preset time. Further, as shown in Fig. 17 (4), the liquid crystal television has a defect that the vertical line is generated on the display screen. * Moreover, the liquid crystal television 400 is characterized in that In the following configuration, the self-detection of the heart of the source drive is performed when the foot of the body is included. If it is described in more detail, the DVD and HDD control unit 404 receives from the HDD farm 4G3. After indicating that the signal of the optimization of the memory area has been started, a signal indicating that the self-detection and self-repair of the source driver ι〇& has been started is supplied to the controller 100. Then, according to the instruction from the controller 1 The source driver core starts self-detection and self-repair operation. The HDD device 403 can also be configured independently from the LCD TV. The self-test is used. It is not used for the time, so there is no need to display the meaning of maintaining the HDD. As shown in Figure 17(b), the display is turned off. Also, it is considered that the user forgets to maintain the HDD and wants to display it. In this case, it is also possible to perform a simple display by mounting the above-described source driver 100b. The determination flag indicating the result of the self-detection is held in the memory inside the source driver, according to the Self-repair by judging the flag 143488.doc .34- 201030412 Action. Fig. 17(c) shows the state of the screen when the display is performed again after the maintenance is completed, and informs the user that the maintenance has been completed. As shown in Fig. 17 (4), the defect of the vertical line on the display pupil surface of Fig. 17 (a) is eliminated. • Moreover, when the power is turned off, the determination flag stored in the memory inside the source driver 1A is stored in the external memory, and is read again into the source driver 10a when the power is turned on. Self-repairing again in memory. (Configuration of Integrated Circuit 10) Next, the configuration of the source driver 1A of the present invention will be described with reference to Fig. 18. Further, as described above, the preliminary source driver 1b may be configured to be simpler than the source driver 10a', but may be the same as the source driver 10. Hereinafter, a circuit that can perform the same self-detection and self-repair operation as the source driver 1A will be referred to as an integrated circuit. Fig. 18 is an explanatory view showing the configuration of an integrated circuit 1 (drive circuit). As shown in the figure, the 'integrated circuit 10 includes: n sampling circuits 6-1 to 6-n (hereinafter, referred to as sampling circuit 6 in the case of a general term), which are input from the gray-scale data input terminal (not shown). And inputting grayscale data corresponding to each of the n liquid crystal driving signal output terminals OUT1 to UTn (hereinafter referred to as output terminals OUT1 to OUTn) via the data bus; n holding circuits 7-^7^( Hereinafter, in the case of the general term, it is referred to as a holding circuit 7); n DAC circuits 8-1 to 8-n (hereinafter, referred to as DAC circuit 8 in the case of a general term), which convert gray scale data into gray scale voltage Signal; n operational amplifiers 1-1~1_η (hereinafter, referred to as operational amplifier 1 in the general case), which have a snubber circuit for the gray-scale voltage signal from the DAC circuit 143488.doc -35· 201030412 η determination circuits 3-1 to 3-n (hereinafter, referred to as determination circuit 3 in the case of a general term); n determination flags 4-1 to 4-n (hereinafter, referred to as a general case) Judging flag 4); and n pull-up and pull-down circuits 5·1~5-η (hereinafter, referred to as pull-up and pull-down circuit hooks in the case of the general term. As shown in the figure, the accumulation circuit 10 includes a plurality of switches 2a that switch between ON (open) and OFF (off) according to a test signal; according to the test B signal, a plurality of switches 2b that switch between 〇1 and 17; and a plurality of switches 2c that switch between 〇^^ and 〇1^ according to the output signals from the decision flag 4, that is, Flag1 to Flagn (connection switching mechanism) And 2d (connection switching mechanism). In addition, switches, 2b, and 2d become 〇N when the "H" signal is input, and become 〇FF^ when the "L" signal is input. On the other hand, the switch and the switch are turned off when the input has the "k", and become ON when the "n" signal is input. Further, the integrated circuit 10 includes one of the following circuits: a preliminary sampling circuit 26, a preparatory holding circuit 27; a prepared DAC circuit 28 (prepared output circuit); and a preliminary operational amplifier 21. Further, in Fig. 18, the sampling circuit 6, the holding circuit 7, and DA (: circuit 8 corresponds to Fig. 2 Output circuit block 3〇, sampling circuit %, holding circuit 27, and DA shown The C circuit 28 corresponds to the preliminary circuit block 4A shown in FIG. 2. The operational amplifier 1, the decision circuit 3, and the decision flag 4 correspond to the comparison decision circuit 50 shown in FIG. 2, and are connected to the output terminals 〇UT1 to 〇UTn. The switch 2d and the switch 2c correspond to the switching circuit 6A shown in Fig. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in Fig. 2. Further, as shown in Fig. 18, 143488.doc • 36 - The integrated circuit of 201030412 is connected to the display panel 80 shown in FIG. 2 via the output terminals OUT1 to 〇UTn. In FIG. 18, the illustration of the display panel 8A is omitted. (General Operation of Integrated Circuit 10) Next, a general operation of outputting the gray scale voltage to the display panel 80 (see Fig. 2) in the integrated circuit 10 will be described below with reference to Fig. 18. First, in the case of normal operation, the test signal is "L" and the test β signal is "Η". When the test signal is "L", the switch 2a is turned OFF, and the switch 2b is turned ON. As a result, STR1 to STRn signals (hereinafter referred to as STR signals in the case of a general term), which are signals from the shift register, which are not shown, are input to the corresponding sampling circuits 6. The sampling circuit 6 receives the gray scale data corresponding to itself from the gray scale data input terminal via the data bus according to the input STR signal. The hold circuit 7 inputs the gray scale data obtained by the sampling circuit 6 from the sample circuit 6 based on the data LOAD signal '. Then, the DAC circuit 8 (output circuit) inputs gray scale data from the holding circuit 7. The DAC circuit 8 converts the input gray scale data into a gray scale voltage signal and outputs it to the positive polarity input terminal of the differential amplification | § 1 (comparison mechanism). Thus, since the switch 2b is turned on, the output of the operational amplifier 1 becomes a negative feedback to its own negative input terminal. Thereby, the operational amplifier 1 operates as a voltage follower. Thereby, the operational amplifier 1 functions as a snubber circuit for the gray scale voltage from the DAC circuit 8, and outputs a gray scale voltage signal input to its own positive polarity input terminal to the corresponding output terminals OUT1 to OUTn. Here, the switch 2c is turned ON, and the switch 2 (1 is turned OFF. The operation of the switches 2c and 2d will be described below. The above-described series connection to each of the output terminals includes the sampling circuit 6, the holding circuit 7, 143488.doc • 37· 201030412 The DAC circuit 8 and the block of the operational amplifier 1 are used as output circuit blocks, which are used to convert the gray scale data input from the gray scale data input terminal into the driving circuit. After the gray scale voltage of the panel 80 is displayed, the converted gray scale voltage is output to the display panel 80 via the output terminal. (Switching to the operation confirmation test) Next, the switching of the operation confirmation test for confirming the operation of the DAC circuit 8 is performed. The test signal is "H", and the test B signal is "[". First, the switch 2a is turned ON", and the str_signal for the operation confirmation test, that is, the TSTR number, is input to the preparatory sampling circuit 26, and the operation confirmation test is used. The STR signal, that is, the TSTR2 signal is input to the sampling circuit 6. Further, the gray scale voltage from the prepared DAC circuit 28 is input to the negative polarity input terminal of the operational amplifier 1. Further, 'by the switch 2b becomes O FF, and the output of the operational amplifier 1 is blocked from being negatively fed back to its own negative input terminal. As a result, the operational amplifier 1 becomes the output voltage of the DAC circuit 8 connected from its own positive input terminal. The comparator for comparing the output voltages of the Dac circuit 28. The test signal and the test B signal are output from a control circuit (not shown) for switching the control operation confirmation test and the operation confirmation test operation. (Control mechanism) may also be a circuit for controlling the gray scale data and the data L0AD signal input through the data bus bar for the operation confirmation test _. Further, the control circuit can be used with the gray scale data and data load in the general action. The control circuit for controlling the signal and the shift clock with the input signal is the same 'may be a different control circuit. (The operation confirmation test 1 of the first embodiment) 143488.doc -38 - 201030412 Next, the operation confirmation will be described below with reference to FIG. The first sequence of tests will be described. Fig. 19 is a flow chart showing the first sequence of the operation confirmation test of the second embodiment. In the step Μ1 (hereinafter referred to as S21) shown, the test signal is "H" and the test b signal is "L". As described above, the operational amplifier 1 has a comparator function by the S21 Next, in S22, the counter melon φ included in the control circuit (not shown) is initialized to 〇. Further, the control circuit makes the TSTR1 signal valid, and sets the gray scale data of the gray scale m corresponding to the value of the counter m, Here, the gray scale data of the gray scale is stored in the preliminary sampling circuit 26 via the data bus. Further, the control circuit makes the TSTR2 signal valid, and the value of the counter m is added to the gray scale m+1 of the summer. The gray data of the order data and the gray scale is stored in the sampling circuit 6 via the data bus. Next, the preparatory holding circuit 27 obtains the gray scale data of the gray scale from the sampling circuit 26 based on the data L〇AD signal. Further, the DAC circuit 28 inputs the gray scale data from the holding circuit 27, and outputs the gray scale voltage of the Φ gray scale 至 to the negative polarity input terminal of the operational amplifier 1 (S23). On the other hand, the holding circuit 7 obtains the gray scale data of the gray scale 1 from the sampling circuit 6 based on the data L 〇 AD signal. Further, the DAC circuit 8 inputs the gray scale data from the hold circuit 7. The & DAC circuit 8 outputs the gray scale voltage of the gray scale 输 to the positive polarity input terminal of each operational amplifier 串联 connected in series with itself (S23). Furthermore, the integrated circuit 1 of the present invention outputs a gray scale voltage of n gray scale, the gray scale is the lowest voltage value of the gray scale voltage, and the gray scale voltage of the gray scale is the highest voltage value. Then, the operational amplifier 1 compares the gray scale voltage from the 143488.doc -39 - 201030412 DAC circuit 8 input to the positive polarity input terminal with the gray scale voltage from the DAC circuit 28 input to the negative polarity input terminal (S24). . Specifically, the operational amplifier 1 inputs a gray scale voltage of gray scale 1 to its own positive polarity input terminal, and inputs a gray scale voltage of gray scale 0 to its own negative polarity input terminal. Here, if the DAC circuit 8 is normal, the gray scale voltage of the gray scale is 较, and the gray scale voltage of the gray scale is 0, so the operational amplifier j outputs the signal of the "H" level. Here, in the case where the output of the operational amplifier is a signal of the "L" level, the DAC circuit 8 is defective. Then, the decision circuit 3 (determination means) inputs the output signal ' from the operational amplifier ’ and compares the level of the input signal with the expected value memorized by itself. Furthermore, the expected value memorized by the decision circuit 3 is from the control circuit provider. In the operation confirmation test (1), the determination circuit 3 remembers the expected value as the "Η" level. + The signal from the right self-operating amplifier W and the expected value recalled by the decision circuit 3 itself are "Μ . ^路8 . square", the decision circuit 3 determines that the DAC is "L: the face, if The signal input from the operational amplifier 1 is "Η" flag output to the judgment: 4 is generally bad for the tank circuit 8, and when the flag is used, it is judged _ person two: electricity: 3: "H: internal memory (S25) H"flag § already remembers itself. 'Determining circuit 3 can also be the output signal of device 1, if it is done in the evening, the input is from the operational amplification "L·" flag nickname For the H" level, it will be output to the judgment flag standard, then the signal of the U right wheel is "Lj bit J flag output to the judgment (four) standard 4. In the judgment flag 143488.doc 201030412 flag In the case of the standard, it is determined that the flag 4 is continuously maintained. The self-determination circuit 3 inputs the r L" flag, the "H" flag, from the decision circuit 3 even if it is input once. Further, the determination circuit 3 may be configured as follows: When it is determined that the flag 4 is "H" when it is determined to be defective, the subsequent determination operation is not performed.

其次，對計數llm之值是否為進行判以s26)。於計 數器m之值為w以下之情形時，使計數器爪之值加上丄而 反覆進行S23〜S25之步驟直至值成為為止。再者， 所謂該η係積體電路10可輸出之灰階數。 (實施形態1之動作確認測試2) 之第二順序進行說 認測試之第二順序 其次，以下參照圖20對動作確認測試 明。圖2 0係表示第1實施形態之動作確 之流程圖。 首先，於動作確認測試1中，輸入至運算放大器丨之正極 性輸入端子之灰階電壓始終較輸入至負極性輸入端子之灰 階電壓更尚，因此於存在僅將較低之電壓輸出至DAC電路 28之不良之情形時、或於存在僅將較高之電壓輸出至dac 電路8之不良之情形時，判定電路3會輸出表示正常之 「L」旗標。 因此，於動作確認測試2中，對運算放大器1之正極性輸 入端子輸入較負極性輸入端子更低之灰階電壓而進行動作 確認。 首先，動作確認測試1結束後，將計數器m之值初始化 為0(S31)。然後，控制電路使TSTR1信號有效，而將計數 143488.doc •41- 201030412 器m之值加上1所得之灰階m+l之灰階資料、於此為灰階1 之灰階資料經由資料匯流排儲存於預備之取樣電路26中。 繼而，控制電路使TSTR2信號有效，而將與計數器m相對 應之灰階m之灰階資料、於此為灰階〇之灰階資料經由資料 匯流排儲存於取樣電路6中。 於此，與動作確認測試1之S23同樣地，DAC電路28經由 保持電路27而輸入取樣電路26所儲存之灰階資料。進而， DAC電路28將與所輸入之灰階資料相對應之灰階1之灰Next, it is judged whether or not the value of the count llm is s26). When the value of the counter m is equal to or less than w, the value of the counter claw is added to the step S23 to S25 until the value is reached. Furthermore, the η-series circuit 10 can output the number of gray levels. In the second sequence of the operation confirmation test 2 of the first embodiment, the second sequence of the test is performed. Next, the operation check test will be described below with reference to Fig. 20 . Fig. 20 is a flow chart showing the operation of the first embodiment. First, in the operation confirmation test 1, the gray scale voltage input to the positive polarity input terminal of the operational amplifier 始终 is always higher than the gray scale voltage input to the negative polarity input terminal, so that only the lower voltage is output to the DAC in the presence of the DAC. When the circuit 28 is in a bad condition or when there is a problem that only a higher voltage is output to the dac circuit 8, the determination circuit 3 outputs a flag indicating "L" which is normal. Therefore, in the operation confirmation test 2, a lower gray scale voltage than the negative polarity input terminal is input to the positive polarity input terminal of the operational amplifier 1, and the operation is confirmed. First, after the operation confirmation test 1 is completed, the value of the counter m is initialized to 0 (S31). Then, the control circuit makes the TSTR1 signal valid, and adds the grayscale data of the grayscale m+l obtained by adding the value of 143488.doc •41-201030412 to m, and the grayscale data of the grayscale 1 is transmitted through the data. The bus bars are stored in the preparatory sampling circuit 26. Then, the control circuit makes the TSTR2 signal valid, and the gray scale data of the gray scale m corresponding to the counter m, and the gray scale data of the gray scale 于此 are stored in the sampling circuit 6 via the data bus. Here, similarly to S23 of the operation check test 1, the DAC circuit 28 inputs the gray scale data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 will grayscale the gray scale 1 corresponding to the input gray scale data.

階電壓、於此為灰階1之灰階電壓輸出至運算放大器1之負 極性輸入端子。另一方面，DAC電路8經由保持電路7而輸 入取樣電路6所儲存之灰階資料。進而，各DAC電路8將與 所輸入之灰階資料相對應之灰階m之灰階電壓、於此為灰 階〇之灰階電壓輸出至與自身串聯連接之各運算放大Si之 正極性輸入端子（S32)。The step voltage, here the gray scale voltage of the gray scale 1, is output to the negative polarity input terminal of the operational amplifier 1. On the other hand, the DAC circuit 8 inputs the gray scale data stored in the sampling circuit 6 via the holding circuit 7. Further, each DAC circuit 8 outputs a gray scale voltage of gray scale m corresponding to the input gray scale data, and a gray scale voltage of the gray scale 于此 to the positive polarity input of each operational amplification Si connected in series with itself. Terminal (S32).

然後，運算放大器1將輸入至正極性輸入端子之來自 DAC電路8之灰階0之灰階電壓、與輸入至負極性輸入端子 之來自DAC電路28之灰階！之灰階電壓進行比較（S33)。於 此，若DAC電路8正常，則灰階丨之灰階電壓較灰階〇之灰 階電壓更高，因此運算放大器1輸出「L」旗標之信號。於 此，於運算放大器之輸出為「H」位準之信號之情形時 DAC電路8為不良。 *而’判定電路3輸入來自運算放大器1之輸出信號 等所輸入之u之位準與自身所記憶之期望值進行比 於該動作確認測試1中，判定電路3將期望值作為4 143488.doc -42- 201030412 準而加以記憶。於此，若 運算放大器1輸入之信號與自 -之期望值同為「L」位準，則判定電路 DAC電路8正堂。又一 士工 馬 方面，若自運算放大器1輸入之信號 ‘：」’則判定電路3判定為DAC電路8 +良，並將 Η」旗標輸出至判定旗標4。於自判定電路3輸入「η :標之情形時，判定旗標4將所輸入之「Η」旗標記憶於」自 身之内部記憶體中（S34)。反覆進行以上之S33〜s34之步驟 直至爪之值成為n-1為止（S35、S36)。 (實施形態1之動作確認測試3) 其-人’以下參照圖21對動作確認測試之第三順序進行說 明。圖2丨係表示第丨實施形態之動作確認測試之第三順序 之流程圖。 DAC電路8中存在如下情形··於存在輸出端成為開路之 不良之情形時，運算放大器1持續保持藉由已執行之確認 測試而輸入至運算放大器i之灰階電麼，而於動作確認測 • 試1及2中無法檢測出不良。於此，動作確認測試3中，將 下拉電路連接於運算放大器丨之正極性輸入端子。藉此， 於DAC電路8之輸出端成為開路之情形時，會將較低之電 壓輸入至運算放大器i之正極性輸入端子。其結果可防止 於DAC電路8之輸出端成為開路之情形時、換言之於dac 電路8無輸出之情形時，運算放大以持續保持⑽行之確 認測試之輸入至運算放大器丨之灰階電壓。 動作確認測試3之具體順序係如圖21所示，首先，將計 數器m初始化為0(S41)。後’上拉與下拉電路5將運算放 143488.doc -43- 201030412 大器1之正極性輸入端子下拉（S42)e自此開始之s43〜s47 之步驟與已進行之上述之動作確認測試丨之S23〜S27之步驟 相同’因此於此省略其說明。 如上所述，藉由將運算放大器1之正極性輸入端子下拉 進行動作相測試！之順序，而於DAC電路8之輸出端成為 開路之情形時，運算放大以輸出「L」位準之信號。其結 果’判定電路3根據所輸入之「L」位準之信號，判定為 DAC電路8中存在不良’且判定旗標4記憶「h」旗標。 (實施形態1之動作確認測試4) 其次，以下參照圖22對動作確認測試之第四順序進行說 明。圖22係表不第1實施形態之動作確認測試之第四順序 之流程圖。 於此，動作確認測試4係與動作確認測試3同樣地用以對 應於DAC電路8之輸出端成為開路之不良。如該圖所示， 首先，將計數器m初始化為0(S51) ^然後，上拉與下拉電 路5將運算放大器丄之正極性輸入端子上拉（s52)。自此開 始之S53〜S57之步驟與已進行之上述之動作確認測試2之 S32〜S36之步驟相同，因此於此省略其說明。 如上所述，藉由將運算放大器丨之正極性輸入端子上拉 進行動作確涊測試2之順序，而於DAC電路8之輸出端成為 開路之情形時，運算放大器i輸出「H」位準之信號。其結 果，判定電路3根據所輸入之「H」位準之信號，判定為 DAC電路8中存在不良，且判定旗標4記憶「Η」旗標。 (實施形態1之動作確認測試5) 143488.doc 201030412 其次’以下參照圖23對動作確認測試之第五順序進行說 明。圖23係表示第1實施形態之動作確認測試之第五順序 之流程圖。 DAC電路8中存在產生自身之鄰接之兩個灰階短路之不 良的情形。如上所述，於鄰接之兩個灰階短路之情形時， DAC電路8輸出短路之兩個灰階之中間電壓。於該不良之 情形時’ DAC電路8所輸出之灰階電壓與正常之情形相 比’不會偏差1灰階以上之電壓。因此，動作確認測試1〜4 中，無法檢測出該不良。於此，動作域認測試5中之目的 在於’對如上所述之DAC電路8中之鄰接之兩個灰階短路 的不良進行檢測。 如該圖所示，首先’將計數器瓜初始化為〇(S61)。然 後’使TSTR1及TSTR2有效，進而，經由資料匯流排將灰 階m之灰階資料、於此為灰階〇之灰階資料輸入至取樣電路 26及取樣電路6。繼而，DAC電路28及8經由保持電路27及 7，自取樣電路26及6取得灰階〇之灰階資料。進而，DAC 電路28及8將灰階〇之灰階電壓輸出至運算放大器1之正極 性輸入端子及負極性輸入端子（S62)。 接著’藉由未圖示之開關，而使運算放大器1之正極性 輸入端子與負極性輸入端子短路。再者，於動作確認測試 1及2中’判定為Dac電路8不存在不良之情形時，輸入至 正極性輸入端子與負極性輸入端子之灰階電麼之差不會成 為1灰階以上之電壓差。因此’藉由使正極性輸入端子與 負極性輸入端子短路，而不存在較大之電流流動之問題。 143488.doc •45- 201030412 於此’藉由使運算放大器1之正極性輸入端子與負極性 輸入端子短路，而使運算放大器1之兩個輸入端子輸入相 同之灰階電壓。於此’因運算放大器丨原本具有輸入輸出 之偏移電壓’故即便將相同之灰階電壓輸入至自身之兩個 輸入端子’運算放大器1之輸出端仍輸出「H」或「L」之 任一者。判定電路3將上述之使運算放大器1之正極性輸入 端子與負極性輸入端子短路之情形時的運算放大器1之輸 出之位準作為期望值加以記憶（S63)。 繼而’使未圖示之開關成為OFF而解除運算放大器！之 正極性輸入端子與負極性輸入端子之短路。此時，將來自 DAC電路8之灰階〇之灰階電壓輸入至運算放大器1之正極 性輸入端子，將來自DAC電路28之灰階0之灰階電壓輸入 至負極性輸入端子。於此，若DAC電路28及8無不良，則 運算放大器1之輸出成為與記憶於判定電路3中之期望值相 同之輸出。因此，判定電路3將來自運算放大器1之輸出與 自身所記憶之期望值進行比較（S64)。若來自運算放大器1 之輸出值為與期望值不同之值，則判定電路3將「H」旗標 輸出至判定旗標4(S65)。 接著’藉由未圖示之開關，以將來自DAC電路28之灰階 電壓輸入至運算放大器1之正極性輸入端子，將來自DAC 之灰階電壓輸入至負極性輸入端子之方式，切換運 算放大器1之輸入端（S66)。於此，進行與S64相同之處理 (S67)。867中，若來自運算放大器i之輸出與自身所記憶 之期望值不同，則判定電路3將rH」旗標輸出至判定旗標 143488.doc 201030412 4(S68)。如上所述’藉由在正極性輸入端子與負極性輸入 端子之間進行切換，即便判定電路3所記憶之期望值為 「H」位準或「L」位準之任一者，仍可檢測出DA(：電路8 之不良。 使計數器m之值加上1而反覆進行以上之S62〜S68之步驟 直至計數器m之值成為η為止（S69、S70)。 (自我修復）Then, the operational amplifier 1 inputs the gray scale voltage of the gray scale 0 from the DAC circuit 8 to the positive polarity input terminal, and the gray scale voltage from the DAC circuit 28 input to the negative polarity input terminal! The gray scale voltages are compared (S33). Therefore, if the DAC circuit 8 is normal, the gray scale voltage of the gray scale 较 is higher than the gray scale voltage of the gray scale ,, so the operational amplifier 1 outputs the signal of the "L" flag. Therefore, the DAC circuit 8 is defective when the output of the operational amplifier is a signal of "H" level. * The judgment circuit 3 inputs the value of the input u from the operational amplifier 1 or the like to the expected value stored by itself. In the operation confirmation test 1, the determination circuit 3 takes the expected value as 4 143488.doc -42 - 201030412 Remember to remember. Here, if the signal input from the operational amplifier 1 is the same as the expected value of -, the circuit DAC circuit 8 is judged to be in the right direction. On the other hand, if the signal input from the operational amplifier 1 is ':', the decision circuit 3 determines that the DAC circuit 8 + is good, and outputs the flag to the decision flag 4. When the self-determination circuit 3 inputs "n: the standard condition, the determination flag 4 memorizes the input "Η" flag in the internal memory of itself (S34). The above steps S33 to s34 are repeated until the value of the claw becomes n-1 (S35, S36). (Operation Confirmation Test 3 of the First Embodiment) The third procedure of the operation confirmation test will be described below with reference to Fig. 21 . Fig. 2 is a flow chart showing the third sequence of the operation confirmation test of the second embodiment. The DAC circuit 8 has the following situation: When there is a problem that the output terminal is open, the operational amplifier 1 continues to hold the gray scale power input to the operational amplifier i by the executed verification test, and confirms the operation. • No defects can be detected in tests 1 and 2. Here, in the operation confirmation test 3, the pull-down circuit is connected to the positive polarity input terminal of the operational amplifier 丨. Thereby, when the output terminal of the DAC circuit 8 is open, a lower voltage is input to the positive input terminal of the operational amplifier i. As a result, when the output terminal of the DAC circuit 8 is turned off, in other words, when the dac circuit 8 has no output, the operation is amplified to continuously maintain the grayscale voltage of the input of the test input to the operational amplifier ( (10). The specific sequence of the operation confirmation test 3 is as shown in Fig. 21. First, the counter m is initialized to 0 (S41). After the 'pull-up and pull-down circuit 5 put the operation 143488.doc -43- 201030412 the positive polarity input terminal of the large device 1 pull-down (S42) e step s43~s47 from the beginning and the above-mentioned action confirmation test The steps of S23 to S27 are the same', and thus the description thereof is omitted here. As described above, the action phase test is performed by pulling down the positive input terminal of the operational amplifier 1! In the case of the case where the output of the DAC circuit 8 is open, the operation is amplified to output a signal of the "L" level. As a result, the determination circuit 3 determines that there is a defect in the DAC circuit 8 based on the input signal of the "L" level, and the determination flag 4 memorizes the "h" flag. (Operation Confirmation Test 4 of the First Embodiment) Next, a fourth sequence of the operation confirmation test will be described below with reference to Fig. 22 . Fig. 22 is a flow chart showing the fourth sequence of the operation confirmation test of the first embodiment. Here, the operation check test 4 is used to correspond to the failure of the output end of the DAC circuit 8 in the same manner as the operation check test 3. As shown in the figure, first, the counter m is initialized to 0 (S51). Then, the pull-up and pull-down circuit 5 pulls up the positive input terminal of the operational amplifier ( (s52). The steps from S53 to S57 from the beginning are the same as the steps S32 to S36 of the above-described operation confirmation test 2, and therefore the description thereof will be omitted. As described above, the order of the test 2 is confirmed by pulling up the positive input terminal of the operational amplifier ,, and when the output of the DAC circuit 8 is open, the operational amplifier i outputs the "H" level. signal. As a result, the determination circuit 3 determines that there is a defect in the DAC circuit 8 based on the input "H" level signal, and the determination flag 4 memorizes the "Η" flag. (Operation Confirmation Test 5 of the First Embodiment) 143488.doc 201030412 Next, the fifth sequence of the operation confirmation test will be described below with reference to Fig. 23 . Fig. 23 is a flow chart showing the fifth sequence of the operation confirmation test of the first embodiment. In the DAC circuit 8, there is a case where the two gray-scale short circuits adjacent to each other are generated. As described above, in the case where two adjacent gray scales are short-circuited, the DAC circuit 8 outputs the intermediate voltage of the two gray scales of the short circuit. In the case of this failure, the gray scale voltage outputted by the DAC circuit 8 does not deviate from the voltage of the gray scale by more than the normal case. Therefore, in the operation confirmation tests 1 to 4, the failure cannot be detected. Here, the purpose of the operation domain recognition test 5 is to detect the failure of the adjacent two gray scale short circuits in the DAC circuit 8 as described above. As shown in the figure, first, the counter melon is initialized to 〇 (S61). Then, TSTR1 and TSTR2 are enabled, and the gray scale data of the gray scale m and the gray scale data of the gray scale 于此 are input to the sampling circuit 26 and the sampling circuit 6 via the data bus. Then, the DAC circuits 28 and 8 acquire the gray scale data of the gray scale 自 from the sampling circuits 26 and 6 via the holding circuits 27 and 7. Further, the DAC circuits 28 and 8 output the gray scale voltage of the gray scale 输出 to the positive polarity input terminal and the negative polarity input terminal of the operational amplifier 1 (S62). Then, the positive input terminal of the operational amplifier 1 and the negative input terminal are short-circuited by a switch (not shown). Further, in the case of the operation confirmation tests 1 and 2, when it is determined that there is no defect in the Dac circuit 8, the difference between the gray-scale power input to the positive polarity input terminal and the negative polarity input terminal does not become 1 gray scale or more. Voltage difference. Therefore, by short-circuiting the positive polarity input terminal and the negative polarity input terminal, there is no problem that a large current flows. 143488.doc •45- 201030412 Here, the two input terminals of the operational amplifier 1 are input with the same gray scale voltage by short-circuiting the positive input terminal of the operational amplifier 1 and the negative input terminal. Here, 'the operational amplifier has an input/output offset voltage', so even if the same gray-scale voltage is input to its own two input terminals, the output of the operational amplifier 1 outputs "H" or "L". One. The determination circuit 3 stores the level of the output of the operational amplifier 1 when the positive polarity input terminal of the operational amplifier 1 and the negative polarity input terminal are short-circuited as an expected value (S63). Then, turn off the unillustrated switch and release the operational amplifier! The positive input terminal and the negative input terminal are short-circuited. At this time, the gray scale voltage from the gray scale DAC of the DAC circuit 8 is input to the positive polarity input terminal of the operational amplifier 1, and the gray scale voltage of the gray scale 0 from the DAC circuit 28 is input to the negative polarity input terminal. Here, if there is no defect in the DAC circuits 28 and 8, the output of the operational amplifier 1 becomes the same output as the expected value stored in the decision circuit 3. Therefore, the decision circuit 3 compares the output from the operational amplifier 1 with the expected value memorized by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the decision circuit 3 outputs the "H" flag to the decision flag 4 (S65). Then, by using a switch (not shown), the gray scale voltage from the DAC circuit 28 is input to the positive input terminal of the operational amplifier 1, and the gray scale voltage from the DAC is input to the negative input terminal to switch the operational amplifier. Input 1 of 1 (S66). Here, the same processing as that of S64 is performed (S67). In 867, if the output from the operational amplifier i is different from the expected value stored by itself, the decision circuit 3 outputs the rH" flag to the decision flag 143488.doc 201030412 4 (S68). As described above, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the desired value stored in the determination circuit 3 is any of the "H" level or the "L" level, it can be detected. DA (: circuit 8 is defective. The value of the counter m is incremented by 1 and the above steps S62 to S68 are repeated until the value of the counter m becomes η (S69, S70). (Self-repair)

其次，以下參照圖24，對在判定旗標4記憶有「Η」旗標 之情形時、換言之於上述動作確認測試丨〜5中判定電路3判 定為DAC電路8-Η.η之任一者存在不良之情形時的修復 進行說明。圖24係表示於判定為不良之DAC電路8與預備 之DAC電路28之間進行切換而進行自我修復之順序的流程 判定電路3於判定為DAC電路8不良之情形時，將「η 旗標輪出至判定旗標4。進而，衫旗標4輸人來自判定i :3之「H」旗標並記憶於自身之内部。於此，控制電路輩 二標4是否記錄有「H」進行檢測(S7l)。 :測:判方定旗標4未記憶％之情形時，移行至心 另-方面’控制電路於檢測出判定旗標 之情形時，對判定旗標q七之各自所 ^ Η」 標數進行確認。於此，於判定旗標4所記二Η = :為複數個之情形時，移行至S73之處：。之另=旗 判定旗標4所記憶之「H」之旗標數為—個之另二面： 至叫之處理(S72)。 1固之凊形時，移辛 143488.doc •47· 201030412 於S74中，進行將與記憶「H」旗標之判定旗標*相對應 之DAC電路8切換為預備之DAC電路28之處理（s74)。首 先，當對不良之DAC電路8與預備之DAC電路28之切換順 序進行說明時，於此，使與液晶驅動用信號輸出端子 OUT1相對應之判定旗標‘丨為記憶有「H」旗標者。 判定旗標4-1對開關2c及2d輸出成為「H」位準之Flagi 之輸出信號。根據Flagl之輸出信號，已輸入「H」位準之 信號之開關2c成為OFF，開關2d成為〇N。藉此，開關仏將 來自運算放大器1-1之輸出端與液晶驅動用信號輸出端子❹ ουτι之連接斷開。另一方面，開關2d將輸入至取樣電路 6-1之STR1信號輸出至取樣電路％。藉此，與液晶驅動用 6號輸出端子OUT1相對應之灰階資料亦儲存於取樣電路 26中。進而，開關2d將運算放大器21之輸出端與液晶驅動 用信號輸出端子OUT1連接。如上所述，根據來自判定旗 才示4-1之Flagl之輸出信號，開關2(：及2(1進行切換藉此將 不良之DAC電路8·1切換為預備之dAC電路28。 其·人，對S73之處理進行說明。於判定旗標4所記憶之 © Η」旗標數為複數個之情形時，考慮有預備之DAc電路 28可I為不良。因此，於S73中控制電路使判定旗標4所 δ己憶之旗標全部成為「L」旗標後，移行至S75之處理。其 次於871中判定為NO(否）之情形時，於S73之處理後或於 S74之處理後，控制電路將test信號切換為「L」，將test B 化號切換為「H」後，移行至一般動作（S75)。 如上所述’藉由進行動作確認測試1〜5及自我修復之處 143488.doc -48- 201030412 理，積體電路10可將不良之dac電路切換為預備之dac電 進而第1實施形態申’包含與預備之DAC電路28 相對應之預備之取樣電路26及保持電路^。因此，不僅於 • DAC電路8存在不良之情形時，而且於取樣電路6或保持電 H形時m刀換為預備之取樣電路26及 保持電路28。 其人以下參照圖25，對自搭載有積體電路1〇之顯示裝 φ 4之電源接通起至進行動作確認測試後移行至-般動作為 止的順序進行說明。圖25係表示自顯示裝置之電源接通起 至進行動作確認測試後移行至一般動作為止之處理順序的 流程圖。 如該圖所示，首先，將顯示裝置接通電源，使積體電路 10初始化，藉此判定旗標4全部成為「L」旗標（S81)。然 後’控制電路使test信號為「H」，使⑽B信號為「L」 後，將積體電路ίο切換為動作確認測試之狀態（s82)。接 • 著，控制電路及積體電路10進行上述動作確認測試 (S83)。進而，控制電路對全部動作確認測試丨〜5是否結束 進行確認，將成為不良之電路切換為預備之電路後，移行 至一般動作（S84)。 (運算放大器1之動作確認） 上述動作確認測試係以運算放大器1不存在不良為前 提。然而，運算放大器丨中亦存在產生不良之可能性。2 此，本實施形態中，宜於進行上述動作確認測試之前，進 行運算放大器1之動作確認。因此，以下參照圖26，亦對 143488.doc -49- 201030412 運算放大器1之動作確認進行說明。圖26係表示運算放大 器1及用於運算放大器丨之動作確認之周邊電路之構成的說 明圖。 如該圖所示，於輸入來自DAC電路8之輸出與輸入特定 之電壓之間進行切換的開關S5連接於運算放大器丨之正極 性輸入端子。進而，於兩個特定之電壓VreH及Vref2之間 進行切換之開關S3連接於開關S5之b侧（特定電壓之輸入 侧）。另一方面，於輸入用以進行來自運算放大器丨之負反 饋之運算放大器1之輸出與輸入特定之電壓之間進行切換 的開關S6連接於運算放大器i之負極性輸入端子。進而， 於兩個特定之電壓Vrefl及Vref2之間進行切換之開關84連 接於開關84之8側（特定電壓之輸入側）。 其次’對運算放大器1之一般動作進行說明。於運算放 大器1之一般動作時，使開關S5位於A側（DAC電路8之輸出 側）’使開關S6位於A側，藉此運算放大器1作為電壓隨動 器之電路進行動作。 其次，以下對用以進行運算放大器1之動作確認之順序 進行說明。首先’將開關S1及S2切換至B側。藉此，不存 在運算放大器1之負反饋，而運算放大器1作為比較器進行 動作。然後，將開關S3及S4切換至A側。藉此，運算放大 器1之正極性輸入端子輸入Vref 1，負極性輸入端子輸入 Vref2。於此，Vrefl及Vref2為預先生成之電壓，且使 Vrefl之電壓值為較Vref2之電壓值更大之值。再者，使 Vrefl與Vref2之電壓值之差為較運算放大器1之輸入輸出偏 143488.doc -50- 201030412 移值更大之值。此時，與輪入$ ig ., ^ λ 5 、 、極性輸入端子之Vref2 相比’輸入至正極性輸入端子之％ 運算放大器1輸出「Η」位準之广辨 壓較南，因此 自」料之^。判定電路3檢測出來 • Γ 大以之輸出後，與自身所記憶之期望值「H」 進：比較。於此，於運算放大器!之輸出為「L」位準之情 形時，判定電路3可判定為運算放大器1存在不I。再者， 判疋電路3所記憶之期望值係自控制電路提供。 參 其次’亦考慮有運算放大器1之比較器動作存在不良， 二僅能輸出「H」位準之情形。因此，將開關 及S4切換至B侧’將_輸入至運算放大器以正極性 輸入端子’將Vrefl輸入至負極性輸入端子。此時，盘輸 :至正極性輸入端子之Vref2相比，輸入至負極性輸入端 子之Μ1之電壓值更高，因此運算放大器！輸出「L」位 準。判定電路3檢測出來自該運算放大器！之輸出後，盘自 身所記憶之期望值「L」進行比較。於此，於運算放大以 釀 < 輸出為「H」位準之情形時，判定電路3可判定為運算放 存在不良。再者，開關係藉由控制電路進行切 [實施形態2] —其次，以下參照圖27〜圖33 ,對本發明之第2實施形態進 行說月再者，實施形態2之說明係僅對與實施形態1不同 之地方進行說明，對於重複之地方省略其說明。 首先，對實施形態1與實施形態2之不同進行簡單說明。 實施形態1係於運算放大Si中將DAC電路8之輸出與預備 143488.doc 51· 201030412 之DAC電路28之輸出進行比較。另一方面，實施形態2係 將彼此鄰接之兩個DAC電路8設為一組而於運算放大器】中 對來自彼此之DAC電路8之輸出進行比較。 (顯示驅動用半導體積體電路2〇之構成） 參照圖27對本發明之顯示驅動用半導體積體電路（以下 稱作積體電路）20之構成進行說明。圖27係表示積體電路 20(顯示裝置驅動用之積體電路）之構成之說明圖。 運算放大器1將來自串聯連接於自身之DAC電路8之輸出 輸入至自身之正極性輸入端子。進而，運算放大器丨將來 自串聯連接於自身所鄰接之運算放大器之DAC電路8之輸 出輸入至自身之負極性輸入端子。具體而言，如該圖所 不，運算放大器1-1將來自DAC電路8_丨之輸出輸入至自身 之正極性輸入端子，將來自DAC電路8_2之輸出經由開關 2a而輸入至自身之負極性輸入端子。同樣地運算放大器 1-2將來自DAC電路8_2之輸出輸入至自身之正極性輸入端 子，將來自DAC電路8-1之輸出經由開關2a而輸入至自身 之負極性輸入端子。又，積體電路2〇包含預備之取樣電路 26八及268、預備之保持電路27八及278、預備之1)八^；電路 28A及28B、運算放大器2ia及21B、以及上拉與下拉電路 25A及25B。運算放大器21A中，亦將來自DAC電路28a之 輸出輸入至自身之正極性輸入端子，將來自DAc電路28B 之輸出經由開關2a而輸入至自身之負極性輸入端子。進 而，運算放大器21B中，亦將來自DAC電路28B之輪出輸 入至自身之正極性輸入端子，將來自DAC電路28a之輸出 143488.doc -52· 201030412 經由開關2a而輸入至自身之負極性輸入端子。 (積體電路20之一般動作） 於積體電路20之一般動作中，與實施形態i同樣地，控 制電路使test信號成為「L」位準，使㈣則言號成為「H」 位準》藉此，DAC電路8將自保持電路7輸入之灰階資料轉 換為灰階電壓信號並作為灰階電壓輸出至運算放大器 正極性輸入端子。於此，因開關孔為〇1^，故運算放大器i ❹=輸出成為向自身之負極性輸人端子之負反饋。藉此，運 异放大器1作為電壓隨動器進行動作。藉此，運算放大器1 將來自獄電吸灰⑽加鳴應=各 輸出端子OUT1〜OUTn。 (動作確認測試之切換） 向積體電路20之動作確認測試之切換中，控制電路使 testk號成為「Η」位準，使化以則言號成為「[」位準。首 先’因開關2a為0Ν，故將TSTR1信號輸入至取樣電路26α • 及第奇數個取樣電路6(取樣電路6-1、6_3、…、6_(η_υ)。 進而，將TSTR2信號輸入至取樣電路26Β及第偶數個取樣 電路6(取樣電路6-2、6-3、...、6-小進而，因開關2&成為 Ν故對第奇數個運算放大器丨之負極性輸入端子輸入鄰 接之來自第偶數個DAC電路8之輸出，對第偶數個運算放 大器1之負極性輸入端子輸入來自鄰接之第奇數個〇八。電 路8之輸出。又，因test Β信號為「L」位準，故開關u為 〇奸。藉此’將運算放大器!之自身之輸出向負極性輸二 端子的負反饋阻斷。其結果，運算放大器丨成為將來自串 143488.doc •53- 201030412 聯連接於自身之DAC電路8之輸出與來自鄰接之dac電路8 之輸出進行比較的比較器。 (實施形態2之動作確認測試” 其次，以下參照圖28對第2實施形態之動作確認測試之 第一順序進行說明。圖28係表示第2實施形態之動作確認 測試之第一順序之流程圖。 首先，控制電路使test信號成為「H」位準使“Μ B信 號成為「L」位準（S101)。藉此，運算放大器i作為比較器 進行動作（S102)。然後，控制電路將第奇數個判定電路 3(判定電路3_1、3-3、...、3-(n·!))之期望值設定為「L」 位準。另一方面，控制電路將第偶數個判定電路3(判定電 路3-2、3·4、...、3_n)之期望值設定為「H」位準。 繼而，控制電路將自身所包含之計數器瓜初始化為 〇(S103)。進而，控制電路使TSTR1有效後，取樣電路26a 及第奇數個取樣電路6經由資料匯流排而輸入灰階m之灰階 資料。又，控制電路使TSTR2有效後，取樣電路26B及第 偶數個取樣電路6經由資料匯流排而輸入灰階m +丨之灰階 資料（S104)。 於此’若考慮計數器m之值為〇之情形，則第奇數個運 算放大器1將灰階0之灰階電壓，自串聯連接於自身之第奇 數個DAC電路8輸入至自身之正極性輸入端子。又，第奇 數個運算放大器1將灰階1之灰階電壓，自鄰接之第偶數個 DAC電路8輸入至自身之負極性輸入端子。於此，若連接 於運算放大器1之兩個輸入端子之DAC電路8為正常，則第 143488.doc -54- 201030412 奇數個運算放大器1之輸出為「L」。另一方面，第偶數個 運算放大器1將灰階1之灰階電壓，自串聯連接於自身之第 偶數個DAC電路8輸入至自身之正極性輸入端子。又，第 偶數個運算放大器1將灰階〇之灰階電壓，自鄰接之第奇數 個DAC電路8輸入至自身之負極性輸入端子。於此，若連 接於運算放大器1之兩個輸入端子之DAC電路8為正常，則 第偶數個運算放大器1之輸出為「H」。 然後，判定電路3對來自運算放大器】之輸出信號之位準 是否與自身所記憶之期望值一致進行判定（sl〇5)。於此， 於來自運算放大W之輸出與期望值不同之情形時，判定 電路3將「H」旗標輸出至判定旗標4(S1()6)。將計數器瓜之 值I增加而反覆進行以上之S1 04〜S 106之處理直至計數 器m之值成為nj為止（sl〇7、sl〇8)。 (實施形態2之動作確認測試2) ”人卩T參照圖29對第2實施形態之動作綠認測試之 第二順序進行說明。圖29係表示第2實施形態之動作確認 測試之第二順序之流程圖。 第2實施形態中之動作確認測試2係將第2實施形態中之 動作確w K 1中之第奇數個與第偶數個灰階之電壓關係 颠倒過來的動作確認，除此之外，與第2實施形態中之動 作確認測試相同。 「H &制電路將第奇數個判電路3之期望值設定為 「 另方面，將第偶數個判定電路3之期望值設定為 」進而，控制電路將自身所包含之計數器m初始化 143488.doc -55- 201030412 為0(S111)〇 接著，控制電路使TSTR1有效後，取樣電路26A及第奇 數個取樣電路6經由資料匯流排而輸入灰階m+1之灰階資 料。又，控制電路使TSTR2有效後，取樣電路26B及第偶 數個取樣電路6經由資料匯流排而輸入灰階m之灰階資料 (S112) 〇 於此’若考慮計數器m之值為〇之情形，則第奇數個運 算放大器1將灰階1之灰階電壓’自串聯連接於自身之第奇 數個DAC電路8輸入至自身之正極性輸入端子。又，第奇 數個運算放大器1將灰階〇之灰階電壓，自鄰接之第偶數個 DAC電路8輪入至自身之負極性輸入端子。於此，若連接 於運具放大器1之兩個輸入端子之DAC電路8為正常，則第 奇數個運算放大器1之輸出為ΓΗ」位準。另一方面，第偶 數個運算放大器1將灰階0之灰階電壓，自串聯連接於自身 之第偶數個DAC電路8輸入至自身之正極性輸入端子。 又第偶數個運异放大器1將灰階1之灰階電壓，自鄰接之 第奇數個DAC電路8輸入至自身之負極性輸入端子。於 匕若相連接於運算放大器1之兩個輸入端子之DAC電路8 為正常，則第偶數個運算放大器丨之輸出為「L」位準。 其次，判定電路3將來自運算放大器丨之輸出之位準與自 身所C憶之期望值進行比較（S113)。於此，於來自運算放 大器1之輸出與期望值不同之情形時，判定電路3將「H」 旗標輸出至判定旗標[將計數h之值逐_增加而反覆進 仃以上之S112〜S114之處理直至計數器值成為n i為止 143488.doc 201030412 (SI 15、SI 16)。 (實施形態2之動作確認測試3) 其次，以下參照圖30對第2實施形態之動作確認測試之 .^三順序進行說明。圖30係表示第2實施形態之動作確認 測试之第三順序之流程圖。 如第1實施形態之動作確認測試3中所說明般存在如下情 形.於DAC電路8中存在輸出端成為開路之不良之情形 參 _ ’運异放大器1會持續保持藉由已執行之確認測試而輸 入至運算放大器1之灰階電壓，從而於實施形態2之動作確 認測試1及2中無法檢測出不良。 首先，與動作確認測試1〜2同樣地，控制電路將自身所 包含之計數器m之值初始化為〇(sl21)。又，積體電路2〇 中，將上拉與下拉電路5連接於DAC電路8之正極性輸入端 子。於此，控制電路以將第奇數個運算放大器丨之正極性 輸入端子上拉之方式控制上拉與下拉電路5(S122)。其結 • 果，於第奇數個DAC電路8之輸出端為開路之情形時，對 第奇數個運鼻放大器1之正極性輸入端子輸入較高之電 壓。另一方面’控制電路以將第偶數個運算放大器1之正 極性輸入端子下拉之方式控制上拉與下拉電路5(S122)。 其結果，於第偶數個DAC電路8之輸出端成為開路之情形 時’對第偶數個運算放大器1之正極性輸入端子輸入較低 之電壓。 其後之S123〜S127之處理與第2實施形態之動作確認測試 1相同，因此於此省略其說明。 143488.doc •57· 201030412 (實施形態2之動作確認測試4) 其次，以下參照圖3丨對第2實施形態之動作確認測試之 第四順序進行說明。圖31係表示第2實施形態之動作確認 測試之第四順序之流程圖。 於此之目的在於檢測與上述動作確認測試3相同之不 良。首先，與至此為止之動作確認測試同樣地，控制電路 將自身所包含之計數器m之值初始化為〇(s丨3丨）。然後控 制電路以將第奇數個運算放大器1之正極性輸入端子下拉 之方式控制上拉與下拉電路5(S122)。其結果，於第奇數 個DAC電路8之輸出端成為開路之情形時，對第奇數個運 算放大器1之正極性輸入端子輸入較低之電壓。另一方 面’控制電路以將第偶數個運算放大器丨之正極性輸入端 子上拉之方式控制上拉與下拉電路5 (S 122)。其結果，於 第偶數個DAC電路8之輸出端成為開路之情形時，對第偶 數個運算放大器1之正極性輸入端子輸入較高之電壓。 其後之S133〜S137之處理與第2實施形態之動作確認測試 2相同，因此於此省略其說明。 (實施形態2之動作確認測試5) 其次’以下參照圖3 2對第2實施形態之動作確認測試之 第五順序進行說明。圖32係表示第2實施形態之動作確認 測試之第五順序之流程圖。 如第1實施形態之動作確認測試5中已說明般，於DAC電 路8中存在產生自身中之鄰接之兩個灰階短路之不良的情 形。第2實施形態之動作確認測試5之目的在於檢測此種不 143488.doc -58· 201030412 良。 如該圖所示，首先，控制電路將自身所包含之計數器m 之值初始化為0(S141)。其次，使TSTR1及TSTR2有效，進 而，經由資料匯流排將灰階m之灰階資料輸入至取樣電路 26A、取樣電路26B以及取樣電路6。進而，藉由使資料 LOAD信號有效，第奇數個DAC電路8及第偶數個DAc電路 8輸出相同之灰階„!之灰階電壓（S142)。然後，控制電路經 φ 由未圖示之開關而使運算放大器1之正極性輸入端子與負 極性輸入端子短路。藉由使該運算放大器〖之正極性輸入 端子與負極性輸入端子短路，而使得運算放大器丨之正極 性輸入端子及負極性輸入端子輸入相同之灰階電壓。其 次，判定電路3將使運算放大器〗之正極性輸入端子與負極 性輸入端子短路之情形時的運算放大器之輸出之位準作為 期望值加以記憶（S143)。 繼而，使未圖示之開關成為OFF，而解除運算放大器1 馨之正極性輸入端子與負極性輸入端子之短路。此時，對第 奇數個運算放大器1之正極性輸入端子，輸入來自串聯連 接於自身之第奇數個DAC電路8之灰階m之灰階電壓，對負 極輸入端子輸入來自鄰接於自身之第偶數個電路8 之灰階m之灰階電壓。另一方面，對第偶數個運算放大器】 之正極性輸入端子，輸入來自串聯連接於自身之第偶數個 DAC電路8之灰階m之灰階電壓’對負極性輸入端子輸入來 自鄰接於自身之第奇數個DAC電路8之灰階m之灰階電壓。 於此，判疋電路3將自身所記憶之期望值與來自運算放大 143488.doc -59- 201030412 器1之輸出進行比較（S 144)。進而，於來自運算放大器】之 輸出與自身所記憶之期望值不同之情形時，判定電路3將 「H」旗標輸出至判定旗標4 ^進而，判定旗標4將自判定 電路3輸入之「H」旗標記憶於自身之内部。 然後，控制電路使用未圖示之開關，將來自DA(：電路8 之輸入至運算放大器丨之正極性輸入端子之信號、與輸入 至負極性輸入端子之信號加以調換（S146)。之後，進行與 S147之處理相同之處理（S147)。又，與SM5同樣地，於來 自運算放大器1之輸出與自身所記憶之期望值不同之情形 時，判定電路3將「H」輸出至判定旗標4(S148)。 使計數器m之值增加丨而反覆進行以上之si42〜si48之處 理直至計數器m之值成為11為止（S149、si5〇)。 (實施形態2之自我修復） ，其次，以下參照圖33 ’對在判定旗標4記憶有「h」之情 形時換。之於上述動作確認測試】〜5中判定電路3判定為 DAC電路8之任-者存在*良之情形時的修復進行說明。 圖33係表示於判定為不良之Dac 28A及28B之間進行切換而 圖。 電路8與預備之DAC電路 進行自我修復之順序的流程 首先，控制電路對判定旗標4是否記憶有「H」進行檢測 (s!51)。於控制電路檢測出判定旗⑸未記憶n形 時，移行至Sl53之處理。另__ ^ —方面’於控制電路檢測出記 憶有「H」之判定旗標4之愔形 馆化時，將與記憶有「Η」之判 疋旗標4相對應之DAC電路 电路8切換為預備之dac電路28A或 143488.doc 201030412 28B。於此，實施形態2中，因將兩個dac電路8作為一組 進行動作確認，故即便判定旗標4記憶有「h」旗標，仍無 法判斷-組中之哪一個DAC電路為不良。因此實施形離 2中，將與記憶有「H」之判定旗標4相對應之—組之dac 電路8、換言之第奇數個及第偶數個此兩個dac電路8切換 為預備之DAC電路28A及28B(S152)。作為具體之說明以 下設為DAC電路8-1存在不良而進行說明。 於此，於DAC電路8_丨存在不良之情形時，藉由動作確 認測試卜5,判定電路3]及3_2均將「H」輸出至判定旗標 4 1及4-2。進而，判疋旗標4_ 1及4-2將自判定電路3-1及3-2 輸入之「Η」旗標輸出至開關2(；及2d，使開關&成為 OFF ’使開關2d成為ON。其結果，取樣電路26A輸入STR1 仏號’取樣電路26B輸入STR2信號。藉此，取樣電路26A 自資料匯流排取得與液晶驅動用信號輸出端子OUT 1相對 應之灰階資料’又，取樣電路26B自資料匯流排取得與液 晶驅動用信號輸出端子OUT2相對應之灰階資料。進而， 因開關2c為OFF，故將運算放大器1_1之輸出端與液晶驅動 用信號輸出端子OUT1之連接斷開，亦將運算放大器ι_2之 輸出端與液晶驅動用信號輸出端子OUT2之連接斷開。進 而，因開關2d為ON，故運算放大器21A之輸出端連接於液 晶驅動用信號輸出端子OUT1，運算放大器21B之輸出端連 接於液晶驅動用信號輸出端子OUT2。 如上所述，將存在不良之DAC電路8及與其成對之DAC 電路8作為一組而切換為預備之DAC電路28 A及28B，藉此 143488.doc -61 · 201030412 可將存在不良之DAC電路8切換為預備之DAC電路26A或 26B 〇 繼而’控制電路使test信號為「L」，使test b信號為 「H」後，移行至一般動作（S153)。 [實施形態3] 以上說明之實施形態丨及實施形態2中，於來自輸出電路 區塊30(參照圖2)之灰階電壓與來自預備輸出電路區塊 4〇(參照圖2)之灰階電壓之間進行切換的切換電路6〇(參照 圖2)為包含於積體電路1〇及2〇中之構成’但本發明並不限 疋於此’切換電路60亦可為包含於顯示面板側之構成。 以下’將於顯示面板侧包含切換電路60之顯示部9〇,之 構成及動作作為本發明之第3實施形態進行說明。再者， 本實施形態中，對與實施形態1不同之處進行說明，而對 於重複之地方省略其說明。 (顯示部90'之概略構成） 首先’參照圖34對本實施形態之顯示部9〇’之概略構成 進行說明。圖34係表示顯示部90,之概略構成之方塊圖。 如圖34所示’顯示部90'包含顯示面板8〇,、及根據自外 部輸入之灰階資料而驅動顯示面板8〇’之積體電路1〇，（驅動 電路）。於此’積體電路1〇,中’與實施形態1之積體電路1〇 不同之方面在於未包含切換電路6〇,其他構成為與積體電 路10相同之構成。又，顯示面板80,中，與實施形態J之顯 示面板80不同之方面在於包含切換電路60，其他構成為與 顯示面板80相同之構成。 143488.doc -62- 201030412 (顯示部90’之構成） 其次，參照圖35對本實施形態之顯示部90,之更詳細之 構成進行說明。圖35係表示積體電路10，之構成之方塊圖。 如圖35所示，積體電路1〇,包含：η個取樣電路6，其自 灰階資料輸入端子（未圖示）經由資料匯流排而輸入與η個輸 出端子OUT1〜OUTn之各自相對應之灰階資料；η個保持電 路7 ; DAC電路8 ’其將灰階資料轉換為灰階電壓信號；運 算放大器1 ,其對來自DAC電路8之灰階電壓信號具有緩衝 器電路之作用；η個判定電路3 ;以及η個上拉與下拉電路 5 ° 進而，如圖35所示，積體電路10，包含：根據test信號於 ON與OFF之間進行切換之複數個開關2a ;根據test B信號 於ON與OFF之間進行切換之複數個開關2b ;以及根據 LF(L〇w Frequency，低頻）信號於⑽與〇FF之間進行切換 之複數個開關2f。再者，開關2a、2b以及2f於輸入有 「H」信號之情形時為〇>;，於輸入有「L」信號之情形時 為OFF。進而，積體電路1〇，包含各為一個之以下電路：預 備之取樣電路26 ;預備之保持電路27 ;預備之DAC電路 28，預備之運算放大器21以及預備之輸出端子〇υτ〇。 另一方面，如圖35所示，顯示面板8〇，包含：連接於積 體電路ίο’所包含之輸出端子OUT1〜〇UTn之各自之連接端 子（未圖不）；判定旗標9_丨〜9_η(以下，於總稱之情形時稱 作判疋旗標9);根據來自控制電路（未圖示）iLF信號而於 ON與OFF之間進行㈣之開關2f ;根據哪號之反轉信號 143488.doc •63- 201030412 即 LFB(Low Frequency Band，低頻帶）信號而於 與 qff 之間進行切換之開關2e ;以及根據來自判定旗標9之輸出 信號即Flag 1〜Flagn而於ON與OFF之間進行切換之開關& 及2d。再者，開關μ、2e以及2f於輸入有「Η」信號之情 形時為ON，於輸入有「L」信號之情形時為OFF。又，開 關2c於輸入有「Lj信號之情形時為ON，於輸入有γη」 信號之情形時為OFF。 又’本實施形態中之顯示面板80,為液晶顯示面板，如 圖35所示’資料信號線;5L-1〜SL-n(以下，於總稱之情形時 稱作資料信號線SL)經由開關2e及2c而連接於積體電路1〇, 之各個輸出端子OUT。又，數量與掃描信號線GL之根數相 同之像素P連接於各個資料信號線SL。再者，圖35中，將 連接於資料信號線SL-1之像素P作為像素Pd，將連接於資 料信號線SL-n之像素P作為像素p_n。 (實施形態3之自我修復） 其次，對在本實施形態之顯示部90,中進行動作確認測 試之結果為判定旗標4記憶有「H」旗標之情形時的自我修 復動作進行說明。再者，本實施形態中之動作確認測試^ 方法與實施形態1申所述之動作確認測試〗〜5相同因此於 此省略動作確認測試之說明。 首先，於動作確認測試丨〜5結束之時間點，信號為 「H」’ test B信號成為「L」。因此’藉由開㈣而將運 算放大器1與輸出端子〇UT之連接斷開。於此，於動作確 認測試1〜5結束後，控制電路輸出「H」之^信號，並且 143488.doc • 64 · 201030412 1出L」之咖信號。藉由輸出該「Η」之LF信號，開關 成為0N各個判定旗標4經由各輸出端子OUT而連接於 ，判疋旗標9。進而’各個判定旗標4將自身所記憶之 '、丁或乙j旗標作為Fiagl〜Fiagn，經由各輸出端 子OUT而輸出至各判定旗標9。各判定旗標9將自判定旗 4輸出之F㈣〜Flagn記憶於自身之内部記憶體中，並^ 出至連接於自身Ώ 身之開關2c及2ί^再者，於LF信號為ΓΗ」 d門LFB 號成為「L」，因此各開關&為〇FF。藉 此，防止將判定旗標4所輸出之Hagl〜Flagn輸出至資料作 =L广，其結果判定旗標4所輸出之⑽〜一 會對像素P產生影響。 以下’作為顯示部90,中之自我修復動作之詳細說明， 以與輸出端子〇UT1相對應之判定旗標W記憶有 標之情形為例進行說明。 ❿ 「首先’於與輸出端子〇UT1相對應之判定旗標^記憶有 :Η」旗標之情形時，換言之於dac電路8]為不良之情形 判定旗標9·1中自判定旗標4輸出有「H」旗標，且將 所輸出之「H」旗標記錄於自身所包含之内部記憶體中。 再者’於此示例中，判定旗標4_2〜4_n記錄有％旗標。 然後，判定旗標9]將「H」旗標之_輸出至連：於 自身之開關2C及2d。藉此，連接於判定旗㈣之開關2: 將輸出端子0UT1與資料信號線SL-1之連接切斷，進而 接旗標9々„2d使輸出端子⑽q與資料信號線 連接。另一方面’各個判定旗標對連接於自 143488.doc •65· 201030412 身之開關2C及2d輸出「L」旗標之Flag2〜Flagn，因此連接 於判定旗標9-2〜9-n之開關2c成為ON，連接於判定旗標9_ 2〜9-n之開關2d成為0FF ^其結果，各個資料信號線sl_ 2〜SL-n經由開關2e而連接於各個輸出端子OUT2〜〇υΤη。 各判定旗標9根據來自判定旗標4之Flag 1〜Flagn，對連接 於自身之開關2c及2d進行切換後，控制電路輸出「l」之 LF信號，並且輸出ΓΗ」之lFB信號。藉此，使各個輸出 端子OUT2〜OUTn與各個資料信號線SL-2〜SL-n連接。 接著’控制電路輸出「L」之LF信號後，輸出「[」之 test信號與「H」之test B信號，藉此資料信號線SL_i經由 輸出端子OUTO而連接於運算放大器21之輸出端，另一方 面’各個資料信號線SL-2〜SL-n經由輸出端子〇υτ2〜OUTn 而連接於運算放大器1-2〜1-η〇再者’連接於取樣電路 之開關2d根據來自判定旗標4_1之pqagi而成為on，因此輸 入至取樣電路6-1之灰階資料（與資料信號線SL_丨相對應之 灰階資料）亦輸入至取樣電路26。其結果，與資料信號線 SL-1相對應之灰階資料自輸出端子〇uT〇，而代替自輸出 端子OUT1輸入至資料信號線sl-^再者，輸入至取樣電 路6及各個預備之取樣電路26之灰階資料之切換與實施形 態1中之動作相同，因此於此省略其詳細說明。 如上所述，顯示部90·進行自我修復動作，藉此可使用 預備之DAC電路28而代替檢測為不良之Dac電路8，將正 常之灰階電壓輸出至資料信號線SL。再者，與實施形態i 同樣地，本實施形態中，亦包含與預備之DAC電路28相對 143488.doc • 66 - 201030412 應之預備之取樣電路26及保持電路27。因此，不僅於 電路8 ’而且於取樣電路6或保持電路7存在不良之情形 時’亦可切換為預備之取樣電路26及保持電路28。 其次，以下參照圖36，對顯示部90,中之自電源接通起 至進行動作確認測試後移行至一般動作為止之順序進行說 明。圖36係表示自顯示部9〇,之電源接通起至進行動作確認 泪J β式後移行至一般動作為止之處理順序的流程圖。 ❿ 圖所示首先，顯示部90’檢測出由使用者接通電 源後，將積體電路10初始化，藉此使判定旗標4所記憶之 所有旗標成為「L」旗標（s 161)。然後’控制電路使恍^信 號為Η」，使test Β信號為「L」後，將積體電路1〇，切換 為動作確認測試之狀態（S162)。接著，控制電路及積體電 路1〇進行上述之動作確認測試（S163)。進而，控制電路對 所有動作確認測試丨〜〗是否結束進行確認（s丨64) ^若於該 S 1 64中控制電路檢測出並非所有動作確認測試1〜$已結 • 束，則顯示部90,根據來自控制電路之指示，將處理移行至 S163，進行未結束之動作確認測試。另一方面若於“以 中控制電路確認出顯示部9〇,中所有動作確認測試已結束， 則於輸出「H」2LF信號及「L」之LFB信號而檢測出成為 良之電路（取樣電路6、保持電路7、DAC電路9、運算放 大器1)之情形時，將該不良電路切換為預備之電路（取樣電 路26、保持電路27、DAC電路29、運算放大器21)後移行 至一般動作（S165)。 再者，本實施形態中之顯示部90,中係作為記憶判定電 143488.doc -67- 201030412 路3-1之判定結果即旗標之電路而包含判定旗標*及判定旗 標9的構成，但作為顯示部90,之變形例，亦可為不包含判 疋旗軚9、開關2f、開關2e，且判定旗標4控制開關2c及2d 之構成。此時，不需要控制開關2[及26之1^信號及lfb信 號’另一方面’需要用以使判定旗標4與開關以及2d連接 之配線及連接端子。 [實施形態4] 以上說明之實施形態1〜實施形態3中係積體電路與顯示 面板經由輸出端子〇υτ而連接之構成，但積體電路與顯示 面板不經由輸出端子OUT而成為一體之顯示裝置亦包含於 本發明之範嘴内。 以下，參照圖37’將積體電路與顯示面板成為一體之顯 示部90”作為第4實施形態進行說明。再者，本實施形態之 顯示部90”為實施形態1之顯示部9〇之變形例，本實施形態 中’對與實施形態1不同之處進行說明，而對重複之地方 省略其說明。 (顯示部90"之構成） 首先’參照圖37對本實施形態之顯示部90”之構成進行 說明。圖37係表示顯示部90"之構成之方塊圖。 如圖37所示’顯示部90"與實施形態1中所示之積體電路 10及顯示面板80並無區別，運算放大器之輸出端經 由開關2b、2c以及2d而直接連接於資料信號線sl。即，本 實施形態之顯示部90"中’與實施形態1之顯示部9〇不同之 方面在於是否包含輸出端子OUT之不同，其他構成與實施 143488.doc -68- 201030412 形態1之顯示部90相同。 再者，本實施形態中，作為實施形態1之變形例進行說 月彳一自不用說，實施形態2及3亦同樣地，積體電路與顯 "面板不、，由輸出端子OUT而成為一體之顯示裝置亦包含 於本發明之範疇内。 (電視系統） 其次，參照圖38對包含實施形態1之顯示部9〇之電視系 ❹ 統300進行說明。再者，圖38係表示電視系統300之構成之 方塊圖。再者，以下將電視系統300作為包含實施形態1之 顯示部90者進行說明，但本發明之電視系統並不限於此， 亦可為包含實施形態2〜4之顯示裝置而代替顯示部90之構 成。 (電視系統300之構成） 如圖38所示，電視系統3〇〇包含：天線3〇1，其接收廣播 波，調諧器部302，其將接收到之廣播波解調為影像聲音 • 化號；信號分離部303，其將解調之影像聲音信號分離為 衫像仏號與聲音信號；影像信號處理部3〇4，其將分離之 影像信號解碼為數位影像信號；顯示部9〇，其取得解碼之 數位影像信號而作為灰階資料，且根據所取得之灰階資料 • 而於顯示面板80(參照圖2)上顯示影像；聲音信號處理部 3〇5其將分離之聲音k號解碼為數位聲音信號；以及聲 音k號輸出部306，其將解碼之數位聲音信號轉換為類比 聲音信號後，將轉換之類比聲音信號作為聲音自揚聲器輸 出。 143488.doc •69- 201030412 (電視系統300之動作） 其··人，對電視系統300中之動作處理進行說明。首先， 天線301接收來自廣播台之廣播波並將接收到之廣播波 輸出至調諧器部302。調譜器部搬將所輸出之廣播波解調 為影像聲音信號並輸信號分離部3()3。錢分離部如 將所輸出之影料音信號分離為影像㈣與聲音信號並將 各信號輸出至影像信號處理部3〇4及聲音信號處理部3〇5。 影像信號處理部304將所輸出之影像信號解碼為數位影像 信號，並將解碼之數位影像信號作為灰階資料而輸出至顯 示部90。顯示部9〇使用自身所包含之顯示面板⑽而顯示輸 出之灰階資料。另一方面，聲音信號處理部3〇5將由信號 分離部303所分離之聲音信號解碼為數位聲音信號並輸出 至聲音輸出部306。聲音信號輸出部3〇6將輸出之數位聲音 信號轉換為類比聲音信號後，使用自身所包含之揚聲器而 將類比聲音信號作為聲音加以輸出。 再者，本發明之電視系統3〇〇為使用天線3〇1及調諧器部 302作為取得影像聲音信號之機構而自廣播局取得影像聲 音信號之構成’但本發明並不限於此，亦可為自記錄媒體 讀出記錄於該記錄媒體中之内容資料之DVD播放器等内容 讀取裝置、或者經由PC(個人電腦）自網際網路等取得資料 之構成。 實施形態1及實施形態4中所說明之動作確認測試及自我 修復之處理動作係於剛將液晶驅動用半導體積體電路丨〇接 通電源後便進行該動作之構成’但本發明並不限於此亦 143488.doc -70- 201030412 可成為藉由將控制信號輸入至液晶驅動用车 1Λ 卞導體積體電路 10而進行上述動作之構成，且可於任意之時 _ ^ 呵間點進行上述 動作。例如亦可於自顯示裝置之控制器將表 '、-員示之返馳 期間之信號輸入至液晶驅動用半導體積體雷％ t 畑电唂1〇之時間點 上’進行動作確認測試、自我修復。 ‘Next, with reference to Fig. 24, in the case where the determination flag 4 has a "Η" flag, in other words, in the above-described operation confirmation test 丨 5, the determination circuit 3 determines that it is any one of the DAC circuits 8 - Η. The repair in the case of a bad situation is explained. FIG. 24 is a flowchart showing that the flow determination circuit 3 in the sequence of self-repairing between the DAC circuit 8 determined to be defective and the standby DAC circuit 28 is self-repairing, and the "n flag wheel" is set when the DAC circuit 8 is determined to be defective. Going to the judgment flag 4. Further, the shirt flag 4 input comes from the judgment "i" 3 "H" flag and is stored inside itself. Here, whether or not the control circuit has recorded "H" is detected (S7l). : Measure: When the judgment flag 4 has not memorized %, the transition to the heart--the control circuit detects the judgment flag, and confirms the number of each of the judgment flags q VII. Here, when it is determined that the flag 2 of the flag 4 is : a plurality of cases, the process proceeds to S73: The other flag = the flag number of the "H" remembered by the flag 4 is - the other two sides: to the processing (S72). In the case of a solid shape, symmetry 143488.doc • 47· 201030412 In S74, processing is performed to switch the DAC circuit 8 corresponding to the judgment flag* of the memory "H" flag to the preliminary DAC circuit 28 ( S74). First, when the switching sequence between the defective DAC circuit 8 and the standby DAC circuit 28 is described, the determination flag corresponding to the liquid crystal driving signal output terminal OUT1 is set to have the "H" flag stored therein. By. The flag 4-1 outputs the output signal of the Flagi which becomes the "H" level to the switches 2c and 2d. According to the output signal of Flagl, the switch 2c to which the signal of the "H" level has been input is turned OFF, and the switch 2d becomes 〇N. Thereby, the switch 连接 disconnects the output terminal of the operational amplifier 1-1 from the liquid crystal drive signal output terminal ❹ ο υ τι. On the other hand, the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit %. Thereby, the gray scale data corresponding to the output terminal No. 6 of the liquid crystal driving is also stored in the sampling circuit 26. Further, the switch 2d connects the output terminal of the operational amplifier 21 to the liquid crystal driving signal output terminal OUT1. As described above, according to the output signal of Flag1 from the judgment flag 4-1, the switches 2 (: and 2 (1 are switched to thereby switch the defective DAC circuit 8.1 to the preliminary dAC circuit 28). The processing of S73 will be described. When it is determined that the number of "marks" stored in the flag 4 is plural, it is considered that the prepared DAc circuit 28 can be defective. Therefore, the control circuit makes the decision in S73. After all the flags of the flag 4 of the flag 4 have become the "L" flag, the process proceeds to S75. Secondly, when it is judged as NO in 871, after the processing of S73 or after the processing of S74 The control circuit switches the test signal to "L", switches the test B number to "H", and then moves to the normal action (S75). As described above, by performing the action confirmation test 1 to 5 and self-repairing 143488.doc -48- 201030412, the integrated circuit 10 can switch the defective dac circuit to the preliminary dac power, and the first embodiment includes a preliminary sampling circuit 26 and a holding circuit corresponding to the prepared DAC circuit 28. ^. Therefore, not only when the DAC circuit 8 is in a bad situation, but also When the sampling circuit 6 or the electric H-shape is held, the m-knife is replaced with the preliminary sampling circuit 26 and the holding circuit 28. Referring to Fig. 25, the power supply from the display device φ 4 on which the integrated circuit 1 is mounted is turned on. The procedure for moving to the normal operation after the operation check test is performed will be described. Fig. 25 is a flowchart showing the processing procedure from the power-on of the display device to the normal operation after the operation check test is performed. First, the display device is powered on, and the integrated circuit 10 is initialized, thereby determining that all the flags 4 are "L" flags (S81). Then the control circuit makes the test signal "H", so that the (10) B signal When it is "L", the integrated circuit ίο is switched to the state of the operation confirmation test (s82). Then, the control circuit and the integrated circuit 10 perform the above-described operation check test (S83). Further, the control circuit confirms all the operations. When the test 丨~5 is completed, the circuit is switched to the standby circuit, and the circuit is switched to the normal operation (S84). (Activity amplifier 1 operation check) The above operation confirmation test system The operational amplifier 1 is not defective. However, there is a possibility that the operational amplifier 产生 is defective. 2 In the present embodiment, it is preferable to confirm the operation of the operational amplifier 1 before performing the above-described operation confirmation test. Referring to Fig. 26, the operation confirmation of the operational amplifier 1 of 143488.doc -49-201030412 will be described. Fig. 26 is an explanatory view showing the configuration of the operational amplifier 1 and the peripheral circuit for confirming the operation of the operational amplifier 。. As shown, a switch S5 for switching between an input from the DAC circuit 8 and an input specific voltage is connected to the positive input terminal of the operational amplifier 丨. Further, the switch S3 for switching between the two specific voltages VreH and Vref2 is connected to the b side of the switch S5 (on the input side of the specific voltage). On the other hand, a switch S6 for switching between an output of the operational amplifier 1 for performing negative feedback from the operational amplifier 与 and an input specific voltage is connected to the negative input terminal of the operational amplifier i. Further, a switch 84 for switching between the two specific voltages Vref1 and Vref2 is connected to the 8 side of the switch 84 (on the input side of the specific voltage). Next, the general operation of the operational amplifier 1 will be described. In the normal operation of the arithmetic amplifier 1, the switch S5 is placed on the A side (the output side of the DAC circuit 8), and the switch S6 is placed on the A side, whereby the operational amplifier 1 operates as a circuit of the voltage follower. Next, the procedure for confirming the operation of the operational amplifier 1 will be described below. First, switch switches S1 and S2 to the B side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 operates as a comparator. Then, switches S3 and S4 are switched to the A side. Thereby, the positive input terminal of the operational amplifier 1 is input with Vref 1, and the negative input terminal is input with Vref2. Here, Vref1 and Vref2 are pre-generated voltages, and the voltage value of Vref1 is greater than the voltage value of Vref2. Furthermore, the difference between the voltage values of Vref1 and Vref2 is a larger value than the input/output bias of 143488.doc -50-201030412 of the operational amplifier 1. At this time, compared with the Vref2 of the polarity input terminal of the $ ig., ^ λ 5 , and the polarity input terminal, the % input to the positive polarity input terminal is larger than the south of the operational amplifier 1 output "Η" level. ^^. The decision circuit 3 detects that: Γ After the output is large, it is compared with the expected value "H" memorized by itself. Here, when the output of the operational amplifier ! is "L" level, the determination circuit 3 can determine that the operational amplifier 1 is not at 1. Furthermore, the expected value memorized by the circuit 3 is provided from the control circuit. The second step is also considered to be a case where the comparator operation of the operational amplifier 1 is defective, and the second can only output the "H" level. Therefore, the switch S4 is switched to the B side, and _ is input to the operational amplifier to input Vref1 to the negative polarity input terminal. At this time, the disk output: compared to Vref2 of the positive polarity input terminal, the voltage value of Μ1 input to the negative polarity input terminal is higher, so the operational amplifier! The "L" level is output. The decision circuit 3 detects from the operational amplifier! After the output, the expected value "L" memorized by the disc is compared. Here, the operation is amplified to brew < When the output is at the "H" level, the determination circuit 3 can determine that the calculation is defective. Further, the open relationship is cut by the control circuit. [Embodiment 2] Next, the second embodiment of the present invention will be described later with reference to Figs. 27 to 33, and the description of the second embodiment will be carried out only. The description of the form 1 is different, and the description of the place where it is repeated is omitted. First, the differences between the first embodiment and the second embodiment will be briefly described. In the first embodiment, the output of the DAC circuit 8 is compared with the output of the DAC circuit 28 of the preliminary 143488.doc 51·201030412 in the operational amplification Si. On the other hand, in the second embodiment, the two DAC circuits 8 adjacent to each other are grouped, and the outputs from the DAC circuits 8 from each other are compared in an operational amplifier. (Configuration of Display Driving Semiconductor Integrated Circuit 2) The configuration of the display driving semiconductor integrated circuit (hereinafter referred to as integrated circuit) 20 of the present invention will be described with reference to Fig. 27 . Fig. 27 is an explanatory view showing the configuration of the integrated circuit 20 (integrated circuit for driving the display device). The operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to its own positive input terminal. Further, the operational amplifier 丨 is input from the output of the DAC circuit 8 connected in series to the operational amplifier adjacent thereto to its own negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8_丨 to its own positive input terminal, and inputs the output from the DAC circuit 8_2 to its own negative polarity via the switch 2a. Input terminal. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8_2 to its own positive input terminal, and the output from the DAC circuit 8-1 is input to its own negative input terminal via the switch 2a. Further, the integrated circuit 2A includes the preliminary sampling circuits 26 and 268, the preliminary holding circuits 27 and 278, the preliminary 1), the circuits 28A and 28B, the operational amplifiers 2ia and 21B, and the pull-up and pull-down circuits. 25A and 25B. In the operational amplifier 21A, the output from the DAC circuit 28a is also input to its own positive input terminal, and the output from the DAc circuit 28B is input to its own negative input terminal via the switch 2a. Further, in the operational amplifier 21B, the wheel from the DAC circuit 28B is also input to its own positive input terminal, and the output 143488.doc -52· 201030412 from the DAC circuit 28a is input to its own negative input via the switch 2a. Terminal. (General operation of the integrated circuit 20) In the normal operation of the integrated circuit 20, the control circuit sets the test signal to the "L" level and the (4) word to the "H" level, as in the embodiment i. Thereby, the DAC circuit 8 converts the gray scale data input from the hold circuit 7 into a gray scale voltage signal and outputs it as a gray scale voltage to the operational amplifier positive polarity input terminal. Here, since the switch hole is 〇1^, the operational amplifier i ❹ = output becomes negative feedback to its own negative input terminal. Thereby, the operational amplifier 1 operates as a voltage follower. Thereby, the operational amplifier 1 will sound from the prison electric ash (10) = each of the output terminals OUT1 to OUTn. (Switching of Operation Confirmation Test) In the switching of the operation confirmation test of the integrated circuit 20, the control circuit sets the testk number to the "Η" level, and makes the word "[" level. First, since the switch 2a is 0, the TSTR1 signal is input to the sampling circuit 26α and the odd-numbered sampling circuit 6 (the sampling circuits 6-1, 6_3, ..., 6_(η_υ). Further, the TSTR2 signal is input to the sampling circuit. 26Β and the even number of sampling circuits 6 (sampling circuits 6-2, 6-3, ..., 6-small and further, because the switch 2& is the input to the negative input terminal of the odd-numbered operational amplifiers 邻接The output from the even number of DAC circuits 8 inputs the output from the adjacent odd-numbered octaves of the even-numbered input terminals of the even-numbered operational amplifiers 1. The output of the circuit 8 is again, because the test Β signal is at the "L" level. Therefore, the switch u is a traitor. By this, the output of the operational amplifier! itself is blocked by the negative feedback of the negative terminal. As a result, the operational amplifier 丨 becomes connected from the string 143488.doc •53- 201030412 A comparator that compares the output of the DAC circuit 8 itself with the output from the adjacent dac circuit 8. (Operation confirmation test of the second embodiment) Next, the first sequence of the operation confirmation test of the second embodiment will be described below with reference to FIG. Carry out Fig. 28 is a flow chart showing the first sequence of the operation confirmation test in the second embodiment. First, the control circuit sets the test signal to the "H" level so that the "Μ B signal becomes the "L" level (S101). Thus, the operational amplifier i operates as a comparator (S102). Then, the control circuit sets the expected values of the odd-numbered determination circuits 3 (decision circuits 3_1, 3-3, ..., 3-(n·!)) to The "L" level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuits 3 (decision circuits 3-2, 3·4, ..., 3_n) to the "H" level. Then, the control circuit The counter melon included in the self is initialized to 〇 (S103). Further, after the control circuit makes TSTR1 valid, the sampling circuit 26a and the odd-numbered sampling circuits 6 input gray scale data of the gray scale m via the data bus. After the circuit makes TSTR2 valid, the sampling circuit 26B and the even-numbered sampling circuit 6 input gray scale data of gray scale m + 经由 via the data bus (S104). Here, if the value of the counter m is considered to be 〇, then The odd-numbered operational amplifiers 1 will be grayscale voltages of grayscale 0, from the string The odd-numbered DAC circuits 8 connected to themselves are input to their own positive polarity input terminals. Further, the odd-numbered operational amplifiers 1 input the gray scale voltage of the gray scale 1 from the adjacent even number of DAC circuits 8 to the negative pole of itself. The input terminal is the same. If the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd operational amplifier 1 is 143488.doc -54 - 201030412. The even-numbered operational amplifiers 1 input the gray scale voltage of the gray scale 1 from the even-numbered DAC circuits 8 connected in series to their own positive polarity input terminals. Further, the even-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale , from the adjacent odd-numbered DAC circuits 8 to its own negative polarity input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 is "H". Then, the decision circuit 3 determines whether or not the level of the output signal from the operational amplifier is coincident with the expected value memorized by itself (s1 to 5). Here, when the output from the operational amplification W is different from the expected value, the determination circuit 3 outputs the "H" flag to the determination flag 4 (S1()6). The value of the counter melon is incremented and the above processing of S1 04 to S 106 is repeated until the value of the counter m becomes nj (sl 〇 7, sl 〇 8). (Operation check test 2 of the second embodiment) "The second step of the operation green test of the second embodiment will be described with reference to Fig. 29. Fig. 29 shows the second sequence of the operation check test of the second embodiment. The operation confirmation test 2 in the second embodiment confirms the operation of inverting the voltage relationship between the odd number and the even number of gray levels in the operation W k 1 in the second embodiment, and The operation confirmation test in the second embodiment is the same as the operation confirmation test in the second embodiment. The "H & system circuit sets the expected value of the odd-numbered determination circuit 3 to "other, sets the expected value of the even-numbered determination circuit 3 to be" and further controls The circuit initializes the counter m contained therein 143488.doc -55- 201030412 to 0 (S111). Then, after the control circuit makes TSTR1 valid, the sampling circuit 26A and the odd-numbered sampling circuit 6 input the gray scale m via the data bus. +1 grayscale data. Moreover, after the control circuit makes TSTR2 valid, the sampling circuit 26B and the even-numbered sampling circuits 6 input gray scale data of the gray scale m via the data bus (S112). If the value of the counter m is considered to be 〇, Then, the odd-numbered operational amplifiers 1 input the gray scale voltage ' of the gray scale 1 from the odd-numbered DAC circuits 8 connected in series to their own positive polarity input terminals. Further, the odd-numbered operational amplifiers 1 rotate the gray scale voltage of the gray scale , from the adjacent even number of DAC circuits 8 to their own negative polarity input terminals. Here, if the DAC circuit 8 connected to the two input terminals of the implement A1 is normal, the output of the odd-numbered operational amplifiers 1 is "ΓΗ". On the other hand, the even-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale 0 from the even-numbered DAC circuits 8 connected in series to its own positive polarity input terminal. Further, the even-numbered differential amplifier 1 inputs the gray scale voltage of the gray scale 1 from the adjacent odd-numbered DAC circuits 8 to its own negative polarity input terminal. When the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 为 is at the "L" level. Next, the decision circuit 3 compares the level of the output from the operational amplifier 与 with the expected value recalled by itself (S113). Here, when the output from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs the "H" flag to the determination flag [increases the value of the count h by _ and repeats the above S112 to S114. Processing until the counter value becomes ni 143488.doc 201030412 (SI 15, SI 16). (Operation Confirmation Test 3 of the Second Embodiment) Next, the procedure of the operation confirmation test of the second embodiment will be described below with reference to Fig. 30. Fig. 30 is a flow chart showing the third procedure of the operation confirmation test in the second embodiment. As described in the operation confirmation test 3 of the first embodiment, there is a case where the output of the DAC circuit 8 is defective in the open circuit. The transmission amplifier 1 continues to be maintained by the verification test that has been performed. The gray scale voltage input to the operational amplifier 1 is confirmed in the operation confirmation tests 1 and 2 of the second embodiment. First, similarly to the operation confirmation tests 1 to 2, the control circuit initializes the value of the counter m included in itself to 〇 (s21). Further, in the integrated circuit 2, the pull-up and pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8. Here, the control circuit controls the pull-up and pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier ( (S122). In the case where the output of the odd-numbered DAC circuits 8 is open, a higher voltage is input to the positive input terminals of the odd-numbered nasal amplifiers 1. On the other hand, the control circuit controls the pull-up and pull-down circuits 5 to pull down the positive polarity input terminals of the even-numbered operational amplifiers 1 (S122). As a result, when the output terminals of the even-numbered DAC circuits 8 are opened, a lower voltage is input to the positive input terminals of the even-numbered operational amplifiers 1. The subsequent processing of S123 to S127 is the same as the operation checking test 1 of the second embodiment, and thus the description thereof will be omitted. 143488.doc • 57· 201030412 (Operation confirmation test 4 of the second embodiment) Next, a fourth procedure of the operation confirmation test of the second embodiment will be described below with reference to Fig. 3A. Fig. 31 is a flow chart showing the fourth sequence of the operation confirmation test in the second embodiment. The purpose here is to detect the same defect as the above-described action confirmation test 3. First, in the same manner as the operation confirmation test up to this point, the control circuit initializes the value of the counter m included in itself to 〇(s丨3丨). The control circuit then controls the pull-up and pull-down circuits 5 to pull down the positive input terminals of the odd-numbered operational amplifiers 1 (S122). As a result, when the output terminals of the odd-numbered DAC circuits 8 are opened, a lower voltage is input to the positive input terminals of the odd-numbered operational amplifiers 1. The other side control circuit controls the pull-up and pull-down circuits 5 in such a manner as to pull up the positive input terminals of the even-numbered operational amplifiers (S 122). As a result, when the output terminals of the even-numbered DAC circuits 8 are opened, a higher voltage is input to the positive input terminals of the even-numbered operational amplifiers 1. The subsequent processing of S133 to S137 is the same as the operation checking test 2 of the second embodiment, and thus the description thereof will be omitted. (Operation check test 5 of the second embodiment) Next, the fifth sequence of the operation check test of the second embodiment will be described below with reference to Fig. 32. Fig. 32 is a flow chart showing the fifth sequence of the operation confirmation test in the second embodiment. As described in the operation check test 5 of the first embodiment, the DAC circuit 8 has a defect in which two gray-scale short circuits adjacent to each other are generated. The purpose of the operation confirmation test 5 of the second embodiment is to detect such a failure of 143488.doc -58· 201030412. As shown in the figure, first, the control circuit initializes the value of the counter m included in itself to 0 (S141). Next, TSTR1 and TSTR2 are enabled, and the gray scale data of the gray scale m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 via the data bus. Further, by making the data LOAD signal valid, the odd-numbered DAC circuit 8 and the even-numbered DAc circuit 8 output the gray scale voltage of the same gray level „! (S142). Then, the control circuit is φ by a switch not shown. The short-circuit input terminal of the operational amplifier 1 is short-circuited with the negative input terminal, and the positive input terminal and the negative input of the operational amplifier 丨 are short-circuited by short-circuiting the positive input terminal and the negative input terminal of the operational amplifier. The same gray scale voltage is input to the terminal. Next, the determination circuit 3 stores the level of the output of the operational amplifier when the positive polarity input terminal of the operational amplifier is short-circuited with the negative polarity input terminal as an expected value (S143). The switch (not shown) is turned off, and the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1 is released. At this time, the input to the positive input terminal of the odd operational amplifier 1 is connected in series from itself. The gray scale voltage of the gray scale m of the odd number of DAC circuits 8 is input to the input terminal of the negative input terminal from the adjacent The gray scale voltage of the gray scale m of the plurality of circuits 8. On the other hand, for the positive input terminal of the even-numbered operational amplifiers, the gray scale of the gray scale m from the even-numbered DAC circuits 8 connected in series is input. The voltage 'inputs the gray-scale voltage from the gray scale m of the odd-numbered DAC circuits 8 adjacent to itself to the negative polarity input terminal. Here, the decision circuit 3 compares the expected value stored by itself with the operation amplification 143488.doc -59 - 201030412 The output of the device 1 is compared (S 144). Further, when the output from the operational amplifier is different from the expected value stored by itself, the decision circuit 3 outputs the "H" flag to the determination flag 4^ The determination flag 4 memorizes the "H" flag input from the decision circuit 3 inside itself. Then, the control circuit exchanges a signal from the DA (the input of the circuit 8 to the positive polarity input terminal of the operational amplifier 、 and the signal input to the negative polarity input terminal using a switch (not shown) (S146). The same processing as that of S147 (S147). Similarly, in the case where the output from the operational amplifier 1 is different from the expected value stored by itself, the determination circuit 3 outputs "H" to the determination flag 4 (in the same manner as the SM5). S148) The value of the counter m is increased, and the above processing of si42 to si48 is repeated until the value of the counter m becomes 11 (S149, si5〇). (Self-repair of the second embodiment), and subsequently, referring to FIG. 33 In the case where there is a "h" in the judgment flag 4, the correction is performed in the case where the determination circuit 3 determines that the DAC circuit 8 is in the presence or absence of the DAC circuit 8. 33 shows the switching between Dac 28A and 28B which are determined to be defective. The flow of the sequence in which the circuit 8 and the prepared DAC circuit perform self-repair First, whether the control circuit remembers the flag 4 "H" is detected (s! 51). When the control circuit detects that the judgment flag (5) does not memorize the n-shape, it moves to the processing of Sl53. The other __ ^ - aspect 'the control circuit detects that the memory has "H" When the flag 4 is formed, the DAC circuit 8 corresponding to the flag 4 having the "Η" is switched to the preliminary DAC circuit 28A or 143488.doc 201030412 28B. Here, Embodiment 2 In the middle, since the two dac circuits 8 are operated as a group, even if it is determined that the flag 4 has the "h" flag, it is impossible to determine which of the DAC circuits in the group is defective. The group of dac circuits 8, in other words, the odd-numbered and even-numbered two dac circuits 8 are switched to the preliminary DAC circuits 28A and 28B (S152) corresponding to the determination flag 4 in which "H" is stored. Specifically, the following description will be made on the case where the DAC circuit 8-1 has a defect. Here, when the DAC circuit 8_丨 is defective, the operation confirmation test 5 is performed, and the determination circuits 3] and 3_2 are both " H" is output to the decision flags 4 1 and 4-2. Further, the judgment flags 4_ 1 and 4-2 will be self-determined. The "Η" flag of the input of the lanes 3-1 and 3-2 is output to the switch 2 (; and 2d, and the switch & is turned OFF to turn the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 仏 'sample circuit 26B inputs the STR2 signal. Thereby, the sampling circuit 26A obtains the gray scale data corresponding to the liquid crystal driving signal output terminal OUT1 from the data bus. The sampling circuit 26B is obtained from the data bus and the liquid crystal driving signal output terminal OUT2. Corresponding gray scale data. Further, since the switch 2c is turned off, the output terminal of the operational amplifier 1_1 and the liquid crystal driving signal output terminal OUT1 are disconnected, and the output terminal of the operational amplifier ι_2 is disconnected from the liquid crystal driving signal output terminal OUT2. Further, since the switch 2d is turned on, the output terminal of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output terminal of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2. As described above, the defective DAC circuit 8 and its paired DAC circuit 8 are switched as a set of DAC circuits 28 A and 28B as a group, whereby 143488.doc -61 · 201030412 can have a defective DAC circuit. 8 is switched to the preparatory DAC circuit 26A or 26B, and then the 'control circuit sets the test signal to "L", and the test b signal is "H", and then moves to the normal operation (S153). [Embodiment 3] In the embodiment described above and in the second embodiment, the gray scale voltage from the output circuit block 30 (see Fig. 2) and the gray scale from the preliminary output circuit block 4 (see Fig. 2) The switching circuit 6A (see FIG. 2) for switching between voltages is a configuration included in the integrated circuits 1A and 2B. However, the present invention is not limited thereto. The switching circuit 60 may be included in the display panel. The composition of the side. Hereinafter, the display unit 9A of the switching circuit 60 will be included on the display panel side, and the configuration and operation will be described as a third embodiment of the present invention. In the present embodiment, the differences from the first embodiment will be described, and the description of the overlapping portions will be omitted. (Schematic Configuration of Display Unit 90') First, a schematic configuration of the display unit 9A' of the present embodiment will be described with reference to Fig. 34. Fig. 34 is a block diagram showing a schematic configuration of the display unit 90. As shown in Fig. 34, the display unit 90' includes a display panel 8A, and an integrated circuit 1A (drive circuit) for driving the display panel 8'' based on grayscale data input from the outside. Here, the integrated circuit 1 is different from the integrated circuit 1 according to the first embodiment in that the switching circuit 6 is not included, and the other configuration is the same as that of the integrated circuit 10. Further, the display panel 80 differs from the display panel 80 of the embodiment J in that it includes the switching circuit 60, and the other configuration is the same as that of the display panel 80. 143488.doc -62- 201030412 (Configuration of display unit 90') Next, a more detailed configuration of the display unit 90 of the present embodiment will be described with reference to Fig. 35. Fig. 35 is a block diagram showing the configuration of the integrated circuit 10. As shown in FIG. 35, the integrated circuit 1A includes: n sampling circuits 6 which are input from the gray-scale data input terminals (not shown) via the data bus and corresponding to the respective n output terminals OUT1 to OUTn. Gray scale data; n holding circuits 7; DAC circuit 8' which converts gray scale data into gray scale voltage signals; operational amplifier 1 which has a buffer circuit function for gray scale voltage signals from DAC circuit 8; Decision circuit 3; and n pull-up and pull-down circuits 5 ° Further, as shown in FIG. 35, the integrated circuit 10 includes a plurality of switches 2a that switch between ON and OFF according to the test signal; A plurality of switches 2b for switching signals between ON and OFF; and a plurality of switches 2f for switching between (10) and 〇FF according to the LF (L〇w Frequency) signal. Further, the switches 2a, 2b, and 2f are 〇> when the "H" signal is input, and are OFF when the "L" signal is input. Further, the integrated circuit 1A includes one of the following circuits: a prepared sampling circuit 26, a preliminary holding circuit 27, a prepared DAC circuit 28, a preliminary operational amplifier 21, and a preliminary output terminal 〇υτ〇. On the other hand, as shown in FIG. 35, the display panel 8A includes: connection terminals (not shown) connected to the output terminals OUT1 to 〇UTn included in the integrated circuit ίο'; determination flag 9_丨～9_η (hereinafter, referred to as the judgment flag 9 in the case of the general term); the switch 2f is performed between ON and OFF according to the iLF signal from the control circuit (not shown); 143488.doc •63- 201030412 is the LFB (Low Frequency Band) signal and switches 2e to switch between qff; and ON and OFF according to the output signal from decision flag 9 that is Flag 1~Flagn Switch between & and 2d. Further, the switches μ, 2e, and 2f are turned ON when the "Η" signal is input, and turned OFF when the "L" signal is input. Further, the switch 2c is turned OFF when the "Lj signal is turned ON" and the input γη signal is input. Further, the display panel 80 in the present embodiment is a liquid crystal display panel, as shown in FIG. 35, 'data signal line; 5L-1 to SL-n (hereinafter, referred to as a data signal line SL in the case of a general term) via a switch 2e and 2c are connected to the respective output terminals OUT of the integrated circuit 1A. Further, the pixels P having the same number as the number of scanning signal lines GL are connected to the respective data signal lines SL. Further, in Fig. 35, the pixel P connected to the data signal line SL-1 is referred to as a pixel Pd, and the pixel P connected to the data signal line SL-n is referred to as a pixel p_n. (Self-repairing of the third embodiment) Next, the self-repairing operation in the case where the operation flag confirmation test is performed on the display unit 90 of the present embodiment is a case where the determination flag 4 stores the "H" flag. Further, the operation confirmation test method in the present embodiment is the same as the operation confirmation test ～5 described in the first embodiment, and thus the description of the operation confirmation test is omitted here. First, at the time point when the operation confirmation test 丨~5 ends, the signal is "H"' and the test B signal becomes "L". Therefore, the connection between the operational amplifier 1 and the output terminal 〇UT is turned off by turning on (4). Here, after the operation confirmation tests 1 to 5 are completed, the control circuit outputs a signal of "H", and 143488.doc • 64 · 201030412 1 out of the coffee signal of L". By outputting the LF signal of "Η", the switch becomes 0N. Each of the determination flags 4 is connected to each of the output terminals OUT, and the flag 9 is determined. Further, each of the determination flags 4 outputs the ', D, or J flag stored in itself as Fiagl to Fiagn, and outputs it to each of the determination flags 9 via the respective output terminals OUT. Each judgment flag 9 memorizes F(4)~Flagn outputted from the judgment flag 4 in its own internal memory, and outputs it to the switch 2c and 2 ί^ connected to its own body, and the LF signal is ΓΗ" d door The LFB number becomes "L", so each switch & is 〇FF. Therefore, it is prevented that the Hagl~Flagn outputted by the determination flag 4 is output to the data for =L wide, and as a result, it is determined that the (10) to one outputted by the flag 4 affects the pixel P. Hereinafter, a detailed description of the self-repairing operation in the display unit 90 will be described by taking a case where the determination flag W corresponding to the output terminal 〇UT1 is stored as a standard. 「 "Firstly" in the case where the judgment flag corresponding to the output terminal 〇UT1 is stored in the case of "Η" flag, in other words, the dac circuit 8] is bad, and the flag is determined in the flag 9·1. The output has an "H" flag, and the output "H" flag is recorded in the internal memory included in itself. Furthermore, in this example, the decision flags 4_2 to 4_n are recorded with a % flag. Then, the decision flag 9] outputs the "H" flag to the connection: on its own switches 2C and 2d. Thereby, the switch 2 connected to the determination flag (4) cuts off the connection between the output terminal OUT1 and the data signal line SL-1, and further connects the flag 9々„2d to connect the output terminal (10)q to the data signal line. Each of the determination flag pairs is connected to the switches 2C and 2d of the 143488.doc •65·201030412 and outputs Flags 2 to Flagn of the "L" flag, so the switch 2c connected to the determination flags 9-2 to 9-n becomes ON. The switch 2d connected to the determination flags 9_ 2 to 9-n becomes 0FF. As a result, the respective data signal lines sl_ 2 to SL-n are connected to the respective output terminals OUT2 to 〇υΤη via the switch 2e. Each of the determination flags 9 switches between the switches 2c and 2d connected to itself based on Flag 1 to Flagn from the determination flag 4, and then the control circuit outputs the LF signal of "1" and outputs the FB signal of ΓΗ". Thereby, the respective output terminals OUT2 to OUTn are connected to the respective data signal lines SL-2 to SL-n. Then, after the control circuit outputs the LF signal of "L", the test signal of "[" and the test B signal of "H" are output, whereby the data signal line SL_i is connected to the output terminal of the operational amplifier 21 via the output terminal OUTO, and On the one hand, the respective data signal lines SL-2 to SL-n are connected to the operational amplifiers 1-2 to 1-n via the output terminals 〇υτ2 to OUTn, and the switches 2d connected to the sampling circuit are based on the determination flag 4_1. The pqagi becomes on, so the gray scale data (the gray scale data corresponding to the data signal line SL_丨) input to the sampling circuit 6-1 is also input to the sampling circuit 26. As a result, the gray scale data corresponding to the data signal line SL-1 is output from the output terminal 〇uT〇, instead of being input to the data signal line sl-1 from the output terminal OUT1, and is input to the sampling circuit 6 and each of the prepared samples. The switching of the gray scale data of the circuit 26 is the same as that in the first embodiment, and thus detailed description thereof will be omitted herein. As described above, the display unit 90· performs the self-repairing operation, whereby the normal DAC circuit 28 can be used instead of the Dac circuit 8 detected as defective, and the normal gray scale voltage can be output to the data signal line SL. Further, similarly to the embodiment i, the present embodiment also includes the sampling circuit 26 and the holding circuit 27 which are prepared in advance with respect to the DAC circuit 28 which is prepared by the DAC 488. doc • 66 - 201030412. Therefore, it is possible to switch to the preliminary sampling circuit 26 and the holding circuit 28 not only in the case of the circuit 8' but also in the case where the sampling circuit 6 or the holding circuit 7 is defective. Next, a procedure from the power-on of the display unit 90 to the operation confirmation test and then the transition to the normal operation will be described with reference to Fig. 36. Fig. 36 is a flow chart showing the processing procedure from the time when the power is turned on from the display unit 9A to the confirmation of the operation and the movement of the tears to the normal operation. First, the display unit 90' detects that the integrated circuit 10 is initialized after the user turns on the power, so that all the flags memorized by the determination flag 4 become the "L" flag (s 161). . Then, the control circuit sets the signal to "「", and after the test signal is "L", the integrated circuit 1 is switched to the state of the operation confirmation test (S162). Next, the control circuit and the integrated circuit 1 perform the above-described operation confirmation test (S163). Further, the control circuit confirms whether or not all the operation check tests have been completed (s丨64). ^ If the control circuit detects that not all of the operation check tests 1 to $ are bundled in the S 1 64, the display unit 90 According to an instruction from the control circuit, the process is moved to S163, and an unfinished operation confirmation test is performed. On the other hand, if "the display unit 9" is confirmed by the middle control circuit, and all the operation confirmation tests have been completed, the "H" 2LF signal and the LFB signal of "L" are outputted to detect the good circuit (sampling circuit 6). In the case of the holding circuit 7, the DAC circuit 9, and the operational amplifier 1), the defective circuit is switched to the preparatory circuit (the sampling circuit 26, the holding circuit 27, the DAC circuit 29, and the operational amplifier 21), and then moved to the general operation (S165). ). In addition, the display unit 90 in the present embodiment includes the determination flag* and the determination flag 9 as the circuit of the flag determination result of the memory determination 143488.doc-67-201030412. However, as a modification of the display unit 90, the configuration may be such that the flag flag 9, the switch 2f, and the switch 2e are not included, and the flag 4 is controlled to control the switches 2c and 2d. At this time, it is not necessary to control the switches 2 [and 26 signals and the lfb signal]. On the other hand, the wiring and the connection terminals for connecting the determination flag 4 to the switches and 2d are required. [Embodiment 4] In the first to third embodiments described above, the integrated circuit and the display panel are connected via the output terminal 〇υτ, but the integrated circuit and the display panel are integrated without being output via the output terminal OUT. The device is also included in the mouthpiece of the present invention. In the following, the display unit 90" in which the integrated circuit and the display panel are integrated will be described as a fourth embodiment with reference to Fig. 37. Further, the display portion 90" of the present embodiment is a deformation of the display portion 9 of the first embodiment. In the present embodiment, the differences from the first embodiment will be described, and the description of the overlapping portions will be omitted. (Configuration of Display Unit 90" First, the configuration of the display unit 90' of the present embodiment will be described with reference to Fig. 37. Fig. 37 is a block diagram showing the configuration of the display unit 90" as shown in Fig. 37, the display unit 90" The integrated circuit 10 and the display panel 80 shown in the first embodiment are not different, and the output terminal of the operational amplifier is directly connected to the data signal line sl via the switches 2b, 2c, and 2d. That is, the display unit 90" The difference between the middle portion and the display portion 9A of the first embodiment is whether or not the output terminal OUT is included. The other configuration is the same as that of the display unit 90 of the first embodiment of 143488.doc-68-201030412. Further, in the present embodiment, As a modification of the first embodiment, it is needless to say that in the second and third embodiments, the integrated circuit and the display panel are not included, and the display device integrated by the output terminal OUT is also included in the display device. Within the scope of the present invention (television system) Next, a television system 300 including the display unit 9 of the first embodiment will be described with reference to Fig. 38. Fig. 38 shows the structure of the television system 300. In the following, the television system 300 will be described as the display unit 90 according to the first embodiment. However, the television system of the present invention is not limited thereto, and may be replaced by the display device including the second to fourth embodiments. The configuration of the display unit 90. (Configuration of the television system 300) As shown in Fig. 38, the television system 3A includes an antenna 3〇1 that receives a broadcast wave, and a tuner unit 302 that demodulates the received broadcast wave. And a signal separation unit 303, which separates the demodulated video and audio signals into a shirt image and a sound signal; and a video signal processing unit 3〇4 that decodes the separated video signal into a digital image signal; The display unit 9A obtains the decoded digital image signal as grayscale data, and displays the image on the display panel 80 (refer to FIG. 2) according to the acquired grayscale data; the sound signal processing unit 3〇5 The separated sound k number is decoded into a digital sound signal; and the sound k number output unit 306 converts the decoded digital sound signal into an analog sound signal, and converts the analog sound signal as a sound Sound output. 143488.doc •69- 201030412 (Operation of TV system 300) The operation of the television system 300 will be described. First, the antenna 301 receives the broadcast wave from the broadcast station and receives it. The broadcast wave is output to the tuner unit 302. The spectrometer unit demodulates the output broadcast wave into a video/audio signal and transmits the signal separation unit 3()3. The money separating unit separates the output video signal into The video (4) and the audio signal are output to the video signal processing unit 3〇4 and the audio signal processing unit 3〇5. The video signal processing unit 304 decodes the output video signal into a digital video signal, and decodes the decoded digital image. The signal is output to the display unit 90 as gray scale data. The display unit 9 displays the output gray scale data using the display panel (10) included in itself. On the other hand, the sound signal processing unit 3〇5 decodes the sound signal separated by the signal separating unit 303 into a digital sound signal and outputs it to the sound output unit 306. The audio signal output unit 3〇6 converts the output digital audio signal into an analog sound signal, and then outputs the analog sound signal as a sound using the speaker included in the audio signal. Furthermore, the television system 3 of the present invention is configured to acquire an audiovisual signal from a broadcasting station using the antenna 3〇1 and the tuner unit 302 as a mechanism for acquiring video and audio signals. However, the present invention is not limited thereto. A content reading device such as a DVD player that reads content data recorded on the recording medium from a recording medium, or a device that acquires data from an Internet or the like via a PC (personal computer). The operation confirmation test and the self-repair processing operation described in the first embodiment and the fourth embodiment are configured to perform the operation immediately after the liquid crystal driving semiconductor integrated circuit 丨〇 is turned on, but the present invention is not limited thereto. Also, 143488.doc -70-201030412 can be configured to perform the above operation by inputting a control signal to the liquid crystal driving vehicle 1 Λ 体积 volume body circuit 10, and can perform the above operation at any time. . For example, the controller of the display device can input a signal during the return period of the watch and the member to the liquid crystal driving semiconductor integrated body, and perform the operation confirmation test and self. repair. ‘

又’動作確認測試及自我修復之處理動作亦可於如 間點上進行，即液晶驅動用半導體積體電路10中構成有偵 測液晶驅動用半導體積體電路10之異常之 兒俗，於液晶驅 動用半導體積體電路10中產生異常時進行該動作。例如亦 可對自液晶驅動用半導體積體電路10輸出之信號之電流進 行偵測，並於偵測出之電流多於設定電流之情形時進行 動作確認測試及自我修復之處理動作。 又，動作確認測試及自我修復之處理動作亦可定期進 行。例如亦可於不進行顯示之每個垂直返馳期間進行該動 作，或者於預先設定之每個累計顯示時間進行該動作。 又，動作確認測試及自我修復之處理動作亦可於進行顯 示之期間之一部分中進行。例如因液晶顯示裝置中像素記 憶顯示電a，故於顯示電壓之充電結束後，即便使液晶驅 動用半導體積體電路1G之輸出成為高阻抗，顯示仍不存在 問題。於顯示期，使液晶驅動用半導體積體 電路10之輸出成為高阻抗’而進行動作確認測試及自我修 復之處理動作。此時，若無進行所有動作確認測試模式之 時間’則亦可於1條線之顯示期間之一部分中進行例如— 種模式之判定’且亦可於—個晝面之顯示㈣或顯示數個 143488.doc 71- 201030412 畫面之期間進行。 陷進行自G(參照圖18)為了對自身之缺 我檢測（動料認賴），必需 板8。(參照圖2)之輸出信號停止。即，積體電路不面 我檢測之時間==顯:此’龍電路10進行* 響的期間進行。會對^置之影像之顯示產生影 因此’本發明之實施形態中’作為積體電路Μ進行自我 檢測之期間，對積體電路蹄顯示裝置之電源接通時 動過程中進行自我檢測及自我修復之示例進行說明。其原 因在於.若於顯示裝置之啟動過程中，則因顯示裝置不進 订影像之顯心故㈣電W何料會對心裝置之影像 之顯不產生影響的狀態下進行自我檢測及自我修復。 如上所述’本實施形態中之積體電路1()於顯示裝置之電 源接通時之啟㈣程巾進行檢測自身缺陷之自我檢測，但 本發明並不限於此，可於除顯示裝置之啟動過程中以外之 期間進行自我檢測及自我修復。 以下，將除顯示裝置之啟動過程中以外之可進行自我檢 測及自我修復之期間作為實施例進行說明。 [實施例1] (於垂直返馳期間之自我檢測及自我修復） 首先’作為第-實施例，於顯示裝置之垂直返驰期間 中，積體電路10可於不會對顯示裝置之影像顯示產生影響 之狀態下進行自我檢測及自我修復。以下說明其理由。 143488.doc -72· 201030412 以下，參照圖39(a)〜圖39(f)對輸入至顯示裝置之各信號 之時序進行說明。圖39(a)〜圖39(〇係表示輸入至液晶顯示 裝置之各信號之時序之時序圖。 圖39(a)表示自驅動顯示裝置之掃描線之掃描側驅動電路 輸出之、提供給顯示裝置之第一根掃描信號線之掃描信號 SCN1 ’該圖（b)表示自掃描側驅動電路輸出之、提供給顯 不裝置之第二根掃描信號線之掃描信號SCN2，該圖表 φ 示自積體電路10(參照圖18)提供給影像信號反轉電路之、 與顯示裝置之第j根資料信號線相對應之影像信號DSj，該 圖（d)表示自影像信號反轉電路提供給資料侧驅動電路之、 與顯示裝置之第j根資料信號線相對應之影像信號DRVj， 該圖（e)表示提供給顯示裝置之第』根資料信號線之影像信 號DATAj，該圖⑴表示對連接於顯示裝置中之第一根掃描 L號線與第j根資料信號線之像素所施加之驅動電壓 VDlj。又，圖39所示之時刻tl〜t5之期間τν為顯示裝置之 • 垂直掃描期間，期間TV1為垂直返驰期間，時刻tl〜t3之期 間TH為水平掃描期間，時刻t2〜t3之期間TH1為水平返驰期 間。再者’上述影像信號反轉電路為如下電路：於每個水 ，平掃描期間TH及垂直掃描期間TV使來自積體電路1〇之影 像信號DSj之極性反轉，以使顯示裝置之各像素中之顯示 電極之極性反轉。 如圖39(a)及（b)所示’掃描侧驅動電路係自第一根掃描 信號線起依序使時序延遲水平掃描期間TH，而對顯示裝 置之各掃描信號線輸出掃描信號SCN1、掃描信號 143488.doc •73· 201030412 SCN2、…、掃描信號SCNm。又，掃描側驅動電路係於每 個垂直掃描期間TV ’對顯示裝置之各掃描信號線反覆輸 出各掃描信號SCN1〜掃描信號SCNm。再者，於此，顯示 裝置包含m根掃描信號線。 將圖39(c)所示之來自積體電路1〇之影像信號DSj輸入至 影像彳s號反轉電路。然後’影像信號反轉電路於每個水平 掃描期間TH將影像信號DSj之極性反轉，並於每個垂直掃 描期間TV將該影像信號DSj之極性反轉，而生成圖39(d)所 示之影像信號DRVj。進而’影像信號反轉電路將所生成 之影像信號DRVj輸入至資料側驅動電路。 繼而’資料侧驅動電路於每個水平掃描期間TH，對來 自影像信號反轉電路之影像信號DRVj進行取樣，並將所 取樣之信號值延遲一水平掃描期間TH後，作為圖39(e)所 示之影像信號DATAj而輸出至顯示裝置之第j根資料信號 線。 然後，於連接於第一根掃描信號線及第j根資料信號線 之顯示裝置之像素（以下稱作像素⑴中，藉由在時刻u〜t2 之水平掃描期間ΤΗ之掃描信號SCN1，而將像素lj内 之TFT 導通’其結果經由第j根資料信號線’將在時刻tl〜t2之影 像信號DATAj之影像信號電壓作為驅動電壓vd lj而施加至 像素1 j内之顯示電極。於此，即便於時刻t2〜t5將像素〗j内 之TFT之導通斷開，對像素。之顯示電極所施加之驅動電 壓VDlj仍持續保持時刻tl〜t2之期間之電壓位準。同樣 地*’於連接於第二根掃描信號線及第j根資料信號線之顯 143488.doc 201030412 不裝置之像素（以下稱作像素2j)中，藉由在時刻t3〜t4之水 平掃描期間TH之掃描信號SCN2，而將像素巧内之TFT導 通，其結果經由第j根資料信號線，將在時刻t3〜t4之影像 L號DATAj之影像信號電壓作為驅動電壓而施加至像素 内之顯不電極。於此，亦為即便將像素内之TFT之導通 斷開，對像素2j之顯示電極所施加之驅動電壓仍持續保持 時刻t3~t4之期間之電壓位準。 鲁如上所述，即便將各像素内2TFT之導通斷開，顯示裝 置之各像素中之驅動電壓仍持續保持於TFT導通時所施加 之驅動電壓之電壓位準。藉此，掃描側驅動電路不將使各 像素之TFT導通之掃描信號SCNl〜SCNm輸出至掃描信號 線，換言之，於將各像素之TFT之導通斷開之期間即垂直 返驰期間TV1，顯示裝置無需對各像素之顯示電極施加電 壓。即，積體電路10無需輸出作為驅動電壓之根源之影像 信號DSj，而即便將積體電路1〇與顯示裝置電氣切斷，仍 φ 不會對顯示裝置之影像顯示產生影響。 因此，右為顯不裝置之垂直返驰期間，則積體電路⑺可 於不會對顯示裝置之影像顯示產生影響之狀態下進行自我 • 檢測及自我修復。 - (積體電路1 0全體之動作不良檢測） 本實施形態中之積體電路10所進行之檢測自身所包含之 輸出電路區塊之不良的自我檢測處理，係於與各資料信號 線相對應之各輸出電路區塊、且以各輸出電路區塊全體作 為對象而進行之處理。藉此，該自我檢測處理需要時間。 143488.doc -75- 201030412 由此於積體電路10所包含之各輸出電路區塊中無引起 動作不良之可能性之情形時，積趙電路聰需進行自我檢 測處理。換言之’ _電路職於各輸出電路區塊存在引 起動作不良之可能性之情形時，進行自我檢測處理即可。 於此’積體電路10包含動作判定電路，其對積體電路1〇 全體判定疋否存在動作不良之可能性只要為僅於藉由動 作判定電路判定出積體電路1G之哪—處存在動作不良之情 形時進行自我檢測處理，則可防止徒勞之自我檢測處理。 以下，參照圖40〜圖42對積體電路1〇所包含之對積體電 路10全體判定是否存在動作不良之可能性的動作判定電路 2 0 0進行說明。 首先，於㈣電路H)中產生動作不良之情料，供給至 積體電路10之電源電流與正常動作時相比，換言之與作為 製品而出廠時判定為合格品之初始階段相比變多。因此， 於供給至積體電路1 〇之電源電流之值與正常動作時相比大 了固定值以上之情形時，積體電路1〇中會產生動作不良。 因此，動作判定電路200對供給至積體電路1〇之電源電流 之值進行檢測，根據檢測出之電源電流之值而判定於積體 電路10中是否產生了動作不良。 (動作判定電路200之構成） 以下，參照圖40對動作判定電路2〇〇之構成進行說明。 圖40係表示動作判定電路2〇〇之構成之方塊圖。 如圖40所示，動作判定電路2〇〇係於對積體電路1〇供給 電源之VA201與積體電路10之間，包含電阻2〇2(檢測機構） 143488.doc •76- 201030412 及開關203。再者，電阻202與開關203以彼此成為並聯之 方式而連接。進而，動作判定電路200包含：A/D轉換器 204(檢測機構），其連接於電阻202及開關203之於積體電路 10侧之一端；開關205，其輸入來自A/D轉換器204之輸出 信號；EEPROM(Electrically Erasable and Programmable Read Only Memory，電子可擦可程式唯讀記憶體）206(正常 電流值記憶機構），其係連接於開關205之一方之輸出端子 之非揮發性記憶體；資料鎖存電路207，其連接於開關205 之另一方之輸出端子；以及比較電路208(電流值比較機 構、驅動電路判定機構），其將EEPROM 206之輸出值與來 自資料鎖存電路207之輸出值進行比較。再者，比較電路 208之輸出端子連接於積體電路10所包含之控制電路，其 將比較電路208中之比較結果輸出至該控制電路。再者， 開關203及205之切換係藉由積體電路10所包含之控制電路 而進行控制。 (動作判定電路200之概略動作） 動作判定電路200預先將與積體電路10正常動作時之電 源電流值相對應之值作為基準資料而記憶於EEPROM 206 中。於此，動作判定電路200於判定積體電路1〇中是否產 生動作不良之情形時，對與供給至積體電路之電源電流 值相對應之值進行檢測，將該檢測出之值與EEPROM 206 預先記憶之基準資料之值進行比較，於檢測出之值為固定 值以上之情形時，判定為積體電路10中產生了動作不良。 進而，動作判定電路200對積體電路10所包含之控制電路 143488.doc -77- 201030412 輸出表示積體電路ίο中產生了動作不良之信號，藉此控制 電路開始進行積體電路10之自我檢測處理及自我修復處 理。 (基準資料之生成及記憶處理） 如上所述，動作判定電路200需要預先將基準資料記憶 於自身所包含之EEPROM 206中。因此，以下參照圖41對 用於動作判定電路200將基準資料記憶於EEPROM 206中之 處理進行說明。圖41係表示動作判定電路200將基準資料 記憶於EEPROM 206中之動作處理之流程圖。 如圖41所示，於生成基準資料時，控制電路將開關203 打開而使來自VA201之電源電流於電阻202中流動（S301)。 於此，電阻202之電阻值係如積體電路1〇正常動作時之電 阻202之電壓下降成為約〇.1 V般之電阻值。再者，電阻 202之電阻值宜考慮積體電路之消耗電流後決定。 然後，A/D轉換器204將電阻202之積體電路10侧之一端 之電壓值轉換為數位值（S302)。A/D轉換器204將轉換之數 位值經由開關205而輸入至EEPROM 206。EEPROM 206將 輸入之來自A/D轉換器之數位值作為基礎資料而加以記憶 (S303)。再者，S303中之開關205係藉由控制電路以使A/D 轉換器204與EEPROM 206連接之方式進行切換。 一 繼而’ EEPROM 206記憶基礎資料後，控制電路將開關 203短路而使積體電路1〇恢復至一般動作狀態（S3〇4)。再 者’自S301至S304為止之基準資料之生成及記憶處理，係 於包含積體電路10之顯示裝置之製品出廠階段，換言之係 143488.doc -78- 201030412 於積體電路ίο藉由各種出廠檢查而判定為正常之階段進 行。 (動作判定電路200之動作不良檢測處理） 其次，以下參照圖42對動作判定電路200之檢測積體電 * 路1 0之動作不良之處理進行說明。圖42係表示動作判定電 ' 路200中之檢測積體電路10之動作不良之處理的流程圖。 如圖42所示，首先，控制電路將開關203打開而使來自 VA201之電源電流於電阻202中流動（S305)。 然後，A/D轉換器204將電阻202之於積體電路10側之一 端之電壓值轉換為數位值（S3 06)。A/D轉換器204將轉換之 數位值經由開關205而輸入至資料鎖存電路207。資料鎖存 電路207將所輸入之來自A/D轉換器之數位值作為檢測資料 而加以記憶（S307)。再者，S306中之開關205係藉由控制 電路以使A/D轉換器204與資料鎖存電路207連接之方式進 行切換。 φ 繼而，比較電路208將EEPROM 206所記憶之基準資料與 資料鎖存電路207所記憶之檢測資料讀出，並將讀出之基 準資料之值與檢測資料之值進行比較（S308)。進而，比較 - 電路208對基準資料之值與檢測資料之值之差是否為特定 . 值以上（例如以數位值示為3以上）進行檢測（S309)。於此， 於基準資料之值與檢測資料之值之差為特定值以上（例如 以數位值示為3以上）之情形時，將表示積體電路10中產生 動作不良之信號輸出至積體電路10所包含之控制電路。 於此，控制電路自比較電路208輸入表示積體電路10中 143488.doc -79- 201030412 產生了動作不良之信號後，開始進行積體電路ίο之自我檢 測（S311)。進而，於在積體電路1〇之自我檢測中積體電路 10於自身之輸出電路區塊中檢測出不良之情形時積體電 路10將不良之輸出電路區塊之輸出切換為預備之輸出電路 區塊之輸出而進行自我修復。再者，於在S311之積體電路 1 〇之自我檢測中無法檢測出輸出電路區塊之不良之情形 時’考慮因其他因素所引起之電源電流值之變動。因此， 此時’由於電源電流值產生變動，故動作判定電路200生 成S301〜S304中所示之基準資料及進行記憶處理，將產生 變動之電源電流值作為新之基準資料記憶於EEpR〇M 2〇6 中（S312)。進而，8312之後’控制電路將開關2〇3短路而 使動作判定電路2〇〇及積體電路1〇成為一般動作狀態 (S310)。 另一方面’於S309中，當比較電路208檢測出基準資料 之值與檢測資料之值之差未滿特定值（例如以數位值表示 而未滿3)之情形時’將處理移行至S3 10。 [實施例2] (定期之積體電路10之自我檢測） 又’亦可定期進行積體電路1〇之自我檢測（動作確認測 '式）及自我修復。具體而言，亦可如上述實施例1中所說明 於顯示裝置之每個垂直返驰期間，進行積體電路10之自我 檢測（動作確認測試）及自我修復。此時，對垂直同步信號 進行計數，於每個固定次數之顯示中進行上述自我檢測及 自我修復。此時，由非揮發性之記憶體構成計數器，計數 143488.doc 201030412 °對垂直同步㈣之次數進行計數，藉此可實現。進而， ，可為如下構成：積體電路1G包含载時間之計時器，藉 t該計時n而對動作時間進行計數，於每個縣設定之累 • 作時間進行積體電物之自我檢測及自我修復。 [實施例3] 積體電路1〇之自我檢測（動作確認測試）及自我修復 2處理動作亦可於顯示裝置進行影像顯示之期間之一部分 • 心了 W如顯不裝置之各像素記憶顯示電極之電壓，因 此顯示電極之電壓之充雷姓 .^ 兄電、、、°束後，即便使積體電路10之輸 出端子〇UT1〜OUTn成為高阻抗， 示仍不存在問題。 顯不裝置中之影像之顯 因此於顯不裝置進行影像顯示之顯示期間之一部分 電路!。之輸出端子Ο·。，成為高阻抗而 = ㈣_及自我修復之處理動作。作 為使輸出端子OUT1〜OUTn成為高阻抗之方法之一例，相 • 對於使輸出端子OUT1〜OUTn盥顯 傳送路徑而串聯設置開關，將該開關1之每個信號 兩者電氣切斷。 成為阿阻抗’換言之可將該 我檢測（動作確認測試）中，如本實施形⑸所 = 個模式。因此，若無進行自我檢測(動作確 二二Τ我檢測(動作確_試)之-部分模式(例 如僅一種模式）。藉此，可於顯示裝置之一幢之顯示期間 143488.doc -81- 201030412 或數幀之顯示期間進行自我檢測（動作確認測試）之所有模 式。又，若採用不一次性地進行自我檢測（動作確認測試、) 之模式而將各模式分開進行之上述方法，則可於圖所示 之水平返馳期間進行自我檢測（動作確認測試）。 再者，上述實施例i〜3中，將實施形態i中之積體電路1〇 作為對象進行了說明，但本發明並不限於此，亦可適用於 實施形態2及3中之積體電路1〇,、2〇以及實施形態4中之顯 示部90”。 又，本實施形態1〜4中，對藉由液晶顯示面板顯示影像 之液晶顯示裝置進行了說明，但本發明並不限於此，亦可 適用於除液晶顯示裝置以外之顯示裝置例如電漿電視等。 本發明並不限定於上述各實施形態，可於請求項所示之 範圍内進行各種變更，適當地組合不同實施形態中所分別 揭示之技術性機構而獲得之實施形態亦包含於本發明之技 術性範圍内。 再者’亦可以如下方式構成本發明之顯示裝置驅動用之 積體電路及顯示裝置。 [第1構成] 一種驅動電路，其特徵在於：其係驅動顯示面板者，且 包含對成為不良之該驅動電路進行自我修復之自我修復 機構。 [第2構成] 如第1構成之驅動電路，其中包含輸出用以驅動上述顯 示面板之輸出信號之輸出電路， 143488.doc -82« 201030412 上述自我修復機構包含 對上述輸出電路县$ 不良進行判定之判定機構，且 於上述判定機構之判士 尺、、，〇果為不良之情形時，以對上述 顯示面板輸出正常之輪ψ • 、 出4唬之方式對該驅動電路進行自 我修復。 " [第3構成] 如第2構成之驅動電路， 具中包含可對上述顯示面板輸 ❿ 出上述輸出信號之㈣輸出電路， 上述自我修復機構包含 ，刀換機冑*係於上述判定機構之判定結果為不良之情 形時，將來自上述成為不良之輸出電路之輸出信號切換為 來自上述預備輸出電路之捺 輸出仏旒而作為向上述顯示面板 之輸出信號。 [第4構成] 如第3構成之驅動電路，其中上述判定機構， • 包含比較機構，其將央ό μ、+、& , & t 丹糈來自上述輸出電路之輸出信號與來 自上述預備輸出電路之輪出信號進行比較，且 根據上述比較機構之比較社罢料 衩結果，對上述輸出電路是否不 良進行判定。 - [第5構成] -種顯示裝置，其特徵在於包含第i構成至“構成中任 一構成之驅動電路與上述顯示面板。 [第6構成] -種顯示裝置，其特徵在於：其係包含顯示面板與驅動 143488.doc -83- 201030412 電路者， 該驅動電路包含輸出用以驅動上述顯示面板之輸出信號 之輸出電路， 上述驅動電路包含： 判定機構，其對上述輸出電路是否不良進行判定；以及 預備輸出電路，其可對上述顯示面板輸出上述輸出信號； 上述顯示面板包含切換機構， 該切換機構係於來自上述判定機構之判定結果為不良之 情形時’將來自上述成為不良之輸出電路之輸出信號切換 為來自上述預備輸出電路之輸出信號而作為驅動該顯示面 板之輸出信號。 [第7構成] 一種顯示裝置’其特徵在於包含： 顯示面板； 輸出電路，其輸出用以驅動上述顯示面板之輸出，號· 預備輸出電路，其可對上述顯示面板輸出上述輸出作 號； 〇 判定機構’其對上述輸出電路是否不良進行判^ ;以及 切換機構’其於上述判定機構之欺結果為不良之情形 時’將來自上述成為不良之輸出電路之輪出信號切換為來 自：述預備輸出電路之輸出信號而作為驅動上述顯示 之輸出信號。 [第8構成] -種電視系統’其特徵在於包含如請求項5至”任一項 143488.doc -84· 201030412 之顯示裝置。 [第9構成] 一種驅動電路，其特徵在於包含： , 輸出端子，其連接於顯示面板； 輸出電路區塊，其包含可連接於 ' 路；以及 ••铷螺子之輸出電 預備輸出電路區塊’其包含可連接於上述輪出端子 φ 備輸出電路；且驅動上述顯示面板， 上述驅動電路包含：比較機構，其將來自上 之輸出信號與來自上诚箱供A山恭 電路 、米自上述預備輸出電路之輸出信號進行比 較，Further, the operation of the operation confirmation test and the self-repair can be performed at the same time, that is, the liquid crystal driving semiconductor integrated circuit 10 is configured to detect the abnormality of the liquid crystal driving semiconductor integrated circuit 10 in the liquid crystal. This operation is performed when an abnormality occurs in the semiconductor integrated circuit 10 for driving. For example, the current output from the signal output from the liquid crystal driving semiconductor integrated circuit 10 can be detected, and the operation confirmation test and the self-repair processing operation can be performed when the detected current is more than the set current. Further, the action confirmation test and the self-repair process can be performed periodically. For example, the operation may be performed during each vertical flyback period in which display is not performed, or may be performed at each accumulated display time set in advance. Further, the operation confirmation test and the self-repair processing operation can also be performed in one of the periods during which the display is performed. For example, since the pixel memory of the liquid crystal display device displays the electric power a, even after the display of the display voltage is completed, even if the output of the liquid crystal driving semiconductor integrated circuit 1G is made high impedance, there is no problem in display. In the display period, the output of the liquid crystal driving semiconductor integrated circuit 10 is made high impedance, and the operation confirmation test and the self-repair processing operation are performed. In this case, if the time for confirming the test mode is not performed, the determination of, for example, the mode may be performed in one of the display periods of one line, and the display of the image may be performed (four) or several displays. 143488.doc 71- 201030412 During the period of the screen. The trap is carried out from G (refer to Fig. 18). In order to detect the lack of self (the material is recognized), the board 8 is required. The output signal (refer to Figure 2) stops. That is, the integrated circuit is not surfaced. The time of detection is == display: This is performed during the period in which the 'long circuit 10 is*. In the embodiment of the present invention, during the self-detection of the integrated circuit as the integrated circuit, the self-detection and self during the power-on of the integrated circuit hoof display device are performed. An example of a fix is given. The reason is that if the display device is not in the process of starting the display device, the self-detection and self-repair are performed in a state in which the display device does not subscribe to the image of the device (4). . As described above, the integrated circuit 1 (in the present embodiment) performs self-detection for detecting self-defects when the power of the display device is turned on, but the present invention is not limited thereto, and may be used in addition to the display device. Self-test and self-repair during periods other than during the start-up process. Hereinafter, a period in which self-detection and self-repair can be performed other than during the startup of the display device will be described as an embodiment. [Embodiment 1] (Self-detection and self-repair during vertical flyback) First, as a first embodiment, in the vertical flyback period of the display device, the integrated circuit 10 can display the image of the display device without Self-detection and self-healing in the state of influence. The reason is explained below. 143488.doc -72· 201030412 Hereinafter, the timing of each signal input to the display device will be described with reference to Figs. 39(a) to 39(f). 39(a) to 39(B) are timing charts showing timings of signals input to the liquid crystal display device. Fig. 39(a) shows the output from the scanning side driving circuit of the scanning line of the self-driving display device, and is supplied to the display. The scanning signal SCN1 of the first scanning signal line of the device 'b' shows the scanning signal SCN2 output from the scanning side driving circuit and supplied to the second scanning signal line of the display device, and the graph φ shows the self-product The body circuit 10 (refer to FIG. 18) is supplied to the image signal DSj corresponding to the jth data signal line of the display device of the image signal inversion circuit, and the figure (d) is provided from the image signal inversion circuit to the data side. The image signal DRVj corresponding to the jth data signal line of the display device of the driving circuit, the figure (e) showing the image signal DATAj supplied to the 『th root data signal line of the display device, the figure (1) indicating that the pair is connected The driving voltage VDlj applied by the pixels of the first scanning L line and the jth data signal line in the display device. Further, the period τν of the time t1 to t5 shown in FIG. 39 is the vertical scanning period of the display device. period The TV1 is a vertical flyback period, and the period TH of the time t1 to t3 is the horizontal scanning period, and the period TH1 of the time t2 to t3 is the horizontal return period. Further, the image signal inverting circuit is as follows: During the flat scanning period TH and the vertical scanning period, the TV inverts the polarity of the image signal DSj from the integrated circuit 1 to reverse the polarity of the display electrodes in each pixel of the display device. As shown in Fig. 39(a) and b) The scanning side driving circuit sequentially delays the horizontal scanning period TH from the first scanning signal line, and outputs the scanning signal SCN1 and the scanning signal 143488.doc • 73 to each scanning signal line of the display device. 201030412 SCN2, ..., scan signal SCNm. Further, the scan side drive circuit repeatedly outputs each scan signal SCN1 to scan signal SCNm to each scan signal line of the display device during each vertical scan period. The device includes m scanning signal lines. The image signal DSj from the integrated circuit 1〇 shown in Fig. 39(c) is input to the image 彳s number inverting circuit. Then the 'image signal inverting circuit is at each level. During the tracing period TH, the polarity of the image signal DSj is inverted, and the polarity of the image signal DSj is inverted by the TV during each vertical scanning period to generate the image signal DRVj shown in FIG. 39(d). The circuit inputs the generated image signal DRVj to the data side driving circuit. Then the 'data side driving circuit samples the image signal DRVj from the image signal inverting circuit during each horizontal scanning period TH, and samples the sampled signal value After delaying one horizontal scanning period TH, it is output to the jth data signal line of the display device as the video signal DATAj shown in FIG. 39(e). Then, in the pixel of the display device connected to the first scanning signal line and the jth data signal line (hereinafter referred to as pixel (1), by the scanning signal SCN1 during the horizontal scanning period from time u to t2, The TFT in the pixel lj is turned on, and the result is applied to the display electrode in the pixel 1j as the driving voltage vd lj as the driving voltage vd lj via the jth data signal line '. That is, it is convenient to turn off the turn-on of the TFT in the pixel J at the time t2 to t5, and the driving voltage VDlj applied to the display electrode of the pixel continues to maintain the voltage level during the period of time t1 to t2. Similarly, *' In the pixel of the second scanning signal line and the jth data signal line 143488.doc 201030412 (hereinafter referred to as pixel 2j), by the scanning signal SCN2 during the horizontal scanning period TH at time t3 to t4, On the other hand, the TFT in the pixel is turned on, and as a result, the image signal voltage of the image L number DATAj at the time t3 to t4 is applied as a driving voltage to the display electrode in the pixel via the jth data signal line. also In order to turn on the TFT in the pixel, the driving voltage applied to the display electrode of the pixel 2j is maintained at the voltage level during the period from time t3 to time t4. As described above, even if the TFT is turned on in each pixel. When the voltage is off, the driving voltage in each pixel of the display device is maintained at the voltage level of the driving voltage applied when the TFT is turned on. Therefore, the scanning side driving circuit does not scan the signals SCN1 to SCNm for turning on the TFTs of the respective pixels. Outputted to the scanning signal line, in other words, during the period in which the TFT of each pixel is turned off, that is, during the vertical flyback period TV1, the display device does not need to apply a voltage to the display electrodes of the respective pixels. That is, the integrated circuit 10 does not need to be output as the driving voltage. At the root of the video signal DSj, even if the integrated circuit 1〇 is electrically disconnected from the display device, φ does not affect the image display of the display device. Therefore, the right is the vertical flyback period of the display device. The body circuit (7) can perform self-detection and self-repair without affecting the image display of the display device. - (The overall operation of the integrated circuit 10 Good detection) The self-detection processing of the defective output circuit block included in the integrated circuit 10 in the present embodiment is performed on each output circuit block corresponding to each data signal line, and The entire output circuit block is processed as an object. Therefore, the self-detection process requires time. 143488.doc -75- 201030412 Therefore, no malfunction occurs in each of the output circuit blocks included in the integrated circuit 10. In the case of possibility, Ji Zhao Cong Cong needs to perform self-detection processing. In other words, the ' _ circuit works in the case where there is a possibility of malfunction in each output circuit block, and self-detection processing can be performed. Here, the integrated circuit 10 includes an operation determination circuit, and it is determined that there is a possibility that the integrated circuit 1 is not defective in operation as long as the integrated circuit 1G is determined only by the operation determination circuit. In the case of a bad situation, self-detection processing can prevent self-detection processing in vain. Hereinafter, an operation determination circuit 200 for determining whether or not there is a possibility of malfunction in the integrated circuit 10 included in the integrated circuit 1A will be described with reference to Figs. 40 to 42. First, in the (4) circuit H), a malfunction occurs, and the power supply current supplied to the integrated circuit 10 is higher than that in the normal operation, in other words, compared with the initial stage when it is judged to be a good product when it is shipped as a product. Therefore, when the value of the power supply current supplied to the integrated circuit 1 is larger than the fixed value, the operation failure occurs in the integrated circuit 1 . Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 1A, and determines whether or not a malfunction has occurred in the integrated circuit 10 based on the detected value of the power supply current. (Configuration of Operation Determination Circuit 200) Hereinafter, the configuration of the operation determination circuit 2A will be described with reference to FIG. Fig. 40 is a block diagram showing the configuration of the operation judging circuit 2A. As shown in FIG. 40, the operation determination circuit 2 is connected between the VA 201 and the integrated circuit 10 that supply power to the integrated circuit 1A, and includes a resistor 2〇2 (detection mechanism) 143488.doc • 76- 201030412 and a switch. 203. Further, the resistor 202 and the switch 203 are connected in parallel to each other. Further, the operation determination circuit 200 includes an A/D converter 204 (detection mechanism) connected to one end of the resistor 202 and the switch 203 on the side of the integrated circuit 10, and a switch 205 whose input is from the A/D converter 204. Output signal; EEPROM (Electrically Erasable and Programmable Read Only Memory) 206 (normal current value memory mechanism), which is a non-volatile memory connected to an output terminal of one of the switches 205; A data latch circuit 207 connected to the other output terminal of the switch 205; and a comparison circuit 208 (current value comparing means, drive circuit determining means) for outputting the output value of the EEPROM 206 and the output from the data latch circuit 207 Values are compared. Further, the output terminal of the comparison circuit 208 is connected to a control circuit included in the integrated circuit 10, and outputs the comparison result in the comparison circuit 208 to the control circuit. Furthermore, the switching of the switches 203 and 205 is controlled by the control circuit included in the integrated circuit 10. (Schematic Operation of Operation Determination Circuit 200) The operation determination circuit 200 stores the value corresponding to the power source current value when the integrated circuit 10 operates normally as the reference data in the EEPROM 206. Here, when determining whether or not a malfunction occurs in the integrated circuit 1A, the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit, and detects the detected value with the EEPROM 206. When the value of the reference data stored in advance is compared, when the detected value is equal to or greater than the fixed value, it is determined that the integrated circuit 10 has a malfunction. Further, the operation determination circuit 200 outputs, to the control circuit 143488.doc-77-201030412 included in the integrated circuit 10, a signal indicating that a malfunction has occurred in the integrated circuit ί, whereby the control circuit starts self-detection of the integrated circuit 10. Processing and self-healing processing. (Generation and Memory Processing of Reference Data) As described above, the operation determination circuit 200 needs to store the reference data in advance in the EEPROM 206 included in itself. Therefore, a process for the operation determination circuit 200 to store the reference data in the EEPROM 206 will be described below with reference to FIG. Fig. 41 is a flow chart showing the operation of the operation determination circuit 200 for storing the reference data in the EEPROM 206. As shown in Fig. 41, when the reference data is generated, the control circuit turns on the switch 203 to cause the power source current from the VA 201 to flow in the resistor 202 (S301). Here, the resistance value of the resistor 202 is such that the voltage of the resistor 202 when the integrated circuit 1 is normally operated is reduced to a resistance value of about 0.1 V. Furthermore, the resistance value of the resistor 202 should be determined in consideration of the current consumption of the integrated circuit. Then, the A/D converter 204 converts the voltage value at one end of the integrated circuit 10 side of the resistor 202 into a digital value (S302). The A/D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205. The EEPROM 206 memorizes the input digital value from the A/D converter as a base material (S303). Furthermore, the switch 205 in S303 is switched by the control circuit to connect the A/D converter 204 to the EEPROM 206. Then, after the EEPROM 206 memorizes the basic data, the control circuit short-circuits the switch 203 to return the integrated circuit 1 to the normal operation state (S3〇4). Furthermore, the generation and memory processing of the reference data from S301 to S304 is performed at the factory stage of the display device including the integrated circuit 10, in other words, the system is 143488.doc-78-201030412 in the integrated circuit ίο The inspection is judged to be a normal stage. (Operation failure detection processing of the operation determination circuit 200) Next, a process of detecting the malfunction of the integrated electric circuit 10 in the operation determination circuit 200 will be described below with reference to Fig. 42. Fig. 42 is a flowchart showing the processing of the malfunction of the detected integrated circuit 10 in the operation determination circuit 200. As shown in Fig. 42, first, the control circuit opens the switch 203 to cause the power source current from the VA 201 to flow in the resistor 202 (S305). Then, the A/D converter 204 converts the voltage value of the resistor 202 to one end of the integrated circuit 10 side into a digital value (S3 06). The A/D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205. The data latch circuit 207 memorizes the input digital value from the A/D converter as detection data (S307). Further, the switch 205 in S306 is switched by the control circuit to connect the A/D converter 204 and the data latch circuit 207. φ Then, the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data memorized by the data latch circuit 207, and compares the value of the read reference data with the value of the detected data (S308). Further, the comparison-circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is a specific value or more (for example, a digital value of 3 or more) (S309). In the case where the difference between the value of the reference data and the value of the detection data is a specific value or more (for example, when the digital value is 3 or more), a signal indicating that the malfunction of the integrated circuit 10 is generated is output to the integrated circuit. 10 control circuits included. Here, the control circuit starts the self-detection of the integrated circuit ίο from the comparison circuit 208 after inputting a signal indicating that the operation failure has occurred in the integrated circuit 10 143488.doc -79- 201030412 (S311). Further, when the integrated circuit 10 detects a defect in its own output circuit block in the self-detection of the integrated circuit 1A, the integrated circuit 10 switches the output of the defective output circuit block to the preliminary output circuit. The output of the block is self-healing. Further, when the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 1 of S311, the fluctuation of the power supply current value due to other factors is considered. Therefore, at this time, "the power supply current value fluctuates, so the operation determination circuit 200 generates the reference data shown in S301 to S304 and performs the memory processing, and stores the generated power supply current value as the new reference data in the EEpR 〇 M 2 〇6 (S312). Further, after 8312, the control circuit short-circuits the switch 2〇3, and causes the operation determination circuit 2A and the integrated circuit 1 to be in a normal operation state (S310). On the other hand, in S309, when the comparison circuit 208 detects that the difference between the value of the reference data and the value of the detected data is less than a specific value (for example, represented by a digital value but less than 3), the process proceeds to S3 10 . [Embodiment 2] (Self-detection of the integrated integrated circuit 10) It is also possible to periodically perform self-detection (operation confirmation measurement) of the integrated circuit 1 and self-repair. Specifically, the self-detection (action confirmation test) and self-repair of the integrated circuit 10 can be performed during each vertical flyback period of the display device as described in the first embodiment. At this time, the vertical sync signal is counted, and the above self-detection and self-repair are performed in each fixed number of displays. At this time, the counter is composed of non-volatile memory, and the number of times of vertical synchronization (four) is counted by counting 143488.doc 201030412 °, thereby achieving this. Further, the integrated circuit 1G may include a timer for carrying time, and the operation time is counted by the time n, and the self-detection of the integrated body is performed at the time set by each county. Self-healing. [Embodiment 3] The self-detection (operation confirmation test) and the self-repair 2 processing operation of the integrated circuit 1 can also be performed in one part of the period during which the display device performs image display. Therefore, there is no problem in the display of the voltage of the electrode. The display of the image in the display device is thus part of the display circuit during the display period of the display device. The output terminal Ο·. , becomes a high impedance and = (four) _ and self-repair processing action. As an example of a method of making the output terminals OUT1 to OUTn high impedance, the phase switches are provided in series with the output terminals OUT1 to OUTn, and each of the switches 1 is electrically disconnected. Into the A-impedance, in other words, in the test (action confirmation test), as in the embodiment (5) = mode. Therefore, if there is no self-test (the action is indeed the second part of the test (action confirmed _ test) - part mode (for example, only one mode). Thus, during the display period of one of the display devices 143488.doc -81 - 201030412 or all modes of self-test (action confirmation test) during the display period of several frames. In addition, if the above method is performed by separately performing the mode of self-detection (action confirmation test) without one-time operation, Self-detection (operation confirmation test) can be performed during the horizontal hopback period shown in the figure. In the above-described embodiments i to 3, the integrated circuit 1 实施 in the embodiment i has been described as an object, but the present invention has been described. The present invention is not limited to this, and can be applied to the integrated circuits 1A and 2B of the second and third embodiments and the display unit 90" of the fourth embodiment. Further, in the first to fourth embodiments, the liquid crystal is used. Although the liquid crystal display device for displaying an image on the display panel has been described, the present invention is not limited thereto, and may be applied to a display device other than the liquid crystal display device, such as a plasma TV. The present invention is not limited to the above. The embodiment can be variously modified within the scope of the claims, and the embodiments obtained by appropriately combining the technical mechanisms disclosed in the different embodiments are also included in the technical scope of the present invention. The integrated circuit for driving the display device of the present invention and the display device are configured as follows. [First configuration] A drive circuit for driving a display panel and including self-repairing the drive circuit that is defective [Second Configuration] The driving circuit of the first configuration includes an output circuit for outputting an output signal for driving the display panel, 143488.doc - 82 « 201030412 The above self-healing mechanism includes the above output circuit In the case where the judgment unit of the county is judged to be inferior, and the result of the judgement of the above-mentioned judgment institution is that the result is bad, the drive circuit outputs the normal rim and the output of the display panel. < [3rd configuration] The drive circuit of the second configuration includes the display surface The board outputs the (four) output circuit of the output signal, wherein the self-healing mechanism includes: when the determination result of the determining means is bad, switching the output signal from the defective output circuit to The output signal from the preliminary output circuit is used as an output signal to the display panel. [Fourth configuration] The driving circuit according to the third aspect, wherein the determining means includes a comparing means, which is όμ, + And &, & t the output signal from the output circuit is compared with the round-out signal from the preliminary output circuit, and based on the result of the comparison mechanism of the comparison mechanism, determining whether the output circuit is defective or not . - [Fifth Configuration] A display device including the ith configuration to the "display circuit of any one of the configurations" and the display panel. [Sixth configuration] The display device includes The display panel and the driver 143488.doc-83-201030412 circuit, the driving circuit includes an output circuit for outputting an output signal of the display panel, and the driving circuit includes: a determining mechanism that determines whether the output circuit is defective; And a preliminary output circuit that outputs the output signal to the display panel; the display panel includes a switching mechanism that is configured to cause a defective output circuit when the determination result from the determination mechanism is defective The output signal is switched to an output signal from the preliminary output circuit as an output signal for driving the display panel. [Seventh Configuration] A display device includes: a display panel; an output circuit whose output is used to drive the display panel Output, number · preliminary output circuit, which can be used for the above display The panel outputs the output number; the 〇 determination mechanism 'determines whether the output circuit is defective; and the switching mechanism' when the spoofing result of the determining mechanism is bad, 'will turn from the above-mentioned bad output circuit The output signal is switched to an output signal from the preparatory output circuit as an output signal for driving the display. [Embodiment 8] A television system is characterized in that it includes any one of claims 1-5488.doc-84 as claimed in claim 5 to · 201030412 display device. [9th configuration] A driving circuit comprising: an output terminal connected to a display panel; an output circuit block including an output electric pre-output circuit block connectable to the 'way; and • a snail 'Includes an output circuit connectable to the above-mentioned wheel terminal φ; and drives the display panel, the drive circuit includes: a comparison mechanism that outputs an output signal from the upper box to A Shangong circuit, m from the above The output signals of the preliminary output circuit are compared,

判定機構，其根據上述比較機構之比較結果，對上 出電路是否不良進行判定； J 連接切換機構，其於上述判定機構之判定結果為不良之 情形時，使上述預備輸出電路代替上述輸出電路 • 上述輸出端子。 ' [第10構成] 。。如第9構成之驅動電路，其中上述比較機構為運算放大 器。 [第11構成] 如第9構成之驅動電路，其中上述輸出電路區塊及上述 預備輸出電路區塊進一步包含使用有運算放大器之輸出緩 衝Γ於使用上述運算放大器作為上述比較機構而上述判 疋結果為不良之情形時，連接上述預備輸出電路區塊而代 143488.doc •85- 201030412 替上述輸出電路區塊。 [第12構成] 如第9構成之驅動電路，其中上述輪出電路區塊及上述 預備輸出電路區塊進一步包含：使用有運算放大器之輸出 緩衝器·，以及記憶提供給輸出電路之輸入端之信號之電 路；於使用上述運算放大器作為上述比較機構而上述判定 結果為不良之情形時，連接上述預備輸出電路區塊而代替 上述輸出電路區塊。 [第13構成] 如第9構成至第12構成中任一項之驅動電路，其中包含 對輸入至上述輸出電路及預備輸出電路之輸入信號進行控 制之控制機構， 上述控制機構係對上述輸出電路與預備輸出電路輸入大 小相異之輸人信號，並輸出與上述大小相異之輸入信號相 對應之、來自上述比較機構之比較結果之期望值， 上述判定機構係於上述比較結果與上述期望值不同之情 形時’將上述輸出電路判定為不良。 [第14構成] 如第9構成至第13構成中任一構成之驅動電路，其中進 一步包含儲存表示上述判定機構之判定結果之旗標的旗標 儲存機構， 當上述旗標之值表示上述輸出電路為不良時上述連接 切換機構使上述預備輸出電路代替卜汁於山兩 电播n朁上述輸出電路而連接於 上述輸出端子。 143488.doc 201030412 [第15構成] 如第9構成至第14構成中任一構成之驅動電路，其中於 不會對上述顯示面板所顯示之圖像產生影響之期間， 上述比較機構將來自上述輸出電路之輸出信號與來自上 述預備輸出電路之輸出信號進行比較， 上述判定機構根據上述比較機構之比較結果，對上述輸 出電路是否不良進行判定， 上述連接切換機構將對於上述輸出端子之連接，自藉由 上述判定機構判定為不良之輸出電路之輸出端切換為上述 預備輸出電路之輸出端， 於上述連接切換機構將上述輸出端子與上述預備輸出電 路之輸出端連接後，上述預備輸出電路對上述輸出端子輸 出輸出信號。 [第16構成] 如第9構成至第15構成中任一構成之驅動電路，其中進 一步包含： 檢測機構，其對供給至上述驅動電路之電源電流之值進 行檢測； 正常電流值記憶機構，其預先記憶上述驅動電路正常動 作時之上述電源電流之值； 電流值比較機構，其將來自上述檢測機構之電源電流之 值與來自上述正常電流值記憶機構之電源電流之值進行比 較；以及 驅動電路判定機構，其根據上述電流值比較機構之比較 143488.doc -87- 201030412 結果，對上述驅動電路是否不良進行判定； 於上述驅動電路判定機構之判定結果為不良之情形時， 上述比較機構將來自上述輸出電路之輸出信號與來自上 述預備輸出電路之輸出信號進行比較， 、 上述判定機構根據上述比較機構之比較結果，對上述輪 出電路是否不良進行判定， 上述連接切換機構將對於上述輸出端子之連接，自藉由 上述判定機構判定為不良之輸出電路之輸出蠕切換為上述 預備輸出電路之輸出端。The determining means determines whether the upper circuit is defective or not based on the comparison result of the comparing means; and the J connection switching means causes the preliminary output circuit to replace the output circuit when the determination result of the determining means is defective. The above output terminal. ' [10th composition]. . A driving circuit according to the ninth aspect, wherein the comparing means is an operational amplifier. [11th configuration] The drive circuit of the ninth aspect, wherein the output circuit block and the preliminary output circuit block further include an output buffer using an operational amplifier, and the use of the operational amplifier as the comparison means In the case of a bad situation, connect the above-mentioned preliminary output circuit block and replace the above output circuit block with 143488.doc •85- 201030412. [12th configuration] The driving circuit of the ninth aspect, wherein the round-trip circuit block and the preliminary output circuit block further include: an output buffer using an operational amplifier, and a memory supplied to an input terminal of the output circuit In the case of using the operational amplifier as the comparison means and the determination result is defective, the preparatory output circuit block is connected instead of the output circuit block. [13th configuration] The driving circuit according to any one of the ninth to twelfth aspects, comprising: a control unit that controls an input signal input to the output circuit and the preliminary output circuit, wherein the control unit is connected to the output circuit And an input signal different from the input size of the preliminary output circuit, and outputting an expected value of the comparison result from the comparison means corresponding to the input signal different in size, wherein the determining means is different from the expected value In the case of the case, the above output circuit is judged to be defective. [Fourteenth configuration] The drive circuit of any one of the ninth to thirteenth configurations, further comprising: a flag storage mechanism that stores a flag indicating a determination result of the determination means, wherein the value of the flag indicates the output circuit In the case of failure, the connection switching means connects the preparatory output circuit to the output terminal instead of the output circuit of the second antenna. [Fourteenth configuration] The driving circuit according to any one of the ninth to fourteenth aspects, wherein the comparing means is from the output while not affecting an image displayed on the display panel The output signal of the circuit is compared with an output signal from the preliminary output circuit, and the determining means determines whether the output circuit is defective based on a comparison result of the comparing means, and the connection switching means lends the connection to the output terminal The output end of the output circuit determined to be defective by the determining means is switched to the output end of the preliminary output circuit, and after the connection switching means connects the output terminal to the output end of the preliminary output circuit, the preliminary output circuit pairs the output The terminal outputs an output signal. [16th configuration] The drive circuit of any one of the ninth to fifteenth configurations, further comprising: a detection mechanism that detects a value of a power source current supplied to the drive circuit; and a normal current value memory mechanism Pre-memorizing the value of the power source current when the driving circuit is normally operated; the current value comparing mechanism comparing the value of the power source current from the detecting mechanism with the value of the power source current from the normal current value memory mechanism; and the driving circuit a determining unit that determines whether the driving circuit is defective according to a comparison of the current value comparing means 143488.doc -87-201030412; and when the determining result of the driving circuit determining means is bad, the comparing means will come from The output signal of the output circuit is compared with an output signal from the preliminary output circuit, and the determining means determines whether the round circuit is defective based on a comparison result of the comparing means, and the connection switching means is for the output terminal Connection, self-reliance The output of the output circuit determined to be defective by the determining means is switched to the output end of the preparatory output circuit.

[第17構成J 如第9構成至第16構成中任一構成之驅動電路，其中於 上述顯示面板之電源剛接通後， 上述比較機構將來自上述輸出電路之輸出信號與來自上 述預備輸出電路之輸出信號進行比較， 上述判定機構根據上述比較機構之比較結果，對上述輸 出電路是否不良進行判定， 上述連接切換機構將對於上述輸出端子之連接，自藉由 上述判定機構判定為不良之輸出電路之輸出端切換為上述 預備輸出電路之輸出端。 [第18構成] 如第9構成至第16構成中任一構成之驅動電路，其中於 上述顯示面板之垂直返馳期間， 上述比較機構將來自上述輸出電路之輸出信號與來自上 述預備輸出電路之輸出信號進行比較， 143488.doc -88- 201030412 上述判定機構根據上述比較機構之比較結果，對上述輸 出電路是否不良進行判定， 上述連接切換機構將對於上述輸出端子之連接，自藉由 上述判定機構判定為不良之輸出電路之輸出端切換為上述 預備輸出電路之輸出端。 [第19構成] 如第9構成至第18構成中任一構成之驅動電路，其中進[17th configuration J] The drive circuit of any one of the ninth to sixteenth configurations, wherein the comparison means outputs an output signal from the output circuit and the preliminary output circuit after the power of the display panel is turned on. Comparing the output signals, the determining means determines whether the output circuit is defective based on a comparison result of the comparing means, and the connection switching means determines the connection to the output terminal from the output circuit determined to be defective by the determining means The output is switched to the output of the above preparatory output circuit. [18th configuration] The drive circuit according to any one of the ninth to 16th configurations, wherein the comparison means outputs an output signal from the output circuit and the output from the preliminary output circuit during a vertical flyback period of the display panel The output signal is compared, 143488.doc -88- 201030412, the determining means determines whether the output circuit is defective according to the comparison result of the comparing means, and the connection switching means connects the output terminal by the determining means The output terminal of the output circuit determined to be defective is switched to the output terminal of the preliminary output circuit. [19th configuration] The drive circuit of any one of the ninth to eighteenth configurations, wherein

步匕3將自上述輸出端子至上述顯示面板之信號傳送路 徑切斷之切斷機構， 口於上述切斷機構將自上述輸出端子至上述顯示面板之信 號傳送路徑切斷後， 、上述比較機構將來自上述輸出電路之輸出信號與來自上 述預備輸出電路之輸出信號進行比較， 上述判^機構根據上述比較機構之比較結果，對上述輸 出電路是否不良進行判定， 上述連接切換機構將對於上述輸出端子之連接自藉由 上述判定機構判定為不良之輸出電路之輸出端切換為上述 預備輸出電路之輸出端。 [產業上之可利用性] —本發明提供-種顯示裝置，其包含對輸出電路之缺陷進 丁檢測及自我修復之具體的機構，且包含可更容易處理輸 出電路之不良之顯示驅動用積艘電路，特別是本發明較佳 -適；可以適田之時機進行自我檢測及自我修復之液晶顯 示裝置。 143488.doc •89- 201030412 【圖式簡單說明】 圖1係表示本發明之一實施形態之液晶電視之構成的方 塊圖。 圖2係表示本發明之一實施形態之顯示裝置之構成的方 塊圖。 圖3係表示本發明之一實施形態之液晶電視之外觀之 圖。 圖4係表示本發明之一實施形態之構成液晶電視中所包 含之積體電路的輸出電路區塊產生異常之情形時之顯示之 一例的圖》 圖5係表示本發明之一實施形態之液晶電視中之自我檢 測及自我修復動作之示例的圖，圖5(a)係表示自我檢測及 自我修復動作開始前之液晶電視之圖，圖5(b)係表示自我 檢測及自我修復動作進行中之液晶電視之圖，圖5(c)係表 示自我檢測及自我修復動作結束後之液晶電視之圖。 圖6係表示本發明之一實施形態之液晶電視中之維護功 能表之顯示例的圖。 圖7係表示本發明之一實施形態之液晶電視中之自我檢 測及自我修復動作之示例的圖，圖7(a)係表示自我檢測及 自我修復動作開始前之液晶電視之圖，圖 檢測及自我修復動作進行中之液晶電視之圖，圖叫係表 不自我檢測及自我修復動作結束後之液晶電視之圖。 圖8係表*本發明之—實施形態之構成液晶電視之TFT_ LCD模組即顯示部中安奘 女裒有對顯不面板進仃驅動之源極驅 143488.doc 201030412 動器之示例的圖。 圖9係表示本發明之一實施形態之構成液晶電視之tft_ LCD模組即顯示部中安裝有對顯示面板進行驅動之源極驅 動器及預備源極驅動器之示例的圖。 圖10係表示使用捲帶式載體’將本發明之一實施形態之 具有自我檢測及自我修復功能之源極驅動器與預備之源極 驅動器並聯安裝於玻璃基板上之狀態的概略圖。 Φ 圖11係表示將圖10所示之捲帶式載體打開之狀態的圖。 圖12係自方向A觀察圖11所示之安裝有源極驅動器及預 備之源極驅動器之捲帶式載體的俯視圖。 圖13係表示本發明之一實施形態之構成液晶電視之tft_ LCD模組即顯示部中，將記憶體安裝於連接著源極驅動器 之輸入端之印刷基板上之示例的圖。 圖14係表示本發明之一實施形態之構成液晶電視之tft_ LCD模組即顯示部中，將記憶體安裝於連接著源極驅動器 φ 之輸入端之印刷基板上之另一例的圖。 圖15係表示於本發明之一實施形態之顯示部之電源斷開 時’進行源極驅動器之自我檢測之順序的流程圖。 •圖16係表示本發明之一實施形態之液晶電視中之自我檢 .測及自我修復動作之一例的圖，圖16(a)係表示自我檢測及 自我修復動作前之液晶電視的圖，圖16〇3)係表示自我檢測 及自我修復動作進行中之液晶電視之圖，圖丨6(勾係表示自 我檢測及自我修復動作結束後之液晶電視之圖。 圖17係表示本發明之一實施形態之液晶電視中之自我檢 143488.doc •91- 201030412 測及自我修復動作之_例的圖，圖17⑷係表示自我檢測及 自我修復動作前之液晶電視之圖，圖17(b)係表示自我檢測 及自我修復動作進行中之液晶電視之圖，圖17(c)係表示自 我檢測及自我修復動作結束後之液晶電視之圖。 圖18係表示本發明之一實施形態之顯示驅動用半導體積 體電路之構成之說明圖。 圖19係表不本發明之一實施形態之動作確認測試之第一 順序之流程圖。 圖20係表示本發明之一實施形態之動作確認測試之第二 順序之流程圖。 圖21係表示本發明之一實施形態之動作確認測試之第二 順序之流程圖。 圖22係表示本發明之一實施形態之動作確認測試之第四 順序之流程圖。 圖23係表示本發明之一實施形態之動作確認測試之第五 順序之流程圖。 圖24係表示本發明之一實施形態之將不良之輪出電路切 換為預備之輸出電路之順序的流程圖。 圖25係表示本發明之一實施形態之自顯示裝置之電源接 通起至進行動作確認測試後移行至一般動作為止之順序的 流程圖。 圖26係表示本發明之一實施形態之用以進行運算放大器 之動作確認之電路構成的說明圖。 圖27係表示本發明之另一實施形態之顯示驅動用半導體 143488.doc •92- 201030412 積體電路之構成的說明圖。 圖2 8係表示本發日月之其 . y + f 之另一實施形態之動作確認 一順序的流程圖。 之第 圖29係表示本發明之另一實施形態之動作確認 二順序的流程圖》 第 -圖30絲示本發明之另—實施形態之動作確認挪 二順序的流程圖。 弟 圖31係、表示本發明之另—實施形態之動作破認 明序㈣程ffl。 之第 圖32係表示本發明之另—實施形態之動作確認測試 五順序的流程圖。 圖33係表示本發明之另一實施形態之將不良之輪出電 切換為預備之輸出電路之順序的流程圖。 圖34係表示本發明之進而另一實施形態之顯示裝置 略構成的方塊圖。 • 圖35係表示本發明之進而另一實施形態之顯示裝置 成的方塊圖。 圖36係表示本發明之進而另一實施形態之自顯示裝置之 電源接通起至進行動作確認測試後移行至一般動作為止 . 順序的流程圖。 之 圖37係表示本發明之進而另一實施形態之顯示裝置之 成的方塊圖。 圖38係表示本發明之一實施形態之電視系統之構成 塊圖》 ^3488.(100 -93- 201030412 圖39(a)〜圖39(f)係表示本發明之一實施形態之輸入至顯 示裝置之掃描信號、影像信號、像素電極之電壓值的時序 圖。 圖4〇係表示表示本發明之一實施形態之動作判定電路之 構成的方塊圖。 圖41係表示本發明之一實施形態之對正常動作時之積體 電路之電源電流值進行檢測及記憶之處理的流程圖。 圖42係表示本發明之一實施形態之根據供給至積體電路 之電源電流值而對積體電路之動作不良進行檢測之處理的 ◎ 流程圖。 圖43係表示先前例中之顯示驅動用半導體積體電路之構 成的說明圖。 【主要元件符號說明】 -1 運算放大器（比較機構） -2 運算放大器（比較機構） -η 運算放大器（比較機構）Step 3: cutting the signal transmission path from the output terminal to the display panel, and cutting the signal transmission path from the output terminal to the display panel by the cutting mechanism, and the comparison mechanism The output signal from the output circuit is compared with an output signal from the preliminary output circuit, and the determining means determines whether the output circuit is defective based on a comparison result of the comparing means, and the connection switching means is for the output terminal The output end of the output circuit connected to the output circuit determined by the above-described determination means is switched to the output end of the preliminary output circuit. [Industrial Applicability] - The present invention provides a display device including a specific mechanism for detecting defects and self-repair of an output circuit, and including a display drive product which can more easily handle an output circuit. The circuit, in particular, the invention is preferably suitable; the liquid crystal display device capable of self-detecting and self-repairing at the timing of the field. 143488.doc • 89- 201030412 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a liquid crystal television according to an embodiment of the present invention. Fig. 2 is a block diagram showing the configuration of a display device according to an embodiment of the present invention. Fig. 3 is a view showing the appearance of a liquid crystal television according to an embodiment of the present invention. 4 is a view showing an example of display when an abnormality occurs in an output circuit block of an integrated circuit included in a liquid crystal television according to an embodiment of the present invention. FIG. 5 is a view showing a liquid crystal according to an embodiment of the present invention. Figure 5 (a) shows the LCD TV before the start of the self-test and self-repair action, and Figure 5 (b) shows the self-test and self-repair action in progress. The picture of the LCD TV, Figure 5 (c) shows the LCD TV after the self-test and self-repair actions. Fig. 6 is a view showing an example of display of a maintenance function table in a liquid crystal television according to an embodiment of the present invention. 7 is a view showing an example of self-detection and self-repairing actions in a liquid crystal television according to an embodiment of the present invention, and FIG. 7(a) is a view showing a liquid crystal television before self-detection and self-repairing operations, and pattern detection and The picture of the LCD TV in the process of self-repair is called the picture of the LCD TV after the self-test and self-repair action. Fig. 8 is a view showing an example of a source drive 143488.doc 201030412 of a TFT-LCD module constituting a liquid crystal television according to an embodiment of the present invention. Fig. 9 is a view showing an example in which a source driver and a preparatory source driver for driving a display panel are mounted on a display unit of a tft_LCD module constituting a liquid crystal television according to an embodiment of the present invention. Fig. 10 is a schematic view showing a state in which a source driver having a self-detection and self-healing function according to an embodiment of the present invention and a preparatory source driver are mounted in parallel on a glass substrate using a tape carrier. Φ Fig. 11 is a view showing a state in which the tape carrier shown in Fig. 10 is opened. Figure 12 is a plan view of the tape carrier in which the source driver and the prepared source driver shown in Figure 11 are viewed from direction A. Fig. 13 is a view showing an example in which a memory is mounted on a printed circuit board to which an input terminal of a source driver is connected, in a display portion of a tft_LCD module constituting a liquid crystal television according to an embodiment of the present invention. Fig. 14 is a view showing another example of mounting a memory on a printed circuit board to which an input terminal of a source driver φ is connected, in a display unit of a tft_LCD module constituting a liquid crystal television according to an embodiment of the present invention. Fig. 15 is a flow chart showing the procedure of performing self-detection of the source driver when the power of the display unit in the embodiment of the present invention is turned off. Fig. 16 is a view showing an example of self-detection and self-repairing operations in a liquid crystal television according to an embodiment of the present invention, and Fig. 16(a) is a view showing a liquid crystal television before self-detection and self-repair operation. 16〇3) is a diagram showing the LCD TV in the process of self-detection and self-repair, and Figure 6 is a diagram showing the LCD TV after the self-detection and self-repair actions are completed. Figure 17 shows an implementation of the present invention. Self-checking in the form of LCD TV 143488.doc •91- 201030412 Measured and self-healing action _ example, Figure 17 (4) shows the LCD TV before self-test and self-repair, Figure 17 (b) shows FIG. 17(c) is a diagram showing a liquid crystal television after the self-detection and the self-repairing operation are completed. FIG. 18 is a view showing a display driving semiconductor according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 19 is a flow chart showing the first sequence of the operation confirmation test according to an embodiment of the present invention. Fig. 20 is a view showing an embodiment of the present invention. Figure 2 is a flow chart showing the second sequence of the operation confirmation test according to an embodiment of the present invention. Fig. 22 is a view showing the fourth operation verification test according to an embodiment of the present invention. Figure 23 is a flow chart showing the fifth sequence of the operation confirmation test according to an embodiment of the present invention. Fig. 24 is a diagram showing the switching of a defective turn-out circuit to a preliminary output circuit according to an embodiment of the present invention. Fig. 25 is a flow chart showing the procedure of moving from the power-on of the display device to the operation after the operation confirmation test according to an embodiment of the present invention. Fig. 26 is a view showing one of the present inventions. FIG. 27 is an explanatory view showing a configuration of an integrated circuit of the display driving semiconductor 143488.doc • 92-201030412 according to another embodiment of the present invention. Fig. 2 is a flow chart showing the sequence of the operation confirmation of another embodiment of the present day and the month y + f. Fig. 29 is a view showing Flowchart of the second embodiment of the operation of the second embodiment of the present invention. Fig. 30 is a flow chart showing the operation of the second embodiment of the present invention. FIG. 31 shows another embodiment of the present invention. Figure 32 is a flow chart showing the fifth sequence of the operation confirmation test according to another embodiment of the present invention. Fig. 33 is a view showing a bad wheel according to another embodiment of the present invention. Fig. 34 is a block diagram showing a schematic configuration of a display device according to still another embodiment of the present invention. Fig. 35 is a view showing still another embodiment of the present invention. A block diagram of the device. Fig. 36 is a flow chart showing the procedure from the time when the power of the display device is turned on until the operation confirmation test is performed after the operation is confirmed to the normal operation in still another embodiment of the present invention. Figure 37 is a block diagram showing a display device according to still another embodiment of the present invention. 38 is a block diagram showing a configuration of a television system according to an embodiment of the present invention. ^3488. (100-93-201030412, FIG. 39(a) to FIG. 39(f) show input to display according to an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of an operation determination circuit according to an embodiment of the present invention. FIG. 41 is a block diagram showing an embodiment of the present invention. Flowchart for detecting and remembering the power supply current value of the integrated circuit during normal operation. Fig. 42 is a view showing the operation of the integrated circuit based on the power supply current value supplied to the integrated circuit according to an embodiment of the present invention. Fig. 43 is an explanatory view showing a configuration of a semiconductor integrated circuit for display driving in the prior art. [Description of main component symbols] -1 Operational amplifier (comparison mechanism) -2 Operational amplifier ( Comparison mechanism) -η operational amplifier (comparative mechanism)

c 開關（連接切換機構） d 開關（連接切換機構） •1 判定電路（判定機構） •2 判定電路（判定機構） n 判定電路（判定機構） 1 判定旗標（旗標儲存機構） 2 判定旗標（旗標儲存機構） n 判定旗標（旗標儲存機構） J43488.doc -94· 201030412c Switch (connection switching mechanism) d Switch (connection switching mechanism) • 1 judgment circuit (determination mechanism) • 2 judgment circuit (judgment mechanism) n judgment circuit (judgment mechanism) 1 judgment flag (flag storage mechanism) 2 judgment flag Standard (flag storage organization) n judgment flag (flag storage organization) J43488.doc -94· 201030412

8-1 DAC電路（輸出電路） 8-2 DAC電路（輸出電路） 8-n DAC電路（輸出電路） 10 液晶驅動用半導體積體電路（驅動電路） 10' 液晶驅動用半導體積體電路（驅動電路） 10a 液晶驅動用半導體積體電路（驅動電路、第j 驅動電路、源極驅動器） 10b 液晶驅動用半導體積體電路（驅動電路、第2 驅動電路、預備源極驅動器） 20 液晶驅動用半導體積體電路（驅動電路） 21 運算放大器（比較機構） 21A 運算放大器（比較機構） 21B 運算放大器（比較機構） 28 DAC電路（預備輸出電路） 28A DAC電路（預備輸出電路） 28B DAC電路（預備輸出電路） 50 比較判定機構（自我檢測與自我修復機構、判定 機構） 60 切換電路（自我檢測與自我修復機構、切換 機構） 61 切換電路（自我檢測與自我修復機構） 80 顯示面板 80， 顯示面板 81 記憶體（記憶裝置） 143488.doc -95- 201030412 82 動作切換輸入端子 83 薄膜基材 84 輸入端子 85 阻焊劑 86 輸出側配線 87 元件孔 88 輸入側配線 89 捲帶式載體 90 顯示部（顯示裝置） 92 像素 93 TFT 94 閘極線 95 源極線 96 玻璃基板 97 印刷基板（PWD) 98 薄膜電纜（FPC) 99 閘極驅動器 100 控制器（寫入控制機構） 202 電阻（檢測機構） 204 A/D轉換器（檢測機構） 206 EEPROM(正常電流值記憶機構） 208 比較電路（電流值比較機構、驅動電路判定 機構） 300 電視糸統 143488.doc -96- 201030412 400 液晶電視 401 開關按钮 402 DVD裝置（影像再生裝置 、DVD再生裝置） 403 HDD裝置（影像再生裝置 、HDD再生裝置） 404 DVD與HDD控制部8-1 DAC circuit (output circuit) 8-2 DAC circuit (output circuit) 8-n DAC circuit (output circuit) 10 Semiconductor integrated circuit for driving liquid crystal (drive circuit) 10' Semiconductor integrated circuit for liquid crystal drive (driver) Circuit) 10a Semiconductor integrated circuit for liquid crystal drive (drive circuit, jth drive circuit, and source driver) 10b Semiconductor integrated circuit for liquid crystal drive (drive circuit, second drive circuit, and preparatory source driver) 20 Liquid crystal drive semiconductor Integrated circuit (drive circuit) 21 Operational amplifier (comparison mechanism) 21A Operational amplifier (comparison mechanism) 21B Operational amplifier (comparison mechanism) 28 DAC circuit (prepared output circuit) 28A DAC circuit (prepared output circuit) 28B DAC circuit (prepared output) Circuit) 50 Comparison judgment mechanism (self-detection and self-repair mechanism, judgment mechanism) 60 Switching circuit (self-detection and self-repair mechanism, switching mechanism) 61 Switching circuit (self-detection and self-repair mechanism) 80 Display panel 80, display panel 81 Memory (memory device) 143488.doc -95 - 201030412 82 Action switching input terminal 83 Film substrate 84 Input terminal 85 Solder resist 86 Output side wiring 87 Component hole 88 Input side wiring 89 Tape carrier 90 Display unit (display unit) 92 Pixels 93 TFT 94 Gate line 95 Source Polar 96 Glass Substrate 97 Printed Substrate (PWD) 98 Thin Film Cable (FPC) 99 Gate Driver 100 Controller (Write Control Mechanism) 202 Resistance (Detection Mechanism) 204 A/D Converter (Detection Mechanism) 206 EEPROM (Normal Current value memory mechanism) 208 Comparison circuit (current value comparison mechanism, drive circuit determination mechanism) 300 TV system 143488.doc -96- 201030412 400 LCD TV 401 switch button 402 DVD device (image reproduction device, DVD reproduction device) 403 HDD Device (image reproduction device, HDD reproduction device) 404 DVD and HDD control unit

143488.doc -97-143488.doc -97-

Claims (1)

201030412 七、申請專利範®： 一種顯示裝置，其特徵在於包含·· 顯示面板； 第1驅動電路，其係驅動上述顯示面板之驅動電路， 且具有對該驅㈣路之不良進行檢測並修復之自我檢測 • 與自我修復機構；及 第2驅動電路，其係驅動上述顯示面板之驅動電路， 且不同於上述第1驅動電路。 參2.如請求項！之顯示裝置，其中 上述第2驅動電路於上述自我檢測與自我修復機構對 上述第1驅動電路之不良進行檢測並修復時，驅動上述 顯示面板。 3.如請求項1之顯示裝置，其中 上述第I驅動電路包含複數個輸出電路，其等輸出用 以驅動上述顯示面板之輸出信號， • β上述自我檢測與自我修復機構包含判定上述輸出電路 疋否不良之判定機構，且於上述判定機構之判定結果為 不良之情形時，以將正常之輸出信號輸出至上述顯示面 板之方式對該驅動電路進行自我修復。 4·如請求項3之顯示裝置，其中 上述第1驅動電路包含可對上述顯示面板輸出上述輸 出信號之預備輸出電路， J 上述自我檢測與自我修復機構包含切換機構，其於上 述判定機構之判定結果為不良之情形時，將來自上述成 143488.doc 201030412 為不良之輸出電路之輸出信 5. 6. 電路的輸出信號而作為向上:二為板= 如請求項4之顯示裝置，其中 —輸出信號。 機構包切來自上述輸出電路之輸出信號、 = = = :電路，信號進行比較的_ :根據上述比較機構之比較結果而判定上 路疋否不良。 其中進一步包含控制機構，其 上述預備輸出電路之輸入信號 如請求項5之顯示裝置， 對輸入至上述輸出電路及 進行控制， 值 上述控制機構對上述輸出電路與上述預備輸出電路輸 入大小相異之輸人信號，並且輸出與上述大小相異之輸 入信號相對應之、來自上述比較機構之比較結果之期望 述判疋機構於上述比較結果與上述期望值相異之情 形時，判定上述輸出電路為不良。 7. 如請求項4之顯示裝置，其中 上述判定機構包含對來自上述複數個輸出電路中之至 /兩個輸出電路之輸出信號進行比較之比較機構，且根 據上述比較機構之比較結果而判定上述輸出電路是否不 良。 8. 如請求項7之顯示裝置，#中進一步包含控制機構，其 ί輸至上述複數個輪出電路中之至少兩個輸出電路之 輸入信號進行控制， 143488.doc 201030412 9. 上述控制機構對上述至少 之铨m # 夕兩個輪出電路輸入大小相異 之輸入15號，並且輸出與上 虛夕^ 兴上这大小相異之輸入信號相對 應之、來自上述比較機構之比較結果之期望值， j述判定機構於上述比較結果與上述㈣值相異之情 形時，判定為上述至少兩個輸出電路中之任一者不良。 如請求項5之顯示裝置，其中 10 上述輸出電路具有運算放大器來作為輸出緩衝器， 上述比較機構係包含上述運算放大器而構成之比較 11. 12. 13. 14. 如請求項9之顯示裝置，其中 上述運算放大器於驅動顯示面板之情形時，作為電壓 隨動器進行動作。 如請求項1之顯示裝置，其中 上述第1驅動電路安裝於上述顯示面板之丨邊上， 上述第2驅動電路於上述顯示面板上，安裝於安裝有 上述第1驅動電路之邊之對邊。 如請求項1之顯示裝置，其中 上述第1驅動電路及上述第2驅動電路安裝於上述顯示 面板之相同邊上。 如請求項1之顯示裝置，其中 上述第1驅動電路、及上述第2驅動電路係驅動上述顯 示面板之源極線之源極驅動器。 一種電視系統，其特徵在於包含如請求項1之顯示裝 置0 143488.doc201030412 VII. Patent Application: A display device, comprising: a display panel; a first driving circuit for driving a driving circuit of the display panel, and having the defect of detecting the driving (four) road and repairing a self-detecting and self-repairing mechanism; and a second driving circuit that drives the driving circuit of the display panel and is different from the first driving circuit. See 2. Requests! In the display device, the second driving circuit drives the display panel when the self-detecting and self-healing mechanism detects and repairs the defect of the first driving circuit. 3. The display device of claim 1, wherein the first driving circuit comprises a plurality of output circuits, the output of which is used to drive an output signal of the display panel, and the beta self-detecting and self-repairing mechanism comprises determining the output circuit. If the determination result of the determination means is defective, the drive circuit is self-repaired by outputting the normal output signal to the display panel. 4. The display device according to claim 3, wherein said first driving circuit includes a preliminary output circuit that outputs said output signal to said display panel, J said self-detecting and self-healing mechanism includes a switching mechanism, said decision of said determining means If the result is a bad situation, the output signal from the above-mentioned 143488.doc 201030412 is a bad output circuit. 5. The output signal of the circuit is taken as upward: two is the board = display device of claim 4, where - output signal. The mechanism cuts the output signal from the above output circuit, = = = : circuit, and the signal is compared _ : whether the path is defective according to the comparison result of the comparison mechanism. Further, the control unit further includes an input signal of the preliminary output circuit, such as the display device of claim 5, for inputting to the output circuit and controlling the value, wherein the control unit has a different input size to the output circuit and the preliminary output circuit. And inputting a signal, and outputting a comparison judgment result corresponding to the input signal different in size from the comparison means, wherein the comparison result is different from the expected value, and determining that the output circuit is defective . 7. The display device of claim 4, wherein the determining means includes a comparing means for comparing output signals from the plurality of output circuits to the two output circuits, and determining the above based on the comparison result of the comparing means Is the output circuit defective? 8. The display device of claim 7, further comprising a control mechanism for controlling input signals of at least two of the plurality of round-trip circuits to be controlled, 143488.doc 201030412 9. The above-mentioned at least two 轮m # 夕 two round-out circuits input different sizes of input No. 15, and output the expected value of the comparison result from the comparison mechanism corresponding to the input signal of the same size. When the comparison result differs from the value of (4), the determination means determines that any of the at least two output circuits is defective. The display device of claim 5, wherein the output circuit has an operational amplifier as an output buffer, and the comparison mechanism comprises a comparison of the operational amplifiers. 11. 12. 13. 14. The display device of claim 9, The above operational amplifier operates as a voltage follower when driving the display panel. A display device according to claim 1, wherein said first driving circuit is mounted on a side of said display panel, and said second driving circuit is mounted on said display panel on a side opposite to a side on which said first driving circuit is mounted. The display device of claim 1, wherein the first driving circuit and the second driving circuit are mounted on the same side of the display panel. The display device of claim 1, wherein the first driving circuit and the second driving circuit drive a source driver of a source line of the display panel. A television system characterized by comprising the display device of claim 1 0 143488.doc
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JP6706954B2 (en) 2016-04-01 2020-06-10 三菱電機株式会社 Driver IC and liquid crystal display device
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GB9219836D0 (en) * 1992-09-18 1992-10-28 Philips Electronics Uk Ltd Electronic drive circuits for active matrix devices,and a method of self-tasting and programming such circuits
JPH06324651A (en) * 1992-10-19 1994-11-25 Fujitsu Ltd Driving circuit of liquid crystal display device
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