WO2010058836A1 - Display device and television system - Google Patents

Display device and television system Download PDF

Info

Publication number
WO2010058836A1
WO2010058836A1 PCT/JP2009/069697 JP2009069697W WO2010058836A1 WO 2010058836 A1 WO2010058836 A1 WO 2010058836A1 JP 2009069697 W JP2009069697 W JP 2009069697W WO 2010058836 A1 WO2010058836 A1 WO 2010058836A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
self
output
signal
display panel
Prior art date
Application number
PCT/JP2009/069697
Other languages
French (fr)
Japanese (ja)
Inventor
伸介 安西
好博 中谷
宏晃 藤野
裕文 松井
雅美 森
浩一 細川
利男 渡部
昌史 勝谷
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2010058836A1 publication Critical patent/WO2010058836A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
    • H04N17/045—Self-contained testing apparatus
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to a display device using a drive circuit that performs self-detection and self-repair of a defect in a DA converter output circuit.
  • FIG. 32 is a block diagram showing a configuration of a conventional semiconductor integrated circuit for driving a liquid crystal.
  • the liquid crystal driving semiconductor integrated circuit 101 shown in the figure can output m gray scale output voltages from n liquid crystal driving signal output terminals.
  • a liquid crystal driving semiconductor integrated circuit 101 includes an external clock input terminal 102, a gradation data input terminal 103 having a plurality of signal input terminals, a LOAD signal input terminal 104, and V0 terminals 105 and V1 terminals which are reference power supply terminals. 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109.
  • the liquid crystal driving semiconductor integrated circuit 101 includes n liquid crystal driving signal output terminals 111-1 to 111-n (hereinafter, the liquid crystal driving signal output terminals are referred to as signal output terminals. Terminals 111-1 to 111-n are collectively referred to as signal output terminal 111).
  • the liquid crystal driving semiconductor integrated circuit 101 includes a reference power correction circuit 121, a pointer shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 126 and an output buffer 127.
  • the pointer shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n.
  • the latch circuit unit 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n hold circuits 125-1 to 125-n.
  • the DAC circuit 126 is composed of n DAC circuits 126-1 to 126-n.
  • the output buffer 127 includes n output buffers 127-1 to 127-n, and each output buffer includes an operational amplifier.
  • the pointer shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-n based on the clock input signal input from the clock input terminal 102.
  • the latch circuit 124 selected by the pointer shift register circuit 123 stores the gradation output data from the gradation data input terminal 103.
  • the gradation output data corresponds to each latch circuit 124, in other words, corresponds to each signal output terminal 111 and is data synchronized with the clock input signal. Accordingly, each of the latch circuits 124-1 to 124-n can store gradation output data having different values corresponding to each signal output terminal 111.
  • the gradation output data stored in the latch circuits 124-1 to 124-n is transferred to the corresponding n number of hold circuits 125-1 to 125-n by the data LOAD signal. Further, the hold circuits 125-1 to 125-n output the gradation output data input from the latch circuits 124-1 to 124-n to the DAC circuits 126-1 to 126-n as digital data.
  • the DAC circuits 126-1 to 126-n select one voltage value among m kinds of gradation voltages based on the gradation output data from the hold circuit 125, and output buffers 127-1 to 127- output to n.
  • the DAC circuit 126 can output m types of gradation voltages depending on voltages input from the reference power supply terminal V0 terminal 105 to the V4 terminal 109.
  • the output buffer 127 buffers the gradation voltage from the DAC circuit 126 and outputs it as a liquid crystal panel drive signal to the signal output terminals 111-1 to 111-n.
  • the same number of shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 as the liquid crystal drive signal output terminals 111 are required, and the liquid crystal drive signal output terminals 111 are 1000 in number. If it is a terminal, 1000 of each of the circuits 124 to 127 is required.
  • the display driving semiconductor integrated circuit needs to give a signal of gradation voltage of R, G, B for each data line.
  • the number of outputs of one display driving semiconductor integrated circuit is 720, eight display driving semiconductor integrated circuits are required.
  • a semiconductor integrated circuit for display driving is tested at a wafer stage, is subjected to a shipping test after being packaged, and a display test is performed after being mounted on a liquid crystal panel. Furthermore, semiconductor integrated circuits that may cause initial failures are removed by screening tests such as burn-in and stress tests. Therefore, a display device on which a display driving semiconductor integrated circuit in which display failure occurs is not shipped to the market. However, a display defect rarely occurs while using the display device due to a very small defect or a foreign matter adhering and mixing that has not been determined to be defective during a pre-shipment test or a screening test.
  • the display defect occurrence rate is 57.6 ppm (57.6 / 1,000,000). That is, about one in about 17361 units will cause display defects, and the larger the size and the higher definition, the higher the rate of occurrence of display defects.
  • the display driving semiconductor integrated circuit is provided with a spare circuit provided for the defective circuit, and the defective circuit is switched to the spare circuit, so that the defect of the display driving semiconductor integrated circuit is eliminated. Avoidance is disclosed.
  • the display driving semiconductor integrated circuit includes a spare parallel circuit at each stage of the shift register, and performs a self-inspection of the shift register.
  • a technique for avoiding display defects caused by a defective shift register by selecting one having no defect is disclosed.
  • a selector is provided at the input and output of the DAC circuit, and the selector is switched based on the RAM information in which the position of the defective DAC circuit is stored, and a DAC circuit without a defect is selected. A method of using the same is disclosed.
  • Patent Document 1 and Patent Document 2 do not disclose any self-detection method for detecting a defect in an output circuit such as a DAC circuit.
  • Patent Document 3 discloses a technique for providing redundancy to a drive circuit of a product in which a drive circuit is integrated with a display panel and restoring the drive circuit even after the product is completed.
  • a spare output is provided for the drive output in the drive circuit, and one output of the drive output is compared with the spare output, and the output circuit determines whether the output values are equal.
  • the display panel is driven by a spare output circuit instead of the output circuit to be diagnosed during self-detection.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 6-208346 (published July 26, 1994)” Japanese Patent Publication “Japanese Patent Laid-Open No. 8-278771 (published on October 22, 1996)” Japanese Patent Gazette “Special Table 2004-511022 (April 8, 2004)”
  • the drive circuit to be diagnosed is separated from the display panel, the display panel is driven by the spare drive circuit, and the output of the spare drive circuit and the drive circuit to be diagnosed are The output is compared to determine whether the drive circuit to be diagnosed is good or bad.
  • image data representing an image to be displayed to the drive circuit to be diagnosed and the spare drive circuit an image is displayed on the display panel by the spare drive circuit, and the drive circuit to be diagnosed is also displayed.
  • Self-detection can be performed. That is, when the analog clamp voltage is selected and output as in the configuration of Patent Document 3, a part of the data is compared with the display data, so that the difference between the output circuits can be detected.
  • the data for comparing the output of the spare drive circuit and the output of the drive circuit to be diagnosed is limited to the image data to be displayed.
  • a DA converter circuit that outputs a voltage corresponding to the digital data is required.
  • a driver circuit for 256 gradation display requires a DA converter circuit that selects 256 voltages. Therefore, in order to detect a malfunction of the DA conversion circuit, it is necessary to compare all input data corresponding to 256 voltage outputs.
  • the present invention has been made in view of the above problems, and its object is to provide a display device provided with a drive circuit capable of self-detecting and self-repairing defects in an output circuit and an output block around the output circuit. It is an object of the present invention to provide a display device that performs self-detection and self-repair at an appropriate timing without disturbing viewing.
  • a display device is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected.
  • Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
  • the drive circuit drives the display panel.
  • the drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure.
  • the drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels.
  • Self-detection processing can be executed using the key data.
  • the image may be a still image or a moving image, that is, a video.
  • a self-detection / self-repair means performs the process which detects the defect of a drive circuit, when the image which should be displayed on the said display panel switches discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously. A process for detecting a circuit defect is executed. Further, for example, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM. A process for detecting a circuit defect is executed.
  • the self-detection process can be executed in a period that does not affect the display.
  • the display device according to the present invention executes a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the current display content is temporarily interrupted on the screen of the display device. Since the self-detection process is executed at the timing, the user does not feel uncomfortable. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
  • the display device includes a display panel, a supply period in which an image signal is supplied, and a supply stop period in which the supply of the image signal is stopped, among periods in which an image is displayed on the display panel.
  • Drive circuit for driving the display panel while switching between them, and having self-detection / self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected
  • the self-detecting / self-repairing means executes a process of detecting a defect of the driving circuit during the supply stop period.
  • the drive circuit switches between the supply period in which the image signal is supplied and the supply stop period in which the supply of the image signal is stopped, during the period in which the image is displayed on the display panel. While driving the display panel.
  • the drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure.
  • the drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels. Self-detection processing can be executed using the key data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit during the supply stop period.
  • the self-detecting / self-repairing unit executes processing for detecting a defect in the driving circuit in the horizontal scanning period and the vertical scanning period.
  • the display device According to the display device according to the present invention, it is possible to execute the self-detection process in a period in which the display device is driven and does not affect the display. That is, the display device according to the present invention performs a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the image signal is supplied to the display panel that is displaying an image. Since the self-detection process is executed at a timing that is not performed, driving of the display panel is not hindered. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
  • a display device is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected.
  • Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
  • the display device includes a display panel, a supply period in which an image signal is supplied, and a supply stop in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel.
  • the self-detecting / self-repairing means is characterized by executing a process of detecting a defect of the driving circuit during the supply stop period.
  • the display device According to the display device according to the present invention, at the timing when the content currently displayed on the screen of the display device is temporarily interrupted, or at the timing when the image signal is not supplied to the display panel displaying the image, Since the self-detection process is executed, it is possible to execute the self-detection and self-repair processes at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved.
  • FIG. 1 is a block diagram illustrating a configuration of a liquid crystal television according to an embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus based on one Embodiment of this invention. It is a figure which shows an example of a display when abnormality generate
  • a liquid crystal television it is a figure which shows a mode that self-detection and a self-repair operation
  • (c) is a figure which shows the mode after a channel change.
  • a liquid crystal television it is a figure which performs a mode that self-detection and a self-repair operation are performed at the time of CM shift
  • (a) is a diagram showing a state before CM shift
  • (b) is a state during a self-detection operation.
  • (c) is a figure which shows the mode in CM
  • (d) is a figure which shows the mode at the time of program resumption. It is a timing chart showing the signal for driving the display panel of a liquid crystal television.
  • FIG. 3 is a time chart according to an embodiment of the present invention, in which (a) to (f) are a scanning signal, a video signal, and a voltage value of a pixel electrode input to a display device according to an embodiment of the present invention.
  • FIG. It is a block diagram which shows the structure of the operation
  • Embodiment 1 A first embodiment of the present invention will be described below with reference to FIGS.
  • liquid crystal television 400 As a typical display device using a display driving circuit, a thin-screen television typified by a liquid crystal television can be given.
  • a liquid crystal television (liquid crystal display device) performs display by mounting a plurality of drive circuits created with a semiconductor integrated circuit (LSI) on a display panel.
  • LSI semiconductor integrated circuit
  • the user recognizes it as a direct display defect.
  • it is necessary to repair the defective part promptly, and it is desirable that the repair be completed in a short time at the place where the user is using if possible.
  • the present applicant has proposed a display driving circuit having a self-diagnosis self-repair function (self-detection and self-repair function) for a failure of the display drive circuit itself (for example, Japanese Patent Application No. 2008-130848, Application Nos. 2008-048640, Japanese Patent Application No. 2008-048639, and Japanese Patent Application No. 2008-054130: all unpublished at the time of confirmation prior to the filing of this application.
  • FIG. 1 shows a block diagram showing a configuration of a liquid crystal television 400 according to the present invention.
  • the liquid crystal television 400 includes a TFT-LCD module (display unit) 90 and a remote control I / F 401.
  • the display unit 90 includes source drivers (driving circuits, integrated circuits) 10a and 10b, a TFT-LCD panel (display panel) 80, a gate driver 99, and a controller 100.
  • the source driver 10a that is, the integrated circuits 10a and 10b is a display driving circuit having the above-described self-detection and self-repair functions.
  • the integrated circuits 10a and 10b that is, the generic names of the source drivers 10a and 10b are represented.
  • FIG. 2 is a block diagram illustrating a schematic configuration of the display unit 90.
  • the display unit 90 includes a display panel 80 and a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit or a source driver) that drives the display panel 80 based on gradation data input from the outside. ) 10.
  • the source driver that is, the integrated circuit 10 (driving circuit) includes a switching circuit 60 (self-detection / self-repairing means, switching means), a switching circuit 61 (self-detection / self-repairing means, switching means), and an output circuit block 30 (output).
  • the display panel 80 includes a pixel 70 to which the gradation voltage from the integrated circuit 10 is applied.
  • the display unit 90 has two basic operations as basic operations. Specifically, in the display unit 90, the integrated circuit 10 converts gradation data input from the outside into a gradation voltage (output signal), and displays an image on the display panel 80 based on the gradation voltage. A normal operation and a self-detection / repair operation in which the integrated circuit 10 detects whether or not the output circuit block 30 included in the integrated circuit 10 is defective and the output circuit block 30 is defective. It has two basic operations.
  • gradation data for operation confirmation is input to the output circuit block 30 and the spare output circuit block 40 from the outside via the switching circuit 61.
  • Each of the output circuit block 30 and the spare output circuit block 40 converts the input gradation data into a gradation voltage and outputs the gradation voltage to the comparison determination circuit.
  • the comparison determination circuit 50 compares the gradation voltage from the output circuit block with the gradation voltage from the standby output circuit block, and determines whether or not the output circuit block is defective based on the comparison result.
  • the comparison / determination circuit 50 outputs a determination result (failure detection information) indicating whether or not the output circuit block is defective to the switching circuit 61 and the switching circuit 60.
  • the switching circuit 61 switches the output destination of the gradation data from the outside based on the determination result from the comparison determination circuit 50.
  • the switching circuit 60 receives the gradation voltage from each of the output circuit block 30 and the spare output circuit block 40, and displays the display panel from the inputted gradation voltages based on the determination result from the comparison determination circuit.
  • the gradation voltage to be output to 80 is selected.
  • the switching circuit 61 when the determination result indicating that the output circuit block 30 is defective is input, the switching circuit 61 has the same level as the gradation data output to the output circuit block 30 determined to be defective. The tone data is also input to the spare output circuit block 40.
  • the switching circuit 60 when a determination result indicating that the output circuit block 30 is defective is input to the switching circuit 60, instead of the gradation voltage from the output circuit block 30 determined to be defective, the switching circuit 60 outputs from the standby output circuit 40. The gradation voltage is output to the display panel 80. As a result, even if the output circuit block 30 becomes defective, the integrated circuit 10 can output a normal gradation voltage to the display panel 80 using the spare output circuit block instead.
  • the integrated circuit 10 includes the comparison determination circuit 50, the switching circuit 60, and the switching circuit 61, so that it can detect its own defect and can self-repair itself. It becomes.
  • the integrated circuit 10 includes a self-healing circuit (self-repairing means) that detects its own fault and further self-heals the fault.
  • the configuration of the source driver 10, that is, the integrated circuit 10, and details of self-detection and self-repair operations will be described later.
  • FIG. 3 is a diagram illustrating an example of a display when an abnormality occurs in the output circuit block 30 included in the integrated circuit 10 included in the liquid crystal television 400. As shown in FIG. 3, when there is an abnormality in the output circuit block 30, a vertical line appears on the display.
  • the self-recovering operation is instantaneously executed by the self-recovery function of the display driving device so that the vertical stripe in FIG. 3 disappears.
  • FIG. 4 is a diagram showing how the liquid crystal television 400 performs self-detection and self-repair operations when a channel is changed.
  • FIG. 4A is a diagram showing a state before the channel is changed.
  • FIG. 4B is a diagram showing a state during the self-detection operation, and
  • FIG. 4C is a diagram showing a state after the channel change.
  • the liquid crystal television 400 when the user performs a channel change operation using the remote controller 402, a channel selection input signal is received via the remote control I / F 401, the channel selection input signal is converted into a channel selection voltage, and a tuner ( Broadcast receiving means).
  • the tuner receives a broadcast signal of a channel corresponding to the channel selection voltage. Then, the liquid crystal television 400 displays the program of the channel received by the tuner.
  • the liquid crystal television 400 first receives and displays a 1ch (one channel) program as shown in FIG.
  • the liquid crystal television 400 starts a self-detecting operation.
  • the display on the screen disappears as shown in FIG.
  • the self-detection of the source driver 10 is performed when the channel is switched from 1ch to 2ch, that is, when the display based on the image signal representing the 1ch program is interrupted.
  • the controller 100 shown in FIG. 1 senses the user's channel selection operation, that is, switching from 1ch to 2ch.
  • the controller 100 image switching means
  • the controller 100 When the controller 100 senses channel switching, it instructs the source driver 10 to execute self-detection processing, and the source driver 10 executes self-detection processing. That is, in the liquid crystal television 400, in order to switch from display based on an image signal representing a 1ch program on the display panel 80 to display based on an image signal representing a 2ch program, an image signal representing a 1ch program is displayed. When the display based on is interrupted, the self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 instructs the source driver 10 to perform self-detection processing based on a channel selection input signal input via the remote control I / F.
  • FIG. 4 shows an example of channel switching from 1ch to 2ch.
  • the display based on the image signal representing the 1ch program is temporarily interrupted.
  • the source driver 10 executes self-detection processing in accordance with an instruction from the controller 100 based on the channel selection input signal, for example.
  • the liquid crystal television 400 is a digital television
  • the video signal and audio signal are encoded and transmitted as a digital broadcast wave, so that the compressed video signal and audio signal included in the received digital broadcast wave are decoded.
  • the program of the designated channel is not displayed immediately, but is displayed for a short period of time. Is displayed. Therefore, if self-detection is performed at this timing, the user does not feel uncomfortable. That is, the liquid crystal television 400 completes self-detection in a period that does not affect the display.
  • the liquid crystal television 400 displays the switched program, that is, the 2ch program, as shown in FIG.
  • FIG. 5 is a diagram illustrating a state in which the liquid crystal television 400 performs self-detection and self-repair operations during the transition to CM.
  • FIG. 5A illustrates a state before the transition to CM.
  • FIG. 5B is a diagram showing a state during the self-detection operation
  • FIG. 5C is a diagram showing a state during the CM
  • FIG. 5D is a diagram showing a state when the program is resumed.
  • the liquid crystal television 400 first receives a 1ch broadcast and displays a program included in the 1ch broadcast, as shown in FIG.
  • the liquid crystal television 400 starts a self-detection operation.
  • the display on the screen disappears as shown in FIG.
  • the self-detection of the source driver 10 is performed at the time of transition from the program to the CM, that is, when the display based on the image signal representing the program is interrupted.
  • the controller 100 shown in FIG. 1 senses a transition from a program to a CM.
  • the controller 100 image switching means
  • the source driver 10 is instructed to execute the self-detection process, and the source driver 10 executes the self-detection process. That is, in the liquid crystal television 400, when the display based on the image signal representing the program is interrupted on the display panel 80 in order to shift from the display based on the image signal representing the program to the display based on the image signal representing the CM.
  • the self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 performs scene detection, detects a CM based on the result, and instructs the source driver 10 to perform self-detection processing.
  • Scene detection is a function that detects not only silence and stereo / monaural audio, but also “sound switching” such as the boundary between music and conversation and “video switching” with large scene changes.
  • Scene detection is a technique used when, for example, a CM part is chapter-divided by a hard disk decoder or the like.
  • the liquid crystal television 400 displays a CM as shown in FIG. Thereafter, in the liquid crystal television 400, as shown in FIG. 4D, the program is resumed, and the display shifts from the CM to the program.
  • the self-detection process may include a plurality of steps.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one channel switching.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one transition from a program to a CM.
  • the process may be divided and all the processes included in the self-detection process may be completed by changing the channel several times.
  • the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one channel switching.
  • the time of the self-detection process executed at the time of one channel change can be shortened, and a situation in which the period during which screen display is not performed after the channel switching operation becomes too long can be avoided.
  • the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one transition from the program to the CM. .
  • the process included in the self-repair process is divided into n process groups
  • the process of one process group that is, 1 / n of the self-detection process is performed in one channel switching.
  • processing of n process groups that is, all processes of self-detection are completed.
  • the process included in the self-repair process is divided into n process groups
  • the process of one process group that is, 1/1 of the self-detection process is performed in switching from one program to CM. n.
  • the process of n process groups that is, all processes of self-detection are completed by shifting to CM for n times.
  • the self-detection process includes a plurality of steps, details will be described later.
  • one gradation data is obtained.
  • steps for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit
  • several types of processes are performed for all the gradation data.
  • such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is performed for each channel switching. And the self-detection process for one gradation is completed by switching the channel twice.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each CM transition, and one gradation is obtained by two CM transitions.
  • the self-detection process may be completed.
  • the process which comprises each process group may be preset, and the structure by which the setting information is memorize
  • the source driver 10 when executing the self-detection process, the source driver 10 reads the setting information from the memory, and executes the process group process one by one for each channel switching.
  • the number of processes constituting each process group may be set in advance, and the source driver 10 may be configured to execute the set number of processes for each channel switching.
  • the display panel 80 shown in FIG. 1 constitutes the display unit 90 together with the controller 100, the gate driver 99, and the source dry 10.
  • the display panel 80 has a plurality of gate lines (scanning signal lines) and a plurality of source lines (data signal lines) orthogonal to the gate lines, and at the intersections of these gate lines and source lines, respectively.
  • a pixel portion including a switching element and a liquid crystal capacitor is provided. That is, in the display panel 80, the pixel portions are arranged in a matrix.
  • a gate line is connected to the gate terminal, a source line is connected to the source terminal, and a pixel electrical connection is connected to the drain terminal.
  • a common counter electrode is provided in all the pixel formation portions so as to face the pixel electrode, and the pixel electrode and the counter electrode form a liquid crystal capacitor with a liquid crystal layer interposed therebetween.
  • the pixel electrode is given a potential according to the image to be displayed by the source line and the gate line, and a predetermined potential is given to the common electrode. By applying this voltage, the amount of light transmitted to the liquid crystal layer is controlled, whereby image display is performed. Note that a deflection plate may be used to control the amount of light transmitted by applying a voltage to the liquid crystal layer.
  • FIG. 6 is a timing chart showing signals for driving the display panel 80 of the liquid crystal television 400.
  • Various control signals shown in FIG. 6 are supplied to the controller 100.
  • the controller 100 controls the gate driver 99 and the source driver 10 based on the control signal shown in FIG.
  • the gate driver 99 and the source driver 10 supply a gate signal and a data signal to the display panel 80. Thereby, the display panel 80 is driven.
  • a period 501 is a vertical period
  • a period 502 is a vertical data valid period
  • a period 503 is a vertical blanking period
  • a period 504 is a horizontal period
  • a period 505 is a horizontal data valid period
  • a period 506 is a horizontal blanking period.
  • a period 507 is a vertical effective data start period indicating a period from the input of the vertical synchronization signal to the start of effective data
  • a period 508 is a horizontal effective data indicating a period from the input of the horizontal synchronization signal to the start of effective data. Indicates the data start period.
  • the gate lines are sequentially selected by the gate driver 99 based on the horizontal synchronization signal and supplied with the scanning signal. Then, the gate of the switching element connected to the gate line to which the scanning signal is supplied is turned ON, and an active state in which a data signal can be supplied to the pixel electrode connected to the switching element is obtained. As a result, a data signal is supplied to the pixel electrode from the source driver 10 via the source line, and a voltage representing an image is supplied.
  • a data signal is sequentially supplied from the left pixel to the right pixel for each line of the screen to form a scanning line.
  • the blanking period that is, the blanking period is the time for the scanning line that has scanned the screen to return to the original state.
  • the horizontal blanking period 506 is a time for scanning from left to right in one line of the screen and then returning to the left again.
  • the vertical blanking period 503 is performed while scanning from left to right sequentially from the upper left in all lines of the screen. This is the time from scanning to the lower right until returning to the upper left again.
  • the control signal period shown in FIG. 6 varies depending on the standard of the panel to be driven, the driving method, and the like, as an example, the vertical blanking period is 1.14 ms and the horizontal blanking period is 9 ⁇ s.
  • the data line is not driven, and no data signal is supplied to each pixel constituting the display panel 80.
  • image data is not written to each pixel during these periods, even if the output of the source driver 10 that is a display driving element is high impedance, it does not affect image display. Therefore, in the liquid crystal television 400, the source driver 10 is self-detected and self-repaired using these periods.
  • the controller 100 shown in FIG. 1 senses the horizontal blanking period 506 or the vertical blanking period 503 in response to the supply of the control signal shown in FIG.
  • controller 100 (period switching detection means) senses the horizontal blanking period 506 or the vertical blanking period 503
  • the controller 100 instructs the source driver 10 to execute self-detection processing, and the source driver 10 performs self-detection processing. Execute.
  • self-detection and self-repair are performed in real time because repair is performed for each line.
  • self-detection / self-repair is performed during the vertical blanking period 503 since the repair is performed for each screen, it can be said that self-detection / self-repair is performed in real time. That is, according to the liquid crystal television 400, the self-detection process can be executed in real time without disturbing the viewing of the user.
  • the controller 100 In the vertical blanking period 503, other information such as teletext may be supplied to the controller 100 or the like, but self-detection and self-restoration can be performed by the display driver, that is, the source driver 10 alone. Regardless of other devices such as the controller 100, self-detection and self-repair operations are possible.
  • the vertical blanking period is also called the vertical blanking period.
  • An example of self-detection in the vertical blanking period will be described later again.
  • the self-repairing process may include a plurality of steps.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one horizontal blanking period 506.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one vertical blanking period 503.
  • the self-repair process is divided into a plurality of process groups including one or more processes, and the process groups are executed one by one in one horizontal blanking period 506 or vertical blanking period 503. May be.
  • the time of the self-detection process executed in one horizontal blanking period 506 or the vertical blanking period 503 is shortened, and the period during which the screen display is not performed after the channel switching operation becomes too long. Can avoid the situation.
  • n horizontal blanking period 506 or vertical blanking period 503 the process of one process group, that is, the self-detection process. Of 1 / n. Then, in n horizontal blanking periods 506 or vertical blanking periods 503, processing of n process groups, that is, all processes of self-detection are completed.
  • the self-detection process includes a plurality of steps, details will be described later.
  • one gradation data is obtained.
  • steps for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit
  • several types of processes are performed for all the gradation data.
  • such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process is performed for each horizontal blanking period 506.
  • the group processing is executed, and the self-detection processing for one gradation can be completed by two horizontal blanking periods 506.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each vertical blanking 503, and the vertical blanking 503 is performed twice.
  • the self-detection process for one gradation may be completed.
  • the configuration of the source driver 10a according to the present invention will be described with reference to FIG.
  • the spare source driver 10b can have a simpler configuration than the source driver 10a, but can also have the same configuration as the source driver 10a.
  • a circuit capable of performing self-detection and self-recovery operations similar to those of the source driver 10a will be referred to as an integrated circuit 10 and will be described.
  • FIG. 7 is an explanatory diagram showing the configuration of the integrated circuit 10 (drive circuit).
  • the integrated circuit 10 includes n liquid crystal driving signal output terminals OUT1 to OUTn (hereinafter referred to as output terminals OUT1 to OUTn) via a data bus from a grayscale data input terminal (not shown).
  • N sampling circuits 6-1 to 6-n hereinafter collectively referred to as sampling circuit 6
  • n hold circuits 7-1 to 7-n hereinafter collectively referred to as a hold circuit 7
  • n DAC circuits 8-1 to 8-n hereinafter collectively referred to as “hold circuit 7” that convert gradation data into gradation voltage signals.
  • DAC circuit 8 n operational amplifiers 1-1 to 1-n (hereinafter collectively referred to as operational amplifier 1) having a role of a buffer circuit for the gradation voltage signal from the DAC circuit 8, n judgment circuits 3-1 3-n (hereinafter collectively referred to as determination circuit 3), n determination flags 4-1 to 4-n (hereinafter collectively referred to as determination flag 4), n number of determination flags Pull-up / pull-down circuits 5-1 to 5-n (hereinafter collectively referred to as pull-up / pull-down circuits 5) are provided.
  • the integrated circuit 10 includes a plurality of switches 2 a that are turned on and off by a test signal, a plurality of switches 2 b that are turned on and off by a test B signal, and an output signal from the determination flag 4.
  • switches 2c connection switching means
  • 2d connection switching means
  • the switches 2a, 2b, and 2d are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned off when an “H” signal is inputted, and is turned on when an “H” signal is inputted.
  • the integrated circuit 10 includes a spare sampling circuit 26, a spare hold circuit 27, a spare DAC circuit 28 (spare output circuit), and a spare operational amplifier 21, one for each circuit.
  • the sampling circuit 6, the hold circuit 7, and the DAC circuit 8 correspond to the output circuit block 30 shown in FIG. 2, and the sampling circuit 26, the hold circuit 27, and the DAC circuit 28 are shown in FIG.
  • the operational amplifier 1, the determination circuit 3, and the determination flag 4 correspond to the preliminary circuit block 40 shown, the comparison determination circuit 50 shown in FIG. 2, and the switches 2d and 2c connected to the output terminals OUT1 to OUTn. 2 corresponds to the switching circuit 60 shown in FIG. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in FIG.
  • the integrated circuit 10 shown in FIG. 7 is connected to the display panel 80 shown in FIG. 2 via output terminals OUT1 to OUTn, and the display panel 80 is not shown in FIG.
  • the test signal is “L” and the test B signal is “H”.
  • the switch 2a is turned off and the switch 2b is turned on.
  • the corresponding sampling circuits 6 input STR1 to STRn signals (hereinafter collectively referred to as STR signals), which are signals from a pointer shift register (not shown).
  • STR signals are signals from a pointer shift register (not shown).
  • the sampling circuit 6 acquires gradation data corresponding to itself from the gradation data input terminal via the data bus.
  • the hold circuit 7 inputs the gradation data acquired by the sampling circuit 6 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 (output circuit) inputs gradation data from the hold circuit 7.
  • the DAC circuit 8 converts the input gradation data into a gradation voltage signal, and outputs the gradation voltage signal to the positive input terminal of the operational amplifier 1 (comparing means).
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 serves as a buffer circuit for the grayscale voltage from the DAC circuit 8, and the grayscale voltage signal input to its positive input terminal is used as the corresponding output terminals OUT1 to OUTn. Output to.
  • the switch 2c is ON and the switch 2d is OFF. The operation of the switches 2c and 2d will be described later.
  • the output circuit block has gradation
  • An object of the present invention is to convert gradation data input from a data input terminal into a gradation voltage for driving the display panel 80, and to output the converted gradation voltage to the display panel 80 via an output terminal.
  • test signal and the test B signal are output from a control circuit (not shown) that controls switching of the operation check test and operation of the operation check test.
  • the control circuit is also a circuit for controlling gradation data and a data LOAD signal input via the data bus in the operation check test. Further, the control circuit may be the same as or different from the control circuit that controls the gradation data, the data LOAD signal, and the shift clock input signal during normal operation.
  • FIG. 8 is a flowchart showing a first procedure of the operation check test according to the first embodiment.
  • step S21 (hereinafter abbreviated as S21) shown in the figure, the test signal is set to “H” and the test B signal is set to “L”.
  • the operational amplifier 1 serves as a comparator by S21.
  • a counter m provided in a control circuit (not shown) is initialized to zero. Further, the control circuit activates the gradation data corresponding to the value of the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR1 signal, and the spare sampling circuit 26 via the data bus. To store. Further, the control circuit samples the gradation data of gradation m + 1 obtained by adding 1 to the value of the counter m, the gradation data of gradation 1 here, the TSTR2 signal active, and the data via the data bus. Store in circuit 6. Next, the spare hold circuit 27 acquires gradation data of gradation 0 from the sampling circuit 26 based on the data LOAD signal.
  • the DAC circuit 28 receives the gradation data from the hold circuit 27 and outputs a gradation voltage of gradation 0 to the negative input terminal of the operational amplifier 1 (S23).
  • the hold circuit 7 acquires gradation data of gradation 1 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 inputs gradation data from the hold circuit 7.
  • Each DAC circuit 8 outputs a gradation voltage of gradation 1 to the positive input terminal of each operational amplifier 1 connected in series with itself (S23).
  • the integrated circuit 10 of the present invention outputs an n gradation voltage, the gradation voltage of gradation 0 is the lowest voltage value, and the gradation voltage of gradation n is the lowest. It is assumed that the voltage value is high.
  • the operational amplifier 1 compares the gradation voltage from the DAC circuit 8 input to the positive input terminal and the gradation voltage from the DAC circuit 28 input to the negative input terminal (S24). Specifically, the operational amplifier 1 inputs a gradation voltage of gradation 1 to its own positive input terminal, and inputs a gradation voltage of gradation 0 to its own negative input terminal. If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs an “H” level signal. Here, if the output of the operational amplifier is an “L” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 (determination means) receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. Note that the expected value stored by the determination circuit 3 is given by the control circuit. In this operation check test 1, the determination circuit 3 stores the expected value as the “H” level.
  • the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is at the “H” level, which is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “L” level, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory. (S25) The determination circuit 3 receives the output signal from the operational amplifier 1 and outputs an “L” flag to the determination flag 4 if the input signal is “H” level, and the input signal is “L” level.
  • the configuration may be such that the “H” flag is output to the determination flag 4.
  • the determination flag 4 holds the “H” flag even if the “L” flag is input from the determination circuit 3 thereafter. Continue.
  • the subsequent determination operation may not be performed.
  • n is the number of gradations that the integrated circuit 10 can output.
  • FIG. 9 is a flowchart showing a second procedure of the operation check test according to the first embodiment.
  • the determination circuit 3 outputs an “L” flag indicating normality.
  • the operation check test 2 is performed by inputting a gradation voltage lower than that of the negative input terminal to the positive input terminal of the operational amplifier 1.
  • the control circuit activates the TSTR1 signal for the gradation data of gradation m + 1, in this case, the gradation data of gradation m + 1 by adding 1 to the value of the counter m, and reserves the data via the data bus. Is stored in the sampling circuit 26.
  • the control circuit activates the gradation data corresponding to the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR2 signal to the sampling circuit 6 via the data bus. Store.
  • the DAC circuit 28 inputs the gradation data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 outputs the gradation voltage of gradation m + 1 corresponding to the inputted gradation data, here, the gradation voltage of gradation 1 to the negative input terminal of the operational amplifier 1.
  • the DAC circuit 8 inputs the gradation data stored by the sampling circuit 6 via the hold circuit 7. Further, each DAC circuit 8 has a gradation voltage of gradation m corresponding to the inputted gradation data, here a gradation voltage of gradation 0, of each operational amplifier 1 connected in series to itself. Output to the positive input terminal (S32).
  • the operational amplifier 1 compares the gradation voltage of gradation 0 from the DAC circuit 8 input to the positive input terminal with the gradation voltage of gradation 1 from the DAC circuit 28 input to the negative input terminal. (S33). If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs a signal of the “L” flag. Here, if the output of the operational amplifier is an “H” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. In this operation check test 1, the determination circuit 3 stores the expected value as the “L” level. Here, the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is the “L” level that is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “H”, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory (S34). The above steps S33 to S34 are repeated until the value of m becomes n ⁇ 1 (S35, S36).
  • FIG. 10 is a flowchart showing a third procedure of the operation check test according to the first embodiment.
  • the operational amplifier 1 when there is a problem that the output is open, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 by the executed confirmation test, and the malfunction is confirmed in the operation confirmation tests 1 and 2. It may not be detected.
  • the operation check test 3 a pull-down circuit is connected to the positive input terminal of the operational amplifier 1.
  • a low voltage is input to the positive input terminal of the operational amplifier 1.
  • the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 according to the executed confirmation test. Can be prevented.
  • the specific procedure of the operation check test 3 is as follows. First, the counter m is initialized to 0 (S41). Next, the pull-up / pull-down circuit 5 pulls down the positive input terminal of the operational amplifier 1 (S42). Steps S43 to S47 from here are the same as the steps S23 to S27 of the operation check test 1 already described above, and the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling down the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 1, the operational amplifier 1 outputs the “L” level signal. Will be output. As a result, the determination circuit 3 determines from the inputted “L” level signal that the DAC circuit 8 is defective, and the determination flag 4 stores the “H” flag.
  • FIG. 11 is a flowchart showing a fourth procedure of the operation check test according to the first embodiment.
  • the operation check test 4 is for dealing with a problem that the output of the DAC circuit 8 is open.
  • the counter m is initialized to 0 (S51).
  • the pull-up / pull-down circuit 5 pulls up the positive input terminal of the operational amplifier 1 (S52).
  • the subsequent steps S53 to S57 are the same as the steps S32 to S36 of the operation check test 2 already described above, and therefore the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling up the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 2, the operational amplifier 1 outputs the “H” level signal. Will be output. As a result, the determination circuit 3 determines that the DAC circuit 8 has a problem from the input “H” level signal, and the determination flag 4 stores “H”.
  • FIG. 12 is a flowchart showing the fifth procedure of the operation check test according to the first embodiment.
  • the DAC circuit 8 there may be a problem that two adjacent gradations in itself are short-circuited. As described above, when two adjacent gradations are short-circuited, the DAC circuit 8 outputs an intermediate voltage between the two short-circuited gradations. In the case of this defect, the gradation voltage output from the DAC circuit 8 does not cause a voltage shift of one gradation or more compared to a normal case. Therefore, this malfunction cannot be detected in the operation confirmation tests 1 to 4.
  • the purpose of the operation check test 5 is to detect a problem in which the two adjacent gradations in the DAC circuit 8 are short-circuited.
  • the counter m is initialized to 0 (S61).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m and here gradation data of gradation 0 are input to sampling circuit 26 and sampling circuit 6 via a data bus.
  • the DAC circuits 28 and 8 acquire gradation data of gradation 0 from the sampling circuits 26 and 6 via the hold circuits 27 and 7. Further, the DAC circuits 28 and 8 output a gradation voltage of gradation 0 to the positive input terminal and the negative input terminal of the operational amplifier 1 (S62).
  • the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited by a switch (not shown). If it is determined in the operation check tests 1 and 2 that the DAC circuit 8 is not defective, the difference between the gradation voltages input to the positive input terminal and the negative input terminal is equal to or greater than one gradation. There is no voltage difference. Therefore, there is no problem that a large current flows by short-circuiting the positive input terminal and the negative input terminal.
  • the two input terminals of the operational amplifier 1 input the same gradation voltage.
  • the operational amplifier 1 since the operational amplifier 1 originally has an input / output offset voltage, the output of the operational amplifier 1 is “H” or “L” even if the same gradation voltage is input to its two input terminals. Either of these will be output.
  • the determination circuit 3 stores the output level of the operational amplifier 1 when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S63).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the gradation voltage of gradation 0 from the DAC circuit 8 is input to the positive input terminal of the operational amplifier 1
  • the gradation voltage of gradation 0 from the DAC circuit 28 is input to the negative input terminal. Is done.
  • the determination circuit 3 compares the output from the operational amplifier 1 with the expected value stored by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs the “H” flag to the determination flag 4 (S65).
  • the gradation voltage from the DAC circuit 28 is input to the positive input terminal of the operational amplifier 1 and the gradation voltage from the DAC circuit 8 is input to the negative input terminal by a switch (not shown).
  • the input is switched (S66).
  • the same processing as S64 is performed (S67).
  • the determination circuit 3 if the output from the operational amplifier 1 is different from the expected value stored in the determination circuit 3, the determination circuit 3 outputs an “H” flag to the determination flag 4 (S68). In this way, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the expected value stored in the determination circuit 3 is either the “H” level or the “L” level, the problem of the DAC circuit 8 is prevented. It can be detected.
  • FIG. 13 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuit 28 and performing self-repair.
  • the determination circuit 3 determines that the DAC circuit 8 is defective, the determination circuit 3 outputs an “H” flag to the determination flag 4. Further, the determination flag 4 receives the “H” flag from the determination circuit 3 and stores it in the inside thereof.
  • the control circuit detects whether or not the determination flag 4 records “H” (S71). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S75. On the other hand, when the control circuit detects that the determination flag 4 stores “H”, the control circuit checks the number of “H” flags stored in each of the determination flags 4-1 to 4-n. Here, when the number of “H” flags stored in the determination flag 4 is plural, the process proceeds to S73. On the other hand, when the number of “H” flags stored in the determination flag 4 is one, the process proceeds to S74 (S72).
  • Judgment flag 4-1 outputs an output signal of Flag1 which becomes “H” level to the switches 2c and 2d.
  • the switch 2c to which the “H” level signal is input is turned OFF and the switch 2d is turned ON by the output signal of Flag1.
  • the switch 2c cuts off the connection between the output from the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1.
  • the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit 26.
  • the gradation data corresponding to the liquid crystal driving signal output terminal OUT1 also stores the sampling circuit 26.
  • the switch 2d connects the output of the operational amplifier 21 and the liquid crystal driving signal output terminal OUT1.
  • the switches 2c and 2d are switched by the output signal of Flag1 from the determination flag 4-1, so that the defective DAC circuit 8-1 is switched to the spare DAC circuit 28.
  • the integrated circuit 10 can switch the defective DAC circuit to the spare DAC circuit 28 by performing the operation check tests 1 to 5 and the self-repair process. Further, in the first embodiment, a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28 are provided. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 14 is a flowchart showing a processing procedure from when the display device is turned on until the operation check test is performed and the normal operation is started.
  • FIG. 15 is an explanatory diagram showing a configuration of the operational amplifier 1 and peripheral circuits for confirming the operation of the operational amplifier 1.
  • the positive input terminal of the operational amplifier 1 is connected to a switch S5 for switching input between an output from the DAC circuit 8 and a predetermined voltage. Further, a switch S3 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S5. On the other hand, the negative input terminal of the operational amplifier 1 is connected to a switch S6 for switching input between an output of the operational amplifier 1 for performing negative feedback from the operational amplifier 1 and a predetermined voltage. Further, a switch S4 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S4.
  • the operational amplifier 1 operates as a voltage follower circuit by setting the switch S5 to the A side (output side of the DAC circuit 8) and the switch S6 to the A side.
  • the switches S1 and S2 are switched to the B side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 operates as a comparator.
  • the switches S3 and S4 are switched to the A side.
  • Vref1 is input to the positive input terminal of the operational amplifier 1
  • Vref2 is input to the negative input terminal.
  • Vref1 and Vref2 are voltages generated in advance, and the voltage value of Vref1 is larger than the voltage value of Vref2.
  • the difference in voltage value between Vref1 and Vref2 is set to a value larger than the input / output offset value of the operational amplifier 1.
  • the operational amplifier 1 outputs a signal of “H” level because the voltage of Vref1 input to the positive input terminal is higher than Vref2 input to the negative input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “H” stored by itself. Here, when the output of the operational amplifier 1 is at the “L” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the expected value stored by the determination circuit 3 is given by the control circuit.
  • the switches S3 and S4 are switched to the B side, Vref2 is input to the positive input terminal of the operational amplifier 1, and Vref1 is input to the negative input terminal.
  • the operational amplifier 1 outputs the “L” level because the voltage value of Vref1 input to the negative input terminal is higher than Vref2 input to the positive input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “L” stored by itself. Here, when the output of the operational amplifier 1 is at the “H” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the switches S3 to S6 are switched by the control circuit.
  • the operational amplifier 1 compares the output of the DAC circuit 8 with the output of the spare DAC circuit 28.
  • two adjacent DAC circuits 8 are set as one set, and the outputs from the DAC circuits 8 are compared in the operational amplifier 1.
  • FIG. 16 is an explanatory diagram showing the configuration of the integrated circuit 20 (integrated circuit for driving the display device).
  • the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier 1 to its positive input terminal. Furthermore, the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier adjacent to the operational amplifier 1 to its negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8-1 to its positive input terminal, and outputs the output from the DAC circuit 8-2. It inputs to its own negative input terminal via the switch 2a. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8-2 to its own positive input terminal, and outputs the output from the DAC circuit 8-1 through its switch 2a to its own negative input terminal. To enter.
  • the integrated circuit 20 also includes spare sampling circuits 26A and 26B, spare hold circuits 27A and 27B, spare DAC circuits 28A and 28B, operational amplifiers 21A and 21B, and pull-up / pull-down circuits 25A and 25B.
  • the output from the DAC circuit 28A is input to its own positive input terminal, and the output from the DAC circuit 28B is input to its own negative input terminal via the switch 2a.
  • the output from the DAC circuit 28B is input to its own positive input terminal, and the output from the DAC circuit 28A is input to its own negative input terminal via the switch 2a.
  • the control circuit sets the test signal to the “L” level and the test B signal to the “H” level.
  • the DAC circuit 8 converts the grayscale data input from the hold circuit 7 into a grayscale voltage signal and outputs the grayscale voltage to the positive input terminal of the operational amplifier 1.
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 buffers the gradation voltage from the DAC circuit 8 and outputs it to the corresponding output terminals OUT1 to OUTn.
  • the control circuit sets the test signal to the “H” level and sets the test B signal to the “L” level.
  • the switch 2a is turned ON, the TSTR1 signal is sent to the sampling circuit 26A and the odd-numbered sampling circuits 6 (sampling circuits 6-1, 6-3,..., 6- (n ⁇ 1)). Entered. Further, the TSTR2 signal is input to the sampling circuit 26B and the even-numbered sampling circuits 6 (sampling circuits 6-2, 6-3,..., 6-n).
  • the switch 2a when the switch 2a is turned ON, the output from the adjacent even-numbered DAC circuit 8 is input to the negative-polarity input terminal of the odd-numbered operational amplifier 1, and the negative-polarity input terminal of the even-numbered operational amplifier 1 is input. Are supplied with outputs from adjacent odd-numbered DAC circuits 8. Further, when the test B signal becomes “L” level, the switch 2b is turned OFF. As a result, negative feedback of the output of the operational amplifier 1 to the negative input terminal is cut off. As a result, the operational amplifier 1 becomes a comparator that compares the output from the DAC circuit 8 connected in series with the operational amplifier 1 with the output from the adjacent DAC circuit 8.
  • FIG. 17 is a flowchart showing a first procedure of the operation check test according to the second embodiment.
  • the control circuit sets the test signal to the “H” level and the test B signal to the “L” level (S101). As a result, the operational amplifier 1 operates as a comparator (S102). Next, the control circuit sets the expected value of the odd-numbered determination circuit 3 (determination circuits 3-1, 3-3,..., 3- (n ⁇ 1)) to the “L” level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuit 3 (determination circuits 3-2, 3-4,..., 3-n) to the “H” level.
  • control circuit initializes a counter m included in the control circuit to 0 (S103). Further, the control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m through the data bus. In addition, the control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m + 1 through the data bus (S104).
  • the odd-numbered operational amplifier 1 has an odd-numbered DAC in which a gradation voltage of gradation 0 is connected in series to its positive polarity input terminal. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from its adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 becomes “L”.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent odd-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “H”.
  • the determination circuit 3 determines whether the level of the output signal from the operational amplifier 1 matches the expected value stored by itself (S105).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 (S106).
  • the above processing from S104 to S106 is repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S107, S108).
  • FIG. 18 is a flowchart showing a second procedure of the operation check test according to the second embodiment.
  • the operation check test 2 in the second embodiment is an operation check in which the voltage relationship of the odd-numbered and even-numbered gradations is reversed in the operation check test 1 in the second embodiment. This is the same as the operation check test in the embodiment.
  • control circuit sets the expected value of the odd-numbered determination circuit 3 to “H”, while setting the expected value of the even-numbered determination circuit 3 to “L”. Further, the control circuit initializes a counter m included in the control circuit to 0 (S111).
  • control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m + 1 via the data bus.
  • control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m via the data bus (S112).
  • the odd-numbered operational amplifier 1 is connected to the positive-polarity input terminal of the grayscale voltage of grayscale 1 in series with the odd-numbered DAC. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the output of the odd-numbered operational amplifier 1 becomes “H” level.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from the adjacent odd-numbered DAC circuit 8 to its negative polarity input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “L” level.
  • the determination circuit 3 compares the level of the output from the operational amplifier 1 with the expected value stored in itself (S113).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value.
  • the above processes of S112 to S114 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S115, S116).
  • FIG. 19 is a flowchart showing a third procedure of the operation check test according to the second embodiment.
  • the gradation voltage input to the operational amplifier 1 by the executed check test is used as the operational amplifier. 1 may continue to be held, and in the operation check tests 1 and 2 of the second embodiment, there may be a case where a failure cannot be detected.
  • the control circuit initializes the value of the counter m included therein to 0 (S121).
  • the pull-up / pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8.
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled down (S122).
  • the output of the even-numbered DAC circuit 8 is open, a low voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 20 is a flowchart showing a fourth procedure of the operation check test according to the second embodiment.
  • the control circuit initializes the value of the counter m included in the control circuit to 0 (S131).
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull down the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled up (S122).
  • the output of the even-numbered DAC circuit 8 is open, a high voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 21 is a flowchart showing a fifth procedure of the operation check test according to the second embodiment.
  • the DAC circuit 8 may have a problem that two adjacent gray scales in itself are short-circuited.
  • the purpose of the operation check test 5 of the second embodiment is to detect such a problem.
  • the control circuit initializes the value of the counter m included in itself to 0 (S141).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 through the data bus.
  • the odd-numbered DAC circuit 8 and the even-numbered DAC circuit 8 output the gradation voltage of the same gradation m (S142).
  • the control circuit short-circuits the positive input terminal and the negative input terminal of the operational amplifier 1 through a switch (not shown).
  • the determination circuit 3 stores the output level of the operational amplifier when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S143).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the positive polarity input terminal of the odd-numbered operational amplifier 1 is input with the grayscale voltage of grayscale m from the odd-numbered DAC circuit 8 connected in series to itself, Are supplied with the gradation voltage of gradation m from the even-numbered DAC circuit 8 adjacent thereto.
  • the gradation input of the gradation m from the even-numbered DAC circuit 8 connected in series to the positive-polarity input terminal of the even-numbered operational amplifier 1 is input to the negative-polarity input terminal.
  • the gradation voltage of gradation m from the adjacent odd-numbered DAC circuit 8 is input.
  • the determination circuit 3 compares the expected value stored by itself with the output from the operational amplifier 1 (S144). Further, the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value stored by itself. Further, the determination flag 4 stores therein the “H” flag input from the determination circuit 3.
  • control circuit switches the signal input to the positive input terminal of the operational amplifier 1 and the signal input to the negative input terminal from the DAC circuit 8 using a switch (not shown) (S146). Thereafter, the same processing as S147 is performed (S147). Similarly to S145, when the output from the operational amplifier 1 is different from the expected value stored in the operational amplifier 1, the determination circuit 3 outputs “H” to the determination flag 4 (S148).
  • FIG. 22 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuits 28A and 28B and performing self-repair.
  • the control circuit detects whether or not the determination flag 4 stores “H” (S151). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S153. On the other hand, when the control circuit detects the determination flag 4 storing “H”, the DAC circuit 8 corresponding to the determination flag 4 storing “H” is switched to the spare DAC circuit 28A or 28B.
  • the operation confirmation is performed with the two DAC circuits 8 as one set, even if the determination flag 4 stores the “H” flag, It cannot be determined whether the DAC circuit is defective.
  • the following description assumes that the DAC circuit 8-1 has a problem.
  • the determination circuits 3-1 and 3-2 output “H” to the determination flags 4-1 and 4-2 by the operation check tests 1 to 5. Will do. Further, the determination flags 4-1 and 4-2 output the “H” flag input from the determination circuits 3-1 and 3-2 to the switches 2c and 2d, thereby turning the switch 2c OFF and turning the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 signal, and the sampling circuit 26B inputs the STR2 signal.
  • the sampling circuit 26A acquires gradation data corresponding to the liquid crystal driving signal output terminal OUT1 from the data bus
  • the sampling circuit 26B acquires the gradation data corresponding to the liquid crystal driving signal output terminal OUT2.
  • Data is acquired from the data bus.
  • the switch 2c is turned OFF, the connection between the output of the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1 is cut off, and the output of the operational amplifier 1-2 and the liquid crystal driving signal output terminal OUT2 are disconnected. The connection is also cut off.
  • the switch 2d is turned on, the output of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2.
  • the defective DAC circuit 8 is switched to the spare DAC circuit 28A and 28B by taking the defective DAC circuit 8 and the DAC circuit 8 paired therewith as a set, thereby switching the defective DAC circuit 8 to the spare DAC circuit. It can be switched to 26A or 26B.
  • control circuit sets the test signal to “L” and the test B signal to “H”, and shifts to normal operation (S153).
  • the gradation voltage from the output circuit block 30 (see FIG. 2) and the gradation voltage from the standby output circuit block 40 (see FIG. 2) are switched.
  • the switching circuit 60 (see FIG. 2) is configured to be provided in the integrated circuits 10 and 20, the present invention is not limited to this, and the switching circuit 60 is configured to be provided on the display panel side. Also good.
  • the configuration and operation of the display unit 90 ′ including the switching circuit 60 on the display panel side will be described as a third embodiment according to the present invention.
  • a different part from Embodiment 1 is demonstrated and the description is abbreviate
  • FIG. 23 is a block diagram showing a schematic configuration of the display unit 90 ′.
  • the display unit 90 ' includes a display panel 80' and an integrated circuit 10 '(drive circuit) that drives the display panel 80' based on gradation data input from the outside.
  • the integrated circuit 10 ′ is different from the integrated circuit 10 of the first embodiment in that the switching circuit 60 is not provided, and the other configuration is the same as that of the integrated circuit 10.
  • the display panel 80 ′ is different from the display panel 80 of the first embodiment in that it includes a switching circuit 60, and other configurations are the same as the display panel 80.
  • FIG. 24 is a block diagram showing a configuration of the integrated circuit 10 ′.
  • the integrated circuit 10 ′ receives n grayscale data corresponding to each of the n output terminals OUT1 to OUTn via a data bus from a grayscale data input terminal (not shown).
  • the integrated circuit 10 ′ includes a plurality of switches 2a that are switched ON / OFF by a test signal, a plurality of switches 2b that is switched ON / OFF by a test B signal, and an ON, OFF by an LF signal. And a plurality of switches 2f for switching OFF.
  • the switches 2a, 2b, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • each of the integrated circuit 10 'spare sampling circuit 26, spare hold circuit 27, spare DAC circuit 28, spare operational amplifier 21, and spare output terminal OUT0 is provided.
  • the display panel 80 ′ includes a connection terminal (not shown) connected to each of the output terminals OUT1 to OUTn included in the integrated circuit 10 ′ and determination flags 9-1 to 9-n ( Hereinafter, when collectively referred to as a determination flag 9), a switch 2 f that is switched ON / OFF by an LF signal from a control circuit (not shown), and an ON / OFF by an LFB signal that is an inverted signal of the LF signal. Switch 2e, and switches 2c and 2d that are turned on and off by Flag1 to Flagn that are output signals from the determination flag 9.
  • the switches 2d, 2e, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned on when an “L” signal is input, and is turned off when an “H” signal is input.
  • the display panel 80 ′ in the present embodiment is a liquid crystal display panel, and as shown in FIG. 24, the data signal line SL ⁇ is connected to each of the output terminals OUT of the integrated circuit 10 ′ via the switches 2e and 2c. 1 to SL-n (hereinafter collectively referred to as data signal lines SL) are connected. Further, the same number of pixels P as the number of scanning signal lines GL are connected to each of the data signal lines SL. In FIG. 24, the pixel P connected to the data signal line SL-1 is a pixel P-1, and the pixel P connected to the data signal line SL-n is a pixel Pn.
  • the test signal is “H” and the test B signal is “L”. Therefore, the connection between the operational amplifier 1 and the output terminal OUT is disconnected by the switch 2b.
  • the control circuit outputs an “H” LF signal and also outputs an “L” LFB signal.
  • the switch 2 f is turned on, and each determination flag 4 is connected to each determination flag 9 via each output terminal OUT. Further, each of the determination flags 4 outputs the “H” flag or “L” flag stored therein as Flag1 to Flagn to each determination flag 9 via each output terminal OUT.
  • Each determination flag 9 stores Flag1 to Flagn output from the determination flag 4 in its own internal memory and outputs it to the switches 2c and 2d connected to itself.
  • Each switch 2e is turned OFF when the LFB signal becomes “L” during the period when the LF signal is “H”. This prevents Flag1 to Flagn output from the determination flag 4 from being output to the data signal lines SL-1 to SL-n. As a result, Flag1 to Flagn output from the determination flag 4 affects the pixel P. Will not affect.
  • the determination flag 4-1 corresponding to the output terminal OUT1 stores the “H” flag, in other words, when the DAC circuit 8-1 is defective, the determination flag 9-1 is determined by the determination flag 4 The “H” flag is then output, and the output “H” flag is recorded in the internal memory of the device. In this example, it is assumed that the determination flags 4-2 to 4-n record the “L” flag.
  • the determination flag 9-1 outputs Flag1 of the “H” flag to the switches 2c and 2d connected to the determination flag 9-1.
  • the switch 2c connected to the determination flag 9-1 disconnects the output terminal OUT1 from the data signal line SL-1, and the switch 2d connected to the determination flag 9-1
  • the terminal OUT0 and the data signal line SL-1 are connected.
  • each of the determination flags 9-2 to 9-n is connected to the determination flags 9-2 to 9-n in order to output the Flag 2 to Flagn of the “L” flag to the switches 2c and 2d connected thereto.
  • the switch 2c is turned on, and the switch 2d connected to the determination flags 9-2 to 9-n is turned off.
  • each of the data signal lines SL-2 to SL-n is connected to each of the output terminals OUT2 to OUTn via the switch 2e.
  • each determination flag 9 switches the switches 2c and 2d connected to itself based on Flag1 to Flagn from the determination flag 4, the control circuit outputs an “L” LF signal and outputs “H”. LFB signal is output. As a result, each of the output terminals OUT2 to OUTn is connected to each of the data signal lines SL-2 to SL-n.
  • the data signal line SL-1 is connected to the output terminal OUT0.
  • the data signal lines SL-2 to SL-n are connected to the operational amplifiers 1-2 to 1-n via the output terminals OUT2 to OUTn. Since the switch 2d connected to the sampling circuit 6-1 is turned on by Flag1 from the determination flag 4-1, the grayscale data (corresponding to the data signal line SL-1) input to the sampling circuit 6-1. Gradation data to be input) is also input to the sampling circuit 26.
  • gradation data corresponding to the data signal line SL-1 is input to the data signal line SL-1 from the output terminal OUT0 instead of the output terminal OUT1.
  • switching of the gradation data input to each of the sampling circuit 6 and the spare sampling circuit 26 is the same as the operation in the first embodiment, and thus detailed description thereof is omitted here.
  • the display unit 90 ′ performs a self-repair operation, so that the normal grayscale voltage is applied to the data signal line SL using the spare DAC circuit 28 instead of the DAC circuit 8 detected as defective. Can be output. Similar to the first embodiment, this embodiment also includes a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 25 is a flowchart showing a processing procedure from when the display unit 90 ′ is turned on to when an operation check test is performed and the normal operation is started.
  • the display unit 90 ′ when the display unit 90 ′ detects that the power is turned on by the user, the display unit 90 ′ initializes the integrated circuit 10, thereby setting all the flags stored in the determination flag 4 to the “L” flag. (S161).
  • the control circuit sets the test signal to “H”, the test B signal to “L”, and switches the integrated circuit 10 ′ to the operation check test state (S 162).
  • the control circuit and the integrated circuit 10 perform the above-described operation check test (S163). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed (S164).
  • the display unit 90 ′ in the present embodiment is configured to include the determination flag 4 and the determination flag 9 as a circuit for storing a flag that is a determination result in the determination circuit 3-1, but the display unit 90 ′ is a modified example.
  • the determination flag 9, the switch 2f, and the switch 2e may not be provided, and the determination flag 4 may control the switches 2c and 2d.
  • the LF signal and the LFB signal for controlling the switches 2f and 2e are also unnecessary, while the determination flag 4 and wiring and connection terminals for connecting the switches 2c and 2d are required.
  • the integrated circuit and the display panel are connected via the output terminal OUT.
  • the integrated circuit and the display panel are not connected via the output terminal OUT.
  • An integrated display device is also included in the scope of the present invention.
  • a display unit 90 ′′ in which an integrated circuit and a display panel are integrated will be described as a fourth embodiment with reference to FIG. 26.
  • the display unit 90 ′′ according to the present embodiment is an embodiment. 1 is a modification of the display unit 90 according to the first embodiment. In the present embodiment, portions different from those of the first embodiment will be described, and descriptions of overlapping portions will be omitted.
  • FIG. 26 is a block diagram illustrating the configuration of the display unit 90 ′′.
  • the display unit 90 ′′ has no distinction between the integrated circuit 10 and the display panel 80 shown in the first embodiment, and the outputs of the operational amplifiers 1 and 21 are connected via the switches 2b, 2c, and 2d.
  • the display unit 90 ′′ of the present embodiment is different from the display unit 90 of the first embodiment in whether or not the output terminal OUT is provided.
  • Other configurations are the same as those of the display unit 90 of the first embodiment.
  • FIG. 27 is a block diagram illustrating a configuration of the television system 300.
  • the television system 300 is described as including the display unit 90 according to the first embodiment.
  • the television system according to the present invention is not limited to this, and instead of the display unit 90, The display device according to Embodiments 2 to 4 may be provided.
  • a television system 300 includes an antenna 301 that receives a broadcast wave, a tuner unit 302 that demodulates the received broadcast wave into a video / audio signal, and the demodulated video / audio signal as a video signal and an audio.
  • a signal separation unit 303 that separates the signal into a signal
  • a video signal processing unit 304 that decodes the separated video signal into a digital video signal, and obtains the decoded digital video signal as gradation data.
  • a display unit 90 that displays video on the display panel 80 (see FIG. 2), an audio signal processing unit 305 that decodes the separated audio signal into a digital audio signal, and the decoded digital audio signal as an analog signal.
  • An audio signal output unit 306 is provided that outputs the converted analog audio signal as audio from a speaker after conversion into the audio signal.
  • the antenna 301 receives a broadcast wave from a broadcast station, and outputs the received broadcast wave to the tuner unit 302.
  • the tuner unit 302 demodulates the output broadcast wave into a video / audio signal, and outputs it to the signal separation unit 303.
  • the signal separation unit 303 separates the output video / audio signal into a video signal and an audio signal, and outputs them to the video signal processing unit 304 and the audio signal processing unit 305, respectively.
  • the video signal processing unit 304 decodes the output video signal into a digital video signal, and outputs the decoded digital video signal to the display unit 90 as gradation data.
  • the display unit 90 displays the output gradation data using the display panel 80 provided therein.
  • the audio signal processing unit 305 decodes the audio signal separated by the signal separation unit 303 into a digital audio signal and outputs it to the audio output unit 306.
  • the audio signal output unit 306 converts the output digital audio signal into an analog audio signal, and then outputs the analog audio signal as audio using a speaker provided therein.
  • the television system 300 is configured to acquire from a broadcasting station using the antenna 301 and the tuner unit 302 as means for acquiring a video / audio signal, but the present invention is not limited to this.
  • the content data recorded on the recording medium may be read from the recording medium, and may be acquired via a PC (personal computer) from a content reading device such as a DVD player or the Internet.
  • the operation check test and the self-repair processing operation described in the first and fourth embodiments are performed immediately after power is supplied to the liquid crystal driving semiconductor integrated circuit 10, but the present invention is not limited to this. Instead, it may be configured by inputting a control signal to the liquid crystal driving semiconductor integrated circuit 10 and may be performed at an arbitrary timing. For example, a signal indicating a display blanking period may be input to the liquid crystal driving semiconductor integrated circuit 10 from the controller of the display device, and an operation check test and self-repair may be performed at this timing.
  • the liquid crystal driving semiconductor integrated circuit 10 is configured to detect a malfunction of the liquid crystal driving semiconductor integrated circuit 10, and the liquid crystal driving semiconductor integrated circuit 10 has an abnormality. Sometimes you can go. For example, the current of the signal output from the liquid crystal driving semiconductor integrated circuit 10 may be detected, and when the detected current exceeds the set current, an operation check test and a self-repair processing operation may be performed.
  • the operation check test and the self-repair processing operation may be performed periodically. For example, it may be performed every vertical blanking period in which no display is performed, or may be performed every preset total display time.
  • the operation check test and the self-repair processing operation may be performed during a part of the display period. For example, since a pixel stores a display voltage in a liquid crystal display device, there is no problem in display even if the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance after charging of the display voltage is completed. During a part of the display period, the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance, and an operation check test and a self-repair processing operation are performed.
  • one pattern is determined in a part of the display period of one line, and it is performed in a display period of one screen or a period of displaying several screens. You can also.
  • the integrated circuit 10 according to the present invention needs to stop the output signal for driving the display panel 80 (see FIG. 2) in order to self-detect its own defect (operation check test). There is. That is, the integrated circuit 10 cannot drive the display panel 80 during the self-detection period. Therefore, the timing at which the integrated circuit 10 performs self-detection needs to be performed in a period that does not affect the display of video on the display device.
  • the case where the integrated circuit 10 performs self-detection and self-repair is described as the period during which the integrated circuit 10 performs self-detection during the startup process when the display device is turned on. This is because the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device because the display device does not display video during the startup process of the display device. Because.
  • the integrated circuit 10 in the present embodiment performs self-detection to detect its own defect during the startup process when the display device is turned on.
  • the present invention is not limited to this.
  • Self-detection and self-repair can be performed in a period other than during the startup process of the display device.
  • Example 1 (Self-detection and self-repair in the vertical blanking period)
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device. Become. The reason will be described below.
  • FIG. (A) to (f) of FIG. 28 are time charts showing timings of signals inputted to the liquid crystal display device.
  • FIG. 28A shows the scanning signal line SCN1 that is output from the scanning side driving circuit that drives the scanning lines of the display device and is given to the first scanning signal line of the display device
  • FIG. Indicates a scanning signal line SCN2 output from the scanning side drive circuit and applied to the second scanning signal line of the display device
  • (c) in FIG. 8 is a video signal inversion from the integrated circuit 10 (see FIG. 7).
  • a video signal DSj corresponding to the j-th data signal line of the display device, which is given to the circuit, is shown, and (d) in the same figure shows the j-th data signal line from the video signal inversion circuit to the data side drive circuit.
  • the video signal DRVj corresponding to the data signal line is shown, (e) in the figure shows the video signal DATAj given to the jth data signal line of the display device, and (f) in the figure shows 1 in the display device.
  • the first scanning signal line and the jth It shows a driving voltage VD1j applied to pixels connected to the data signal line.
  • a period TV from time t1 to t5 is a vertical scanning period of the display device
  • a period TV1 is a vertical blanking period
  • a period TH from time t1 to t3 is a horizontal scanning period
  • a period TH1 from t2 to t3 is a horizontal blanking period.
  • the video signal inversion circuit inverts the polarity of the video signal DSj from the integrated circuit 10 in order to invert the polarity of the display electrode in each pixel of the display device every horizontal scanning period TH and vertical scanning period TV. Circuit.
  • the scanning side drive circuit sequentially delays the timing by the horizontal scanning TH from the first scanning signal line for each scanning signal line of the display device. , Scan signal SCN1, scan signal SCN2,..., Scan signal SCNm. Further, the scanning side driving circuit repeatedly outputs each scanning signal SCN1 to scanning signal SCNm to each scanning signal line of the display device every vertical scanning period TV. Note that here, the display device has m scanning signal lines.
  • the video signal DSj from the integrated circuit 10 is input to the video signal inversion circuit.
  • the video signal inversion circuit inverts the polarity of the video signal DSj every horizontal scanning period TH and also inverts the polarity every vertical scanning period TV, so that the video signal DRVj shown in FIG. Generate. Further, the video signal inversion circuit inputs the generated video signal DRVj to the data side driving circuit.
  • the data side driving circuit samples the video signal DRVj from the video signal inverting circuit every horizontal scanning period TH, delays the sampled signal value by one horizontal scanning period TH, and (e) of FIG. Is output to the jth data signal line of the display device.
  • the scanning signal SCN1 in the horizontal scanning period TH from time t1 to t2 is used.
  • the TFT in the pixel 1j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t1 to t2 is applied to the display electrode in the pixel 1j via the jth data signal line as the drive voltage VD1j. Is done.
  • the drive voltage VD1j applied to the display electrode of the pixel 1j continues to hold the voltage level during the time t1 to t2 even when the TFT in the pixel 1j is cut off during the time t2 to t5.
  • the scanning signal SCN2 in the horizontal scanning period TH from time t3 to t4.
  • the TFT in the pixel 2j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t3 to t4 is applied to the display electrode in the pixel 2j via the jth data signal line as a drive voltage.
  • the drive voltage applied to the display electrode of the pixel 2j continues to hold the voltage level between times t3 and t4 even when the TFT in the pixel 2j is turned off.
  • the scanning-side driving circuit does not output the scanning signals SCN1 to SCNm for conducting the TFTs of the respective pixels to the scanning signal line, in other words, the period in which the conduction of the TFTs of the respective pixels is cut off.
  • the display device does not need to apply a voltage to the display electrode of each pixel. That is, it is not necessary for the integrated circuit 10 to output the video signal DSj that is the basis of the drive voltage, and even if the integrated circuit 10 and the display device are electrically disconnected, the display of the video on the display device is affected. There is no.
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device.
  • the integrated circuit 10 performs a self-detection process for detecting a defect in an output circuit block included in the integrated circuit 10 for each output circuit block corresponding to each data signal line and for all the output circuit blocks. It is targeted. Therefore, this self-detection process takes time.
  • the integrated circuit 10 does not need to perform self-detection processing when there is no possibility of malfunction in each output circuit block included in the integrated circuit 10. In other words, the integrated circuit 10 only needs to perform self-detection processing only when there is a possibility of malfunction in each output circuit block.
  • the integrated circuit 10 includes an operation determination circuit that determines whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10, and there is an operation failure somewhere in the integrated circuit 10 by the operation determination circuit. If the self-detection process is performed only when it is determined, it is possible to prevent performing a useless self-detection process.
  • FIG. 29 the operation determination circuit 200 for determining whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10 included in the integrated circuit 10 will be described with reference to FIGS. 29 to 31.
  • FIG. 29 the operation determination circuit 200 for determining whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10 included in the integrated circuit 10 will be described with reference to FIGS. 29 to 31.
  • the power supply current supplied to the integrated circuit 10 is compared with that during normal operation, in other words, compared with the initial stage that is determined to be good when shipped as a product. Become more. Therefore, when the value of the power supply current supplied to the integrated circuit 10 becomes larger than a certain value compared with the normal operation, an operation failure has occurred in the integrated circuit 10. Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 10 and determines whether an operation failure has occurred in the integrated circuit 10 from the detected value of the power supply current.
  • FIG. 29 is a block diagram showing a configuration of the operation determination circuit 200.
  • the operation determination circuit 200 includes a resistor 202 (detection means) and a switch 203 between the integrated circuit 10 and the VA 201 that supplies power to the integrated circuit 10.
  • the resistor 202 and the switch 203 are connected so as to be parallel to each other.
  • the operation determination circuit 200 includes an A / D converter 204 (detection means) connected to one end of the resistor 202 and the switch 203 on the integrated circuit 10 side, and a switch for inputting an output signal from the A / D converter 204.
  • a comparison circuit 208 (current value comparison means, drive circuit determination means) that compares the output value with the output value from the data latch circuit 207 is provided. Note that the output terminal of the comparison circuit 208 connects the comparison result in the comparison circuit 208 to a control circuit included in the integrated circuit 10. Note that switching of the switches 203 and 205 is controlled by a control circuit included in the integrated circuit 10.
  • the operation determination circuit 200 previously stores a value corresponding to the power supply current value during normal operation of the integrated circuit 10 in the EEPROM 206 as reference data.
  • the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit 10.
  • the value of the reference data stored in the EEPROM 206 is compared, and if the detected value is equal to or greater than a certain value, it is determined that an operation failure has occurred in the integrated circuit 10.
  • the operation determination circuit 200 outputs a signal indicating that an operation failure has occurred in the integrated circuit 10 to the control circuit included in the integrated circuit 10, so that the control circuit detects the self-detection of the integrated circuit 10. Start processing and self-healing process.
  • FIG. 30 is a flowchart showing an operation process in which the operation determination circuit 200 stores reference data in the EEPROM 206.
  • the control circuit in generating the reference data, opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S301).
  • the resistance value of the resistor 202 is a resistance value such that the voltage drop of the resistor 202 during the normal operation of the integrated circuit 10 is about 0.1V. Note that the resistance value of the resistor 202 is preferably determined in consideration of current consumption of the integrated circuit.
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S302).
  • the A / D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205.
  • the EEPROM 206 stores the input digital value from the A / D converter as basic data (S303). Note that the switch 205 in S303 is switched by the control circuit so as to connect the A / D converter 204 and the EEPROM 206.
  • the control circuit short-circuits the switch 203 and returns the integrated circuit 10 to the normal operation state (S304).
  • the generation and storage processing of the reference data from S301 to S304 is performed at the product shipment stage of the display device including the integrated circuit 10, in other words, at the stage where the integrated circuit 10 is determined to be normal by various shipment inspections. Is called.
  • FIG. 31 is a flowchart showing processing for detecting an operation failure of the integrated circuit 10 in the operation determination circuit 200.
  • the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S305).
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S306).
  • the A / D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205.
  • the data latch circuit 207 stores the input digital value from the A / D converter as detection data (S307). Note that the switch 205 in S306 is switched by the control circuit so as to connect the A / D converter 204 and the data latch circuit 207.
  • the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data stored in the data latch circuit 207, and compares the value of the read reference data with the value of the detection data (S308). Further, the comparison circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is equal to or greater than a predetermined value (for example, 3 or more as a digital value) (S309).
  • a predetermined value for example, 3 or more as a digital value
  • the control circuit 208 when the control circuit 208 receives a signal indicating that a malfunction has occurred in the integrated circuit 10 from the comparison circuit 208, the control circuit starts self-detection of the integrated circuit 10 (S311). Further, in the self-detection of the integrated circuit 10, when the integrated circuit 10 detects a failure in its own output circuit block, the integrated circuit 10 switches between the output of the defective output circuit block and the output of the spare output circuit block, Perform self-healing. Note that if the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 10 in S311, it is considered that the power supply current value varies due to other factors.
  • the operation determination circuit 200 since the power supply current value fluctuates, the operation determination circuit 200 generates and stores the reference data shown in S301 to S304, and the power supply current value that has fluctuated is newly set.
  • the reference data is stored in the EEPROM 206 (S312). Further, after S312, the control circuit short-circuits the switch 203 to place the operation determination circuit 200 and the integrated circuit 10 in a normal operation state (S310).
  • the comparison circuit 208 detects in S309 that the difference between the reference data value and the detected data value is less than a predetermined value (for example, less than 3 as a digital value), the process proceeds to S310. Transition.
  • a predetermined value for example, less than 3 as a digital value
  • Example 2 (Periodic self-detection of the integrated circuit 10) Further, self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed periodically. Specifically, the self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed for each vertical blanking period of the display device described in the first embodiment. In this case, the vertical synchronization signal is counted and is displayed every certain number of times.
  • the counter can be configured by a non-volatile memory and the counter can count the number of vertical synchronization signals.
  • the integrated circuit 10 may be provided with a timer for measuring time, the operation time is counted by this timer, and the integrated circuit 10 is self-detected and self-repaired every preset accumulated operation time.
  • the self-detection (operation check test) and self-repair processing operation of the integrated circuit 10 may be performed during a part of a period during which the display device displays an image. For example, since each pixel of the display device stores the voltage of the display electrode, after charging of the voltage of the display electrode is finished, the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, There is no problem with the video display.
  • the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, and self-detection (operation check test) and self-repair processing operations are performed.
  • a method for setting the output terminals OUT1 to OUTn to high impedance by providing a switch in series for each signal transmission path connecting the output terminals OUT1 to OUTn and the display device, and opening the switch, The output terminals OUT1 to OUTn and the display device have high impedance, in other words, can be electrically disconnected.
  • the integrated circuit 10 in the first embodiment has been described.
  • the present invention is not limited to this, and the integrated circuits 10 ′, 20 and in the second and third embodiments, and The present invention can also be applied to the display unit 90 ′′ in the fourth embodiment.
  • the liquid crystal display device that displays an image by the liquid crystal display panel has been described.
  • the present invention is not limited to this, and the present invention is not limited to the liquid crystal display device, such as a plasma television. Is also applicable.
  • the display device driving integrated circuit and the display device of the present invention may be configured as follows.
  • the self-healing means is Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means; If the determination result of the determination means is bad, the output terminal comprises a connection switching means for connecting the spare output circuit instead of the output circuit,
  • the output circuit block and the spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means.
  • Control means for controlling input signals to be input to the output circuit and the standby output circuit includes While inputting input signals of different magnitudes to the output circuit and the standby output circuit, Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
  • the drive circuit according to the first configuration or the second configuration, wherein the determination unit determines that the output circuit is defective when the comparison result and the expected value are different.
  • Flag storage means for storing a flag indicating the determination result of the determination means;
  • the connection switching means connects the spare output circuit to the output terminal instead of the output circuit when the value of the flag indicates that the output circuit is defective.
  • the drive circuit according to any one of the configuration from the third configuration to the third configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit, After the connection switching means connects the output terminal and the output of the auxiliary output circuit, the auxiliary output circuit outputs an output signal to the output terminal.
  • the drive circuit according to any one of the configurations.
  • Detection means for detecting the value of the power supply current supplied to the drive circuit; Normal current value storage means for storing in advance the value of the power supply current during normal operation of the drive circuit; Current value comparison means for comparing the value of the power supply current from the detection means with the value of the power supply current from the normal current value storage means; Drive circuit determination means for determining whether or not the drive circuit is defective based on a comparison result of the current value comparison means; When the determination result of the drive circuit determination means is bad, The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to the configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to.
  • a blocking means for blocking a signal transmission path from the output terminal to the display panel After the blocking means blocks the signal transmission path from the output terminal to the display panel,
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • N positive even number
  • N output circuit blocks including an output circuit that is connectable to each of the output terminals and outputs an output signal for driving the display panel
  • a first auxiliary output circuit block including a first auxiliary output circuit connectable to the odd numbered output terminal and capable of outputting the output signal to the display panel
  • a drive circuit for driving the display panel comprising: a second spare output circuit block including a second spare output circuit that can be connected to the even-numbered output terminals and can output the output signal to the display panel.
  • the self-healing means is Comparison means for comparing the output signal from the output circuit and the output signal from the output circuit adjacent to the output circuit; Determination means for determining whether or not the output circuit and the output circuit adjacent to the output circuit are defective based on the comparison result of the comparison means; Connection switching for connecting the first spare output circuit and the second spare output circuit to the output terminal instead of the output circuit and the output circuit adjacent to the output circuit, respectively, when the judgment result of the judging means is bad Means, and
  • the output circuit block, the first spare output circuit block, and the second spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means. .
  • Control means for controlling an input signal input to the output circuit, the first auxiliary output circuit, and the second auxiliary output circuit;
  • the control means includes The odd-numbered output circuit and the first spare output circuit, and the even-numbered output circuit and the second spare output circuit are inputted with different magnitude input signals, Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
  • the drive circuit according to the tenth configuration, wherein the determination unit determines that the output circuit and an output circuit adjacent to the output circuit are defective when the comparison result and the expected value are different.
  • a display device comprising: the drive circuit according to any one of the first configuration to the eleventh configuration; and the display panel.
  • a display panel A drive circuit including an output circuit for outputting an output signal for driving the display panel from an output terminal connected to the display panel, and a display device comprising:
  • the drive circuit is A preliminary output circuit capable of outputting the output signal to the display panel; Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on the comparison result of the comparison means;
  • the display panel Switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel when the determination result from the determination means is defective. , Prepared, In the drive circuit, an operational amplifier used as an output buffer of the output circuit and the spare output circuit is used as the comparison means.
  • a display panel An output circuit for outputting an output signal for driving the display panel; A preliminary output circuit capable of outputting the output signal to the display panel; Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means; When the determination result of the determination means is defective, a switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel, Prepared, An operational amplifier used in the output buffer of the output circuit and the spare output circuit is used as the comparison means.
  • a television system comprising the display device according to any one of the twelfth configuration to the fourteenth configuration.
  • the display unit 90 is a display panel 80 and a drive circuit that drives the display panel 80, and detects a failure of the drive circuit in a state where the electrical connection with the display panel 80 is disconnected.
  • a liquid crystal driving semiconductor integrated circuit 10 having a self-detection / self-repair means for repairing, and the self-detection / self-recovery means is configured to switch the drive circuit when the image to be displayed on the display panel is switched discontinuously. A process for detecting a defect is executed.
  • the liquid crystal driving semiconductor integrated circuit 10 drives the display panel 80.
  • the liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect.
  • the liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected.
  • the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80.
  • the self-detection process can be executed using all the gradation data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit when the image to be displayed on the display panel 80 is switched discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed. Further, for example, when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM, the self-detecting / self-repairing means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed.
  • the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected. Since the self-detection process is executed at the timing when the currently displayed content is temporarily interrupted, the user does not feel uncomfortable. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
  • the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair unit performs the display on the display panel 80 once.
  • the self-detection / self-repair unit performs the display on the display panel 80 once.
  • the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups.
  • the self-detecting / self-repairing unit executes the above process group one by one every time the display based on the image signal being supplied to the display panel 80 is interrupted once. For example, when the number of process groups is n, all the processes included in the self-detection process can be completed when the display is interrupted n times.
  • the process is executed each time the display on the display panel 80 is interrupted. Since the processing time of the process group does not become so long, it is possible to execute self-detection and self-repair processing without making the user feel uncomfortable.
  • the process includes a plurality of steps, and the self-detection / self-repair means is included in the process when the display on the display panel is interrupted once. It is preferable to carry out all the steps.
  • the process for detecting a defect of the semiconductor integrated circuit 10 for driving the liquid crystal that is, the self-detection process includes a plurality of steps, and the self-detection / self-repair means is supplied to the display panel 80.
  • the display based on the middle image signal is interrupted once, all the steps included in the self-detection process are executed.
  • the display unit 90 receives a remote control I / F 401 that receives a channel selection operation by a user and a broadcast corresponding to the channel selection operation received by the remote control I / F 401, and displays the image signal of the broadcast on the display panel.
  • a controller 100 that detects that an image to be displayed on the display panel 80 switches discontinuously when switching between broadcasts received by the tuner, and the self-detection / self-repair means includes a controller When switching of an image to be displayed on the display panel 80 is detected by 100, it is preferable to start processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10.
  • the remote control I / F 401 receives a broadcast program tuning by the user. Further, the tuner receives a broadcast corresponding to the channel selection accepted by the remote control I / F 401 and supplies an image signal of the broadcast to the display panel. For example, the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
  • the controller 100 should display the display panel 80 when the display is interrupted by the tuner receiving a new broadcast in response to the user's channel selection. Detect that the images switch discontinuously. For example, when the user selects channel 2 while displaying a one-channel broadcast on display panel 80, when display of one channel is interrupted because the tuner receives the two-channel broadcast, display panel 80 It detects that the image to be displayed switches discontinuously.
  • the self-detecting / self-repairing means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detecting process when switching the broadcast received by the tuner.
  • a tuner that receives a broadcast and supplies an image signal of the broadcast to the display panel 80, and when the content of the broadcast received by the tuner is switched from a program to a CM (Commercial Message), And a controller 100 for detecting that the image to be displayed on the display panel 80 switches discontinuously, and the self-detection / self-repair means detects the switching of the image to be displayed on the display panel 80 by the controller 100.
  • CM Common Message
  • the tuner receives a broadcast and supplies an image signal of the broadcast to the display panel 80.
  • the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
  • the controller 100 switches the image signal supplied to the display panel 80 from the image signal representing the program included in the broadcast to the image signal representing the CM included in the broadcast.
  • the controller 100 detects that the image to be displayed on the display panel 80 is switched discontinuously when the display based on the image signal representing the program is interrupted by the program being broadcast being shifted to the CM.
  • the self-detection / self-repair means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detection process when the controller 100 detects the interruption of the display on the display panel 80.
  • the display unit 90 includes the display panel 80, a supply period in which an image signal is supplied, and a supply in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel 80.
  • Self-detection / self-repair means for detecting and repairing a defect in the drive circuit that drives the display panel 80 while switching the stop period and is disconnected from the display panel 80.
  • the self-detecting / self-repairing means executes processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period.
  • the liquid crystal driving semiconductor integrated circuit 10 stops the supply period in which the image signal is supplied and the supply of the image signal in the period in which the image is displayed on the display panel 80.
  • the display panel 80 is driven while switching the supply stop period.
  • the liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect.
  • the liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected.
  • the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80.
  • the self-detection process can be executed using all the gradation data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period.
  • the self-detecting / self-repairing unit executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in the horizontal scanning period and the vertical scanning period.
  • the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected, but the display while displaying an image. Since the self-detection process is executed at the timing when the image signal is not supplied to the panel 80, the display panel 80 is not hindered. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
  • the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair means performs the process group for each supply stop period. Are preferably performed one by one.
  • the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups.
  • the self-detecting / self-repairing means executes the above process group one by one for each supply stop period. For example, when the number of process groups is n, all processes included in the self-detection process can be completed in n supply stop periods.
  • the process includes a plurality of processes, and the self-detecting / self-repairing unit executes all processes included in the process in one supply stop period. It is preferable.
  • the process for detecting a defect in the semiconductor integrated circuit 10 for driving the liquid crystal that is, the self-detection process includes a plurality of steps. In the period, all the steps included in the self-detection process are executed.
  • the display unit 90 further includes a controller 100 that detects switching from the supply period to the horizontal blanking period as the supply stop period in a period during which an image is displayed on the display panel 80,
  • the self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
  • the controller 100 detects the horizontal blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the horizontal blanking period. In the horizontal blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
  • the display unit 90 further includes a controller 100 that detects switching from the supply period to the vertical blanking period as the supply stop period in a period during which an image is displayed on the display panel 80,
  • the self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
  • the controller 100 detects the vertical blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the vertical blanking period. In the vertical blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
  • the self-detection process in the vertical blanking period in which the image signal is not supplied to the display panel 80. Therefore, the self-detection process does not affect the screen display. The user does not feel uncomfortable.
  • the liquid crystal driving semiconductor integrated circuit 10 includes an output circuit block 30 that outputs an output signal for driving the display panel 80, and the self-detection / self-repair means includes an output circuit.
  • a comparison / determination circuit 50 for determining whether or not the block 30 is defective is provided. When the determination result of the comparison / determination circuit 50 is defective, a liquid crystal driving semiconductor is output so as to output a normal output signal to the display panel 80.
  • the integrated circuit 10 is preferably self-healing.
  • the liquid crystal driving semiconductor integrated circuit 10 includes the output circuit block 30 that outputs an output signal for driving the display panel 80.
  • the output circuit block 30 converts, for example, video data into a gradation voltage and outputs it as an output signal for driving the display panel 80.
  • the self-detection / self-repair means includes the comparison determination circuit 50 that determines whether or not the output circuit block 30 is defective, and the determination result in the comparison determination circuit 50 is defective. If so, the liquid crystal driving semiconductor integrated circuit 10 is self-repaired so as to output a normal output signal to the display panel 80.
  • the display unit 90 in the display unit 90 according to the present embodiment, a defect in the output circuit block 30 of the liquid crystal driving semiconductor integrated circuit 10 can be detected, and self-repair can be performed when the output circuit block 30 is defective.
  • the liquid crystal driving semiconductor integrated circuit 10 includes a spare output circuit block 40 that can output the output signal to the display panel 80, and the self-detection / self-repair means is a comparison / determination circuit.
  • the determination result of 50 is defective, a switching circuit 60 that switches the output signal from the defective output circuit block 30 to the output signal from the standby output circuit block 40 as an output signal to the display panel 80, It is preferable to provide.
  • the drive circuit includes the spare output circuit block 40 that can output an output signal to the display panel 80.
  • the preliminary output circuit block 40 can convert, for example, video data into a gradation voltage and output it as an output signal for driving the display panel 80.
  • the self-detection / self-repair means includes the switching circuit 60 that switches the output circuit block 30 determined to be defective in the comparison determination circuit 50 to the spare output circuit block 40.
  • the display unit 90 when the output circuit block 30 is defective, the defective output circuit block 30 is switched to the spare output circuit block 40, whereby the liquid crystal driving semiconductor integrated circuit 10 is replaced. Self-healing can be easily performed.
  • the comparison determination circuit 50 compares the output signal from the output circuit block 30 with the output signal from the auxiliary output circuit block 40, as operational amplifiers 1-1, 1-2, 1-. It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n.
  • the operational amplifiers 1-1, 1-2, and 1-n compare the output signal from the output circuit block 30 with the output signal from the spare output circuit block 40. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • a defect in the output circuit block 30 can be determined by comparing the output of the output circuit block 30 and the output of the standby output circuit block 40.
  • a defect in the output circuit block 30 can be easily detected.
  • the display unit 90 further includes control means for controlling input signals input to the output circuit block 30 and the spare output circuit block 40, and the control means includes the output circuit block 30, the spare output circuit block 40, and the like.
  • control means for controlling input signals input to the output circuit block 30 and the spare output circuit block 40
  • the control means includes the output circuit block 30, the spare output circuit block 40, and the like.
  • an input signal of a different magnitude is input, and an expected value of a comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signal of the different magnitude is output, and a comparison determination circuit 50, it is preferable to determine that the output circuit block 30 is defective when the comparison result is different from the expected value.
  • the control means controls the input signals input to the output circuit block 30 and the spare output circuit block 40 and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes.
  • the comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
  • an input signal of gradation m is input to the output circuit block 30, and an input signal of gradation m + 1 is input to the standby output circuit block 40.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the spare output circuit block 40 is higher.
  • the output circuit block 30 when the output circuit block 30 is defective and the output circuit block 30 can output only a high gradation voltage even if a signal of gradation m is input, the operational amplifiers 1-1, 1-2, and 1-n A signal indicating that the input gradation voltage is higher than that of the output circuit block 30 is output.
  • the operational amplifiers 1-1, 1-2, and 1-n compare the grayscale voltages output from the output circuit block 30 and the spare output circuit block 40. Then, different values of signals are output depending on whether the output circuit block 30 is defective or not.
  • the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when the input signal of gradation m is input to the output circuit block 30 and the input signal of gradation m + 1 is input to the standby output circuit block 40 as described above, the level from the output circuit block 30 is increased. When a signal indicating that the regulated voltage is high is input from the operational amplifiers 1-1, 1-2, and 1-n, the output circuit block 30 is determined to be defective.
  • the comparison / determination circuit 50 determines that the output circuit block 30 is defective. It is determined that it is not.
  • the display unit 90 includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
  • the comparison determination circuit 50 includes operational amplifiers 1-1, 1-2, and 1-n that compare output signals from at least two output circuits in the output circuit block 30; It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison results of the operational amplifiers 1-1, 1-2, and 1-n.
  • the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n.
  • the operational amplifiers 1-1, 1-2, and 1-n compare output signals from at least two output circuits in the output circuit block 30. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • the display unit 90 can determine the failure of the output circuit block 30 by comparing the output of the output circuit block 30. Therefore, the failure of the output circuit block 30 can be easily detected with a simple configuration. Can be detected.
  • the display unit 90 further includes control means for controlling input signals to be input to at least two output circuits in the output circuit block 30, and the control means is different from the at least two output circuits.
  • the input signal of the magnitude is input, and the expected value of the comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signals of the different magnitudes is output.
  • the comparison result and the expected value are different, it is preferable to determine that one of the at least two output circuits is defective.
  • the control means controls the input signals input to at least two output circuits in the output circuit block 30, and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes.
  • the comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
  • the input signal of gradation m is input to the first output circuit
  • the input signal of gradation m + 1 is input to the output circuit 2.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the second output circuit is higher. .
  • the operational amplifiers 1-1, 1-2, 1-n Outputs a signal indicating that the gradation voltage input from the first output circuit is higher.
  • the operational amplifiers 1-1, 1-2, and 1-n have the grayscale voltages output from at least two output circuits in the output circuit block 30. And output signals having different values depending on whether the output circuit block 30 is defective or not.
  • the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when different input signals are input to the two output circuits of the first output circuit and the second output circuit as described above, the input signal of the gradation m is input to the first output circuit. When an input signal of gradation m + 1 is input to the second output circuit, a signal indicating that the gradation voltage from the first output circuit is high is supplied to the operational amplifiers 1-1, 1-2, 1-n. When more inputs are made, the comparison / determination circuit 50 determines that at least one of the first output circuit and the second output circuit is defective.
  • the first output circuit and the second output circuit are switched to a spare output circuit.
  • the comparison determination circuit 50 causes the output circuit block 30 to be defective. It is determined that it is not.
  • the display unit 90 includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
  • the output circuit block 30 includes an operational amplifier 21 as an output buffer, and the operational amplifiers 1-1, 1-2, and 1-n are comparators including the operational amplifier 21. It is preferable.
  • the output circuit block 30 includes the operational amplifier 21 as an output buffer.
  • the operational amplifiers 1-1, 1-2, and 1-n are comparators configured by the operational amplifier 21.
  • an output signal from the output circuit block 30 that drives the display panel 80 is buffered and output to an output terminal.
  • the operational amplifier 21 provides a voltage follower circuit by negatively feeding back its output to its negative input terminal, and has a function as a buffer circuit.
  • the operational amplifier 21 buffers the output signal from the output circuit block 30.
  • both the buffer circuit and the operational amplifiers 1-1, 1-2, and 1-n are combined. Therefore, the liquid crystal driving semiconductor integrated circuit 10 according to the present embodiment does not require a separate buffer circuit for buffering the output signal from the output circuit block 30, and has the effect of reducing costs.
  • the operational amplifier 21 preferably operates as a voltage follower when the display panel 80 is driven.
  • the television system 300 may be configured to include the display unit 90.
  • the present invention provides a display device including a display drive integrated circuit that includes specific means for detecting a defect in the output circuit and self-repairing, and that can more easily cope with the malfunction of the output circuit. It is suitable for a liquid crystal display device that can perform self-detection and self-repair at an appropriate timing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • General Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Provided is a liquid crystal television (400) including a display unit (90) equipped with: a display panel (80); and a source driver (10) for driving the display panel (80).  The source driver (10) has a comparison check circuit (50) and a switching circuit (60) for detecting and recovering a failure of the source driver (10) when electrically disconnected from the display panel (80).  The comparison check circuit (50) and the switching circuit (60) execute a process for detecting a failure of the source driver at a channel switching timing or at a timing when a program is shifted to a CM.  Thus, the display device can execute a self-detection and a self-recovery at an appropriate timing.

Description

表示装置、およびテレビジョンシステムDisplay device and television system
　本発明は、ＤＡコンバータ出力回路における不具合の自己検出および自己修復を行う駆動回路を使用した表示装置に関するものである。 The present invention relates to a display device using a drive circuit that performs self-detection and self-repair of a defect in a DA converter output circuit.
　近年、液晶パネル等の大型化および高精細化に伴い、液晶駆動用半導体集積回路においては、液晶駆動用出力端子の端子数増加や、出力端子からの出力する多値電圧の多階調化が進んでいる。例えば、現在主流の液晶駆動用半導体集積回路は、２５６階調の電圧を出力可能な約５００個の出力端子数を備えるものがある。さらに、出力端子数を１０００個以上備えた、液晶駆動用半導体集積回路の開発も、現在行われている。また、階調出力電圧は、液晶パネルの多色化に伴い、１０２４階調を出力可能な液晶駆動用半導体集積回路の開発も行われている。 In recent years, with the increase in size and definition of liquid crystal panels and the like, in the semiconductor integrated circuit for liquid crystal drive, the number of output terminals for liquid crystal drive has increased, and the multi-value voltage output from the output terminal has been increased in multiple gradations. Progressing. For example, some of the currently mainstream liquid crystal driving semiconductor integrated circuits have about 500 output terminals capable of outputting 256 gray scale voltages. Furthermore, development of a semiconductor integrated circuit for driving a liquid crystal having 1000 or more output terminals is currently underway. Also, development of a semiconductor integrated circuit for driving a liquid crystal capable of outputting 1024 gradations has been carried out with the increase in the color of the liquid crystal panel.
　ここで、従来の液晶駆動用半導体集積回路の構成を、図３２を参照して以下に説明する。図３２は、従来の液晶駆動用半導体集積回路の構成を示すブロック図である。 Here, the configuration of a conventional semiconductor integrated circuit for driving a liquid crystal will be described below with reference to FIG. FIG. 32 is a block diagram showing a configuration of a conventional semiconductor integrated circuit for driving a liquid crystal.
　同図に示す液晶駆動用半導体集積回路１０１は、ｎ本の液晶駆動用信号出力端子から、それぞれｍ階調の出力電圧を出力できる。まず、液晶駆動用半導体集積回路１０１の構成について説明する。液晶駆動用半導体集積回路１０１は、外部にクロック入力端子１０２、複数の信号入力端子を備えた階調データ入力端子１０３、ＬＯＡＤ信号入力端子１０４、および、基準電源端子であるＶ０端子１０５、Ｖ１端子１０６、Ｖ２端子１０７、Ｖ３端子１０８、Ｖ４端子１０９を備えている。さらに、液晶駆動用半導体集積回路１０１は、ｎ個の液晶駆動用信号出力端子１１１－１～１１１－ｎ（以下、液晶駆動用信号出力端子を信号出力端子と称する。さらに、液晶駆動用信号出力端子１１１－１～１１１－ｎを総称する場合は、信号出力端子１１１と称する）を備えている。また、液晶駆動用半導体集積回路１０１は、基準電源補正回路１２１、ポインタ用シフトレジスタ回路１２３、ラッチ回路部１２４、ホールド回路１２５、Ｄ／Ａコンバータ（Ｄｉｇｉｔａｌ　Ａｎａｌｏｇ　Ｃｏｎｖｅｒｔｅｒ：以下、ＤＡＣと称する。）回路１２６、および出力バッファ１２７を備えている。また、ポインタ用シフトレジスタ回路１２３は、ｎ段のシフトレジスタ回路１２３－１～１２３－ｎにより構成される。さらに、ラッチ回路部１２４は、ｎ個のラッチ回路１２４－１～１２４－ｎにより構成され、およびホールド回路１２５は、ｎ個のホールド回路１２５－１～１２５－ｎにより構成される。また、ＤＡＣ回路１２６は、ｎ個のＤＡＣ回路１２６－１～１２６－ｎにより構成される。加えて、出力バッファ１２７はｎ個の出力バッファ１２７－１から１２７－ｎにより構成され、各出力バッファは、オペアンプにより構成される。 The liquid crystal driving semiconductor integrated circuit 101 shown in the figure can output m gray scale output voltages from n liquid crystal driving signal output terminals. First, the configuration of the liquid crystal driving semiconductor integrated circuit 101 will be described. A liquid crystal driving semiconductor integrated circuit 101 includes an external clock input terminal 102, a gradation data input terminal 103 having a plurality of signal input terminals, a LOAD signal input terminal 104, and V0 terminals 105 and V1 terminals which are reference power supply terminals. 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109. Furthermore, the liquid crystal driving semiconductor integrated circuit 101 includes n liquid crystal driving signal output terminals 111-1 to 111-n (hereinafter, the liquid crystal driving signal output terminals are referred to as signal output terminals. Terminals 111-1 to 111-n are collectively referred to as signal output terminal 111). The liquid crystal driving semiconductor integrated circuit 101 includes a reference power correction circuit 121, a pointer shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 126 and an output buffer 127. The pointer shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n. Further, the latch circuit unit 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n hold circuits 125-1 to 125-n. The DAC circuit 126 is composed of n DAC circuits 126-1 to 126-n. In addition, the output buffer 127 includes n output buffers 127-1 to 127-n, and each output buffer includes an operational amplifier.
　次に、液晶駆動用半導体集積回路１０１の動作について説明する。ポインタ用シフトレジスタ回路１２３は、クロック入力端子１０２より入力したクロック入力信号に基づき、１個目のラッチ回路１２４－１からｎ個目のラッチ回路１２４－ｎまで順次選択する。ポインタ用シフトレジスタ回路１２３により選択されたラッチ回路１２４は、階調データ入力端子１０３からの階調出力データを格納する。なお、階調出力データは、ラッチ回路１２４ごとに対応する、言い換えれば、信号出力端子１１１ごとに対応する、上記クロック入力信号に同期したデータである。したがって、各ラッチ回路１２４－１～１２４－ｎは、信号出力端子１１１ごとに対応する、それぞれ異なる値の階調出力データを格納できる。ラッチ回路１２４－１～１２４－ｎに格納された階調出力データは、データＬＯＡＤ信号により、それぞれ対応するｎ個のホールド回路１２５－１～１２５－ｎへ転送する。さらに、ホールド回路１２５－１～１２５－ｎは、ラッチ回路１２４－１～１２４－ｎより入力した階調出力データを、デジタルデータとしてＤＡＣ回路１２６－１～１２６－ｎに出力する。 Next, the operation of the liquid crystal driving semiconductor integrated circuit 101 will be described. The pointer shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-n based on the clock input signal input from the clock input terminal 102. The latch circuit 124 selected by the pointer shift register circuit 123 stores the gradation output data from the gradation data input terminal 103. Note that the gradation output data corresponds to each latch circuit 124, in other words, corresponds to each signal output terminal 111 and is data synchronized with the clock input signal. Accordingly, each of the latch circuits 124-1 to 124-n can store gradation output data having different values corresponding to each signal output terminal 111. The gradation output data stored in the latch circuits 124-1 to 124-n is transferred to the corresponding n number of hold circuits 125-1 to 125-n by the data LOAD signal. Further, the hold circuits 125-1 to 125-n output the gradation output data input from the latch circuits 124-1 to 124-n to the DAC circuits 126-1 to 126-n as digital data.
　ここで、ＤＡＣ回路１２６－１～１２６－ｎは、ホールド回路１２５からの階調出力データに基づき、ｍ種類の階調電圧における、１つの電圧値を選択し、出力バッファ１２７－１～１２７－ｎに出力する。なおＤＡＣ回路１２６は、基準電源端子Ｖ０端子１０５～Ｖ４端子１０９より入力する電圧によって、ｍ種類の階調電圧を出力することが可能である。次に、出力バッファ１２７は、ＤＡＣ回路１２６からの階調電圧をバッファし、信号出力端子１１１－１～１１１－ｎに、液晶パネル駆動用信号として出力する。 Here, the DAC circuits 126-1 to 126-n select one voltage value among m kinds of gradation voltages based on the gradation output data from the hold circuit 125, and output buffers 127-1 to 127- output to n. Note that the DAC circuit 126 can output m types of gradation voltages depending on voltages input from the reference power supply terminal V0 terminal 105 to the V4 terminal 109. Next, the output buffer 127 buffers the gradation voltage from the DAC circuit 126 and outputs it as a liquid crystal panel drive signal to the signal output terminals 111-1 to 111-n.
　以上のように、シフトレジスタ回路１２３、ラッチ回路１２４、ホールド回路１２５、ＤＡＣ回路１２６、および出力バッファ１２７は、液晶駆動用信号出力端子１１１と同じ個数必要なり、液晶駆動用信号出力端子１１１が１０００端子であれば、上記の各回路１２４～１２７も、それぞれ１０００個必要となる。 As described above, the same number of shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 as the liquid crystal drive signal output terminals 111 are required, and the liquid crystal drive signal output terminals 111 are 1000 in number. If it is a terminal, 1000 of each of the circuits 124 to 127 is required.
　上述したように、近年、液晶パネル等の表示装置が大型化・高精細化が進んでおり、フルスペックの高精細テレビ（ＨＤＴＶ：Ｈｉｇｈ　Ｄｅｆｉｎｉｔｉｏｎ　Ｔｅｌｅｖｉｓｉｏｎ）においては、データライン数は１９２０本となる。よって、表示駆動用半導体集積回路は、データラインごとに、Ｒ・Ｇ・Ｂの階調電圧の信号を与える必要があり、結果、表示駆動用半導体集積回路は、１９２０本×３（Ｒ・Ｇ・Ｂ）＝５７６０本の出力数、言い換えれば、５７６０個の液晶駆動用信号出力端子を備える必要がある。ここで、１つの表示駆動用半導体集積回路の出力数を７２０本とした場合、表示駆動用半導体集積回路は８個必要となる。 As described above, in recent years, display devices such as liquid crystal panels have been increased in size and definition, and in a full-spec high definition television (HDTV: High Definition Television), the number of data lines is 1,920. Therefore, the display driving semiconductor integrated circuit needs to give a signal of gradation voltage of R, G, B for each data line. As a result, the display driving semiconductor integrated circuit has 1920 lines × 3 (R · G B) = 5760 output numbers, in other words, 5760 liquid crystal drive signal output terminals need to be provided. Here, when the number of outputs of one display driving semiconductor integrated circuit is 720, eight display driving semiconductor integrated circuits are required.
　一般的に、表示駆動用半導体集積回路はウエハ段階においてテストされ、パッケージ後出荷テストされ、液晶パネルへ搭載後に表示テストが行われる。さらに、バーンインやストレステストのスクリーニングテストにより、初期不良が起こる可能性のある半導体集積回路は取り除かれる。したがって、表示不良が起こる、表示駆動用半導体集積回路を搭載した表示装置が、市場へ出荷されることはない。しかしながら、出荷前のテストやスクリーニングテストの際には、不良と判断されなかった、極微小の欠陥や異物の付着混入により、表示装置を使用している間に表示不良が稀に発生する。例えば、表示駆動用半導体集積回路の１つのデータラインにおける、出荷後の表示不良が発生する割合が０．０１ｐｐｍ（１億分の１）であったとしても、データライン数が５７６０本となるフルスペックのＨＤＴＶにおいては、表示不良の発生割合は、５７．６ｐｐｍ（１００万分の５７．６）となる。つまり、約１７３６１台に１台が、表示不良を発生することになり、より大型化・高精細化になるほど、表示不良の発生割合は高くなる。 Generally, a semiconductor integrated circuit for display driving is tested at a wafer stage, is subjected to a shipping test after being packaged, and a display test is performed after being mounted on a liquid crystal panel. Furthermore, semiconductor integrated circuits that may cause initial failures are removed by screening tests such as burn-in and stress tests. Therefore, a display device on which a display driving semiconductor integrated circuit in which display failure occurs is not shipped to the market. However, a display defect rarely occurs while using the display device due to a very small defect or a foreign matter adhering and mixing that has not been determined to be defective during a pre-shipment test or a screening test. For example, even if the ratio of occurrence of display defects after shipment in one data line of a semiconductor integrated circuit for display driving is 0.01 ppm (parts per hundred million), the number of data lines is 5760 full. In the spec HDTV, the display defect occurrence rate is 57.6 ppm (57.6 / 1,000,000). That is, about one in about 17361 units will cause display defects, and the larger the size and the higher definition, the higher the rate of occurrence of display defects.
　このような、表示不良が発生した場合、迅速に表示装置を回収し、表示駆動用半導体集積回路のリペアを行う必要があるが、回収修理に大きなコストを要するのはもちろんのこと、商品イメージが低下することになる。 When such a display defect occurs, it is necessary to quickly collect the display device and repair the display driving semiconductor integrated circuit. Will be reduced.
　ここで、従来技術においては、表示駆動用半導体集積回路に、欠陥となる回路に備える予備の回路を設け、欠陥のある回路を予備の回路に切り替えることにより、表示駆動用半導体集積回路の不具合を回避することが開示されている。 Here, in the prior art, the display driving semiconductor integrated circuit is provided with a spare circuit provided for the defective circuit, and the defective circuit is switched to the spare circuit, so that the defect of the display driving semiconductor integrated circuit is eliminated. Avoidance is disclosed.
　具体的には、特許文献１において、表示駆動用半導体集積回路が、シフトレジスタの各段に予備の並列回路を備え、シフトレジスタの自己検査を行い、この検査結果をもとに、並列回路の欠陥のない一方を選択することによって、欠陥のシフトレジスタが引き起こす表示不良を回避する手法が開示されている。さらに、特許文献２においては、ＤＡＣ回路の入力と出力にセレクターを設け、欠陥のあるＤＡＣ回路の位置が記憶されたＲＡＭの情報をもとに、セレクターを切り替え、欠陥のないＤＡＣ回路を選択して使用する方法が開示されている。 Specifically, in Patent Document 1, the display driving semiconductor integrated circuit includes a spare parallel circuit at each stage of the shift register, and performs a self-inspection of the shift register. A technique for avoiding display defects caused by a defective shift register by selecting one having no defect is disclosed. Furthermore, in Patent Document 2, a selector is provided at the input and output of the DAC circuit, and the selector is switched based on the RAM information in which the position of the defective DAC circuit is stored, and a DAC circuit without a defect is selected. A method of using the same is disclosed.
　なお、特許文献１および特許文献２には、ＤＡＣ回路等の出力回路における欠陥を検出する自己検出の方法については、全く開示されていない。 Note that Patent Document 1 and Patent Document 2 do not disclose any self-detection method for detecting a defect in an output circuit such as a DAC circuit.
　また、特許文献３には、表示パネルに駆動回路を一体化した製品の駆動回路に冗長性を持たせ、製品完成後においても駆動回路を修復する技術が開示されている。特許文献３に記載の構成では、駆動回路内の駆動出力に予備の出力を設け、駆動出力の１出力と、予備の出力を比較し、出力値が等しいかを判断することにより、出力回路が正常であることを確認する自己検出を行うと共に、自己検出中、診断対象の出力回路の代わりに、予備の出力回路で、表示パネルの駆動を行うものである。 Further, Patent Document 3 discloses a technique for providing redundancy to a drive circuit of a product in which a drive circuit is integrated with a display panel and restoring the drive circuit even after the product is completed. In the configuration described in Patent Document 3, a spare output is provided for the drive output in the drive circuit, and one output of the drive output is compared with the spare output, and the output circuit determines whether the output values are equal. While performing self-detection for confirming normality, the display panel is driven by a spare output circuit instead of the output circuit to be diagnosed during self-detection.
日本国公開特許公報「特開平６－２０８３４６号公報（１９９４年７月２６日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 6-208346 (published July 26, 1994)” 日本国公開特許公報「特開平８－２７８７７１号公報（１９９６年１０月２２日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 8-278771 (published on October 22, 1996)” 日本国公開特許公報「特表２００４－５１１０２２号公報（２００４年４月８日公開）」Japanese Patent Gazette “Special Table 2004-511022 (April 8, 2004)”
　特許文献１や特許文献２に開示されている自己検出および自己修復の構成において、例えばユーザが表示装置を視聴している最中に自己検出および自己修復動作が実行された場合、映像信号を表示装置に供給する出力回路を、表示装置から切り離す必要があるため、この間、画像を表示させることができないという特性がある。したがって、突然画像が表示されなくなってしまう。そのため、ユーザの視聴を妨害したり、表示装置が故障したのではないかとユーザに誤解を与えてしまう問題がある。 In the self-detection and self-repair configurations disclosed in Patent Literature 1 and Patent Literature 2, for example, when a self-detection and self-repair operation is performed while the user is viewing the display device, a video signal is displayed. Since the output circuit supplied to the device needs to be separated from the display device, there is a characteristic that an image cannot be displayed during this time. Therefore, the image is suddenly not displayed. Therefore, there is a problem that the user is misunderstood that the viewing of the user is disturbed or the display device is broken.
　また、特許文献３に記載の構成では、診断対象の駆動回路を表示パネルから切り離し、表示パネルの駆動を予備の駆動回路にて行うと共に、予備の駆動回路の出力と、診断対象の駆動回路の出力とを比較して、診断対象の駆動回路の良否を判定する。これにより、診断対象の駆動回路と予備の駆動回路とに、表示する画像を表す画像データを同時に入力することで、予備の駆動回路により表示パネルに画像を表示すると共に、診断対象の駆動回路の自己検出を行うことが可能となる。つまり、特許文献３の構成のようにアナログクランプ電圧を選択して出力する場合は、表示データにより一部のデータを比較しているため、出力回路の差を検出することは可能である。しかしながら、特許文献３の構成では、予備の駆動回路の出力と診断対象の駆動回路の出力とを比較するためのデータは表示する画像のデータに限られてしまうことになる。 In the configuration described in Patent Document 3, the drive circuit to be diagnosed is separated from the display panel, the display panel is driven by the spare drive circuit, and the output of the spare drive circuit and the drive circuit to be diagnosed are The output is compared to determine whether the drive circuit to be diagnosed is good or bad. Thus, by simultaneously inputting image data representing an image to be displayed to the drive circuit to be diagnosed and the spare drive circuit, an image is displayed on the display panel by the spare drive circuit, and the drive circuit to be diagnosed is also displayed. Self-detection can be performed. That is, when the analog clamp voltage is selected and output as in the configuration of Patent Document 3, a part of the data is compared with the display data, so that the difference between the output circuits can be detected. However, in the configuration of Patent Document 3, the data for comparing the output of the spare drive circuit and the output of the drive circuit to be diagnosed is limited to the image data to be displayed.
　これに対して、デジタルデータによる多階調化を行った表示装置の駆動回路では、デジタルデータに対応する電圧を出力するＤＡ変換回路が必要となる。例えば、２５６階調表示のための駆動回路では２５６の電圧を選択するＤＡ変換回路が必要となる。したがって、ＤＡ変換回路の不具合を検出するためには、２５６の電圧の出力に対応する全ての入力データについて比較する必要がある。 On the other hand, in a display device drive circuit that performs multi-gradation using digital data, a DA converter circuit that outputs a voltage corresponding to the digital data is required. For example, a driver circuit for 256 gradation display requires a DA converter circuit that selects 256 voltages. Therefore, in order to detect a malfunction of the DA conversion circuit, it is necessary to compare all input data corresponding to 256 voltage outputs.
　このため、デジタルデータによる多階調化を行った表示装置の駆動回路に対して、特許文献３の構成を適用した場合、一部の階調に対応する入力データしか比較できず、正確に自己検出を行うことができない。つまり、デジタルデータによる多階調化を行った表示装置の駆動回路では、診断対象の出力回路と予備の出力回路との両方を表示パネルの駆動を行わない状態にして、全ての階調に対応する入力データを、診断対象の出力回路と予備の出力回路との両方に与えて診断を行う必要がある。 For this reason, when the configuration of Patent Document 3 is applied to the driving circuit of a display device that has been subjected to multi-gradation using digital data, only input data corresponding to some of the gradations can be compared and the self-correction Detection cannot be performed. In other words, in the display device drive circuit with multi-gradation using digital data, both the output circuit to be diagnosed and the spare output circuit are in a state in which the display panel is not driven, and is compatible with all gradations. It is necessary to perform diagnosis by providing input data to be supplied to both the output circuit to be diagnosed and the spare output circuit.
　したがって、デジタルデータによる多階調化を行った表示装置の駆動回路では、やはり駆動回路の自己検出動作中に画像を表示させることができないため、ユーザの視聴を妨害したり、表示装置が故障したのではないかとユーザに誤解を与えてしまう問題がある。 Therefore, in the display device drive circuit that has performed multi-gradation using digital data, it is impossible to display an image during the self-detection operation of the drive circuit. There is a problem that misleads the user that it may be.
　本発明は、上記の問題点に鑑みてなされたものであり、その目的は、出力回路や出力回路周辺の出力ブロックの欠陥を自己検出および自己修復可能な駆動回路を供えた表示装置において、ユーザの視聴を妨げずに適切なタイミングで自己検出及び自己修復を行う表示装置を提供することにある。 The present invention has been made in view of the above problems, and its object is to provide a display device provided with a drive circuit capable of self-detecting and self-repairing defects in an output circuit and an output block around the output circuit. It is an object of the present invention to provide a display device that performs self-detection and self-repair at an appropriate timing without disturbing viewing.
　本発明に係る表示装置は、上記の課題を解決するために、表示パネルと、上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、上記自己検出・自己修復手段は、上記表示パネルに表示すべき画像が不連続に切り替わるときに、上記駆動回路の不良を検出する処理を実行することを特徴としている。 In order to solve the above problems, a display device according to the present invention is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected. Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
　上記の構成によれば、駆動回路は、表示パネルを駆動する。そして、駆動回路は、駆動回路自身の不良を検出可能であり、検出した不良を修復する自己検出・自己修復手段とを有している。駆動回路は、自身の不良を検出し修復する処理を、表示パネルとの電気的な接続を切り離した状態で実行する。つまり、駆動回路は、表示パネルとの電気的接続を切り離して自身の不良を検出する（すなわち自己検出する）ことで、表示パネルに表示中の画像を表す階調データだけでなく、全ての階調データを用いて自己検出の処理を実行することができる。なお、画像は、静止画像であってもよいし、動画像すなわち映像であってもよい。 According to the above configuration, the drive circuit drives the display panel. The drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure. The drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels. Self-detection processing can be executed using the key data. The image may be a still image or a moving image, that is, a video.
　そして、上記の構成によれば、自己検出・自己修復手段は、上記表示パネルに表示すべき画像が不連続に切り替わるときに、駆動回路の不良を検出する処理を実行する。例えば、自己検出・自己修復手段は、１チャンネルから２チャンネルへの切替によって、１チャンネルの画像信号に基づく表示が中断する場合に、表示パネルに表示すべき画像が不連続に切り替わるときに、駆動回路の不良を検出する処理を実行する。また、例えば、自己検出・自己修復手段は、番組からＣＭへの移行によって、番組を表す画像信号に基づく表示が中断する場合に、表示パネルに表示すべき画像が不連続に切り替わるときに、駆動回路の不良を検出する処理を実行する。 And according to said structure, a self-detection / self-repair means performs the process which detects the defect of a drive circuit, when the image which should be displayed on the said display panel switches discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously. A process for detecting a circuit defect is executed. Further, for example, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM. A process for detecting a circuit defect is executed.
　これにより、本発明に係る表示装置によれば、表示装置の動作において、表示に影響のない期間に、自己検出の処理を実行することができる。つまり、本発明に係る表示装置は、表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出する処理を実行するが、表示装置の画面において現在表示中の内容が一旦途切れるタイミングで、自己検出の処理を実行するため、ユーザに違和感を感じさせることがない。したがって、本発明に係る表示装置によれば、ユーザの視聴を妨げずに適切なタイミングにおいて、自己検出および自己修復の処理を実行することが可能となり、ユーザにとっての利便性を向上させることができる。 Thereby, according to the display device according to the present invention, in the operation of the display device, the self-detection process can be executed in a period that does not affect the display. In other words, the display device according to the present invention executes a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the current display content is temporarily interrupted on the screen of the display device. Since the self-detection process is executed at the timing, the user does not feel uncomfortable. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
　本発明に係る表示装置は、表示パネルと、上記表示パネルに画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切り替えながら上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、上記自己検出・自己修復手段は、上記供給停止期間に、上記駆動回路の不良を検出する処理を実行することを特徴としている。 The display device according to the present invention includes a display panel, a supply period in which an image signal is supplied, and a supply stop period in which the supply of the image signal is stopped, among periods in which an image is displayed on the display panel. Drive circuit for driving the display panel while switching between them, and having self-detection / self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected The self-detecting / self-repairing means executes a process of detecting a defect of the driving circuit during the supply stop period.
　上記の構成によれば、駆動回路は、表示パネルに画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切替ながら、表示パネルを駆動する。そして、駆動回路は、駆動回路自身の不良を検出可能であり、検出した不良を修復する自己検出・自己修復手段とを有している。駆動回路は、自身の不良を検出し修復する処理を、表示パネルとの電気的な接続を切り離した状態で実行する。つまり、駆動回路は、表示パネルとの電気的接続を切り離して自身の不良を検出する（すなわち自己検出する）ことで、表示パネルに表示中の画像を表す階調データだけでなく、全ての階調データを用いて自己検出の処理を実行することができる。なお、画像は、静止画像であってもよいし、動画像すなわち映像であってもよい。 According to the above configuration, the drive circuit switches between the supply period in which the image signal is supplied and the supply stop period in which the supply of the image signal is stopped, during the period in which the image is displayed on the display panel. While driving the display panel. The drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure. The drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels. Self-detection processing can be executed using the key data. The image may be a still image or a moving image, that is, a video.
　そして、上記の構成によれば、自己検出・自己修復手段は、供給停止期間に、駆動回路の不良を検出する処理を実行する。例えば、自己検出・自己修復手段は、水平走査期間や垂直走査期間において、駆動回路の不良を検出する処理を実行する。 And according to the above configuration, the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit during the supply stop period. For example, the self-detecting / self-repairing unit executes processing for detecting a defect in the driving circuit in the horizontal scanning period and the vertical scanning period.
　これにより、本発明に係る表示装置によれば、表示装置に駆動において、表示に影響のない期間に、自己検出の処理を実行することができる。つまり、本発明に係る表示装置は、表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出する処理を実行するが、画像を表示中の表示パネルに画像信号の供給が行われないタイミングで、自己検出の処理を実行するため、表示パネルの駆動を妨げない。したがって、本発明に係る表示装置によれば、ユーザの視聴を妨げずに適切なタイミングにおいて、自己検出および自己修復の処理を実行することが可能となり、ユーザにとっての利便性を向上させることができる。 Thereby, according to the display device according to the present invention, it is possible to execute the self-detection process in a period in which the display device is driven and does not affect the display. That is, the display device according to the present invention performs a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the image signal is supplied to the display panel that is displaying an image. Since the self-detection process is executed at a timing that is not performed, driving of the display panel is not hindered. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
　本発明に係る表示装置は、上記の課題を解決するために、表示パネルと、上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、上記自己検出・自己修復手段は、上記表示パネルに表示すべき画像が不連続に切り替わるときに、上記駆動回路の不良を検出する処理を実行することを特徴としている。 In order to solve the above problems, a display device according to the present invention is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected. Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
　また、本発明に係る表示装置は、表示パネルと、上記表示パネルに画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切り替えながら上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、上記自己検出・自己修復手段は、上記供給停止期間に、上記駆動回路の不良を検出する処理を実行することを特徴としている。 Further, the display device according to the present invention includes a display panel, a supply period in which an image signal is supplied, and a supply stop in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel. A drive circuit for driving the display panel while switching a period, and having self-detection / self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected The self-detecting / self-repairing means is characterized by executing a process of detecting a defect of the driving circuit during the supply stop period.
　それゆえ、本発明に係る表示装置によれば、表示装置の画面において現在表示中の内容が一旦途切れるタイミングで、あるいは、画像を表示中の表示パネルに画像信号の供給が行われないタイミングで、自己検出の処理を実行するため、ユーザの視聴を妨げずに適切なタイミングにおいて、自己検出および自己修復の処理を実行することが可能となり、ユーザにとっての利便性を向上させることができる。 Therefore, according to the display device according to the present invention, at the timing when the content currently displayed on the screen of the display device is temporarily interrupted, or at the timing when the image signal is not supplied to the display panel displaying the image, Since the self-detection process is executed, it is possible to execute the self-detection and self-repair processes at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved.
本発明の実施の一形態に係る、液晶テレビジョンの構成を示すブロックを示す。1 is a block diagram illustrating a configuration of a liquid crystal television according to an embodiment of the present invention. 本発明の実施の一形態に係る、表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus based on one Embodiment of this invention. 液晶テレビジョンに含まれる集積回路を構成する出力回路ブロックに異常が発生した場合の表示の一例を示す図である。It is a figure which shows an example of a display when abnormality generate | occur | produces in the output circuit block which comprises the integrated circuit contained in a liquid crystal television. 液晶テレビジョンにおいて、チャンネル変更時に自己検出および自己修復動作を行う様子を示す図であり、（ａ）はチャンネル変更前の様子を示す図であり、（ｂ）は自己検出動作中の様子を示す図であり、（ｃ）はチャンネル変更後の様子を示す図である。In a liquid crystal television, it is a figure which shows a mode that self-detection and a self-repair operation | movement are performed at the time of a channel change, (a) is a figure which shows the mode before a channel change, (b) shows a mode during self-detection operation | movement. It is a figure and (c) is a figure which shows the mode after a channel change. 液晶テレビジョンにおいて、ＣＭ移行時に自己検出および自己修復動作を行う様子を行う図であり、（ａ）はＣＭ移行前の様子を示す図であり、（ｂ）は自己検出動作中の様子を示す図であり、（ｃ）はＣＭ中の様子を示す図であり、（ｄ）は番組再開時の様子を示す図である。In a liquid crystal television, it is a figure which performs a mode that self-detection and a self-repair operation are performed at the time of CM shift, (a) is a diagram showing a state before CM shift, and (b) is a state during a self-detection operation. It is a figure, (c) is a figure which shows the mode in CM, (d) is a figure which shows the mode at the time of program resumption. 液晶テレビジョンの表示パネルを駆動するための信号を表すタイミングチャートである。It is a timing chart showing the signal for driving the display panel of a liquid crystal television. 本発明の実施の一形態に係る、表示駆動用半導体集積回路の構成を示す説明図である。It is explanatory drawing which shows the structure of the semiconductor integrated circuit for a display drive based on one Embodiment of this invention. 本発明の実施の一形態に係る、動作確認テストの１つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 1st procedure of the operation check test based on one Embodiment of this invention. 本発明の実施の一形態に係る、動作確認テストの２つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 2nd procedure of the operation confirmation test based on one Embodiment of this invention. 本発明の実施の一形態に係る、動作確認テストの３つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 3rd procedure of the operation check test based on one Embodiment of this invention. 本発明の実施の一形態に係る、動作確認テストの４つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 4th procedure of the operation confirmation test based on one Embodiment of this invention. 本発明の実施の一形態に係る、動作確認テストの５つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 5th procedure of the operation confirmation test based on one Embodiment of this invention. 本発明の実施の一形態に係る、不良の出力回路を、予備の出力回路に切り替える手順を示すフローチャート図である。It is a flowchart figure which shows the procedure which switches the defective output circuit to the backup output circuit based on one Embodiment of this invention. 本発明の実施の一形態に係る、表示装置の電源投入から、動作確認テストを行い通常動作に移行するまでの手順を示すフローチャート図である。It is a flowchart figure which shows the procedure from the power-on of a display apparatus to the normal operation according to one embodiment of the present invention. 本発明の実施の一形態に係る、オペアンプの動作確認を行うための回路構成を示す説明図である。It is explanatory drawing which shows the circuit structure for performing operation | movement confirmation of the operational amplifier based on one Embodiment of this invention. 本発明の他の実施形態に係る、表示駆動用半導体集積回路の構成を示す説明図である。It is explanatory drawing which shows the structure of the semiconductor integrated circuit for a display drive based on other embodiment of this invention. 本発明の他の実施形態に係る、動作確認テストの１つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 1st procedure of the operation check test based on other embodiment of this invention. 本発明の他の実施形態に係る、動作確認テストの２つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 2nd procedure of the operation confirmation test based on other embodiment of this invention. 本発明の他の実施形態に係る、動作確認テストの３つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 3rd procedure of the operation confirmation test based on other embodiment of this invention. 本発明の他の実施形態に係る、動作確認テストの４つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 4th procedure of the operation confirmation test based on other embodiment of this invention. 本発明の他の実施形態に係る、動作確認テストの５つ目の手順を示すフローチャート図である。It is a flowchart figure which shows the 5th procedure of the operation confirmation test based on other embodiment of this invention. 本発明の他の実施形態に係る、不良の出力回路を、予備の出力回路に切り替える手順を示すフローチャート図である。It is a flowchart figure which shows the procedure which switches the defective output circuit to the backup output circuit based on other Embodiment of this invention. 本発明のさらに他の実施形態に係る、表示装置の概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the display apparatus based on further another embodiment of this invention. 本発明のさらに他の実施形態に係る、表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus based on further another embodiment of this invention. 本発明のさらに他の実施形態に係る、表示装置の電源投入から、動作確認テストを行い通常動作に移行するまでの手順を示すフローチャート図である。It is a flowchart figure which shows the procedure from the power-on of a display apparatus to the normal operation according to further another embodiment of the present invention after performing an operation check test. 本発明のさらに他の実施形態に係る、表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus based on further another embodiment of this invention. 本発明の実施の一形態に係る、テレビジョンシステムの構成を示すブロック図である。It is a block diagram which shows the structure of the television system based on one Embodiment of this invention. 本発明の実施の一形態に係るタイムチャート図であり、（ａ）～（ｆ）は、本発明の実施の一形態に係る、表示装置に入力する走査信号、映像信号、画素電極の電圧値を示す、タイムチャート図である。FIG. 3 is a time chart according to an embodiment of the present invention, in which (a) to (f) are a scanning signal, a video signal, and a voltage value of a pixel electrode input to a display device according to an embodiment of the present invention. FIG. 本発明の実施の一形態に係る、動作判定回路の構成を示すブロック図である。It is a block diagram which shows the structure of the operation | movement determination circuit based on one Embodiment of this invention. 本発明の実施の一形態に係る、正常動作時における、集積回路の電源電流値を検出および記憶する処理を示す、フローチャート図である。It is a flowchart figure which shows the process which detects and memorize | stores the power supply current value of an integrated circuit at the time of normal operation based on one Embodiment of this invention. 本発明の実施の一形態に係る、集積回路に供給される電源電流値より、集積回路の動作不良を検出する処理を示す、フローチャート図である。It is a flowchart figure which shows the process which detects the malfunctioning of an integrated circuit from the power supply current value supplied to an integrated circuit based on one Embodiment of this invention. 従来例における、表示駆動用半導体集積回路の構成を示す説明図である。It is explanatory drawing which shows the structure of the semiconductor integrated circuit for a display drive in a prior art example.
　以下、本発明に係る実施の形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　〔実施形態１〕
　本発明の第１の実施形態について、図１～図１５を参照して以下に説明する。 Embodiment 1
A first embodiment of the present invention will be described below with reference to FIGS.
　（液晶テレビジョン４００）
　表示用駆動回路を使用した表示装置の代表的なものとしては液晶テレビに代表される薄型テレビを挙げることが出来る。液晶テレビ（液晶表示装置）は、表示パネルに半導体集積回路（ＬＳＩ）で作成した駆動回路を複数実装し、表示を行っている。このような表示装置において、表示用駆動回路に不具合が生じた場合、直接表示不良として、ユーザに認識される。このような不具合が生じた場合、迅速に不具合箇所の修理を行う必要があり、できればユーザが使用している場所にて短時間で修理を終えることが望ましい。表示信号を処理するようなコントロール基板であれば、表示パネルとコネクタで接続されているため交換は容易であるが、表示駆動用回路はコネクタ等で接続されておらず、表示パネルに直接接続されているため、ユーザが製品を使用している場所での交換は困難である。 (LCD television 400)
As a typical display device using a display driving circuit, a thin-screen television typified by a liquid crystal television can be given. 2. Description of the Related Art A liquid crystal television (liquid crystal display device) performs display by mounting a plurality of drive circuits created with a semiconductor integrated circuit (LSI) on a display panel. In such a display device, when a defect occurs in the display drive circuit, the user recognizes it as a direct display defect. When such a problem occurs, it is necessary to repair the defective part promptly, and it is desirable that the repair be completed in a short time at the place where the user is using if possible. If it is a control board that processes display signals, it is easy to replace because it is connected to the display panel with a connector, but the display drive circuit is not connected with a connector etc., but is connected directly to the display panel. Therefore, it is difficult to replace the product at a place where the user is using the product.
　このため、本出願人は、表示用駆動回路自身の不具合に対する自己診断自己修復機能（自己検出および自己修復機能）を有する表示駆動用回路を提案している（例えば、特願２００８－１３０８４８、特願２００８－０４８６４０、特願２００８－０４８６３９、および特願２００８－０５４１３０：いずれも本願出願前の確認時点で未公開）。 For this reason, the present applicant has proposed a display driving circuit having a self-diagnosis self-repair function (self-detection and self-repair function) for a failure of the display drive circuit itself (for example, Japanese Patent Application No. 2008-130848, Application Nos. 2008-048640, Japanese Patent Application No. 2008-048639, and Japanese Patent Application No. 2008-054130: all unpublished at the time of confirmation prior to the filing of this application.
　図１は、本発明に係る液晶テレビジョン４００の構成を示すブロックを示す。図１に示すとおり、液晶テレビジョン４００は、ＴＦＴ－ＬＣＤモジュール（表示部）９０、およびリモコンＩ／Ｆ４０１を含んで構成される。さらに、表示部９０は、ソースドライバ（駆動回路、集積回路）１０ａ、１０ｂ、ＴＦＴ－ＬＣＤパネル（表示パネル）８０、ゲートドライバ９９、およびコントローラ１００とを備えている。そして、ソースドライバ１０ａ、すなわち、集積回路１０ａ、１０ｂが、上述の自己検出および自己修復機能を有する表示用駆動用回路である。なお、以下では、単に集積回路１０またはソースドライバ１０と記載した場合、集積回路１０ａおよび１０ｂ、すなわち、ソースドライバ１０ａおよび１０ｂの総称を表しているものとする。 FIG. 1 shows a block diagram showing a configuration of a liquid crystal television 400 according to the present invention. As shown in FIG. 1, the liquid crystal television 400 includes a TFT-LCD module (display unit) 90 and a remote control I / F 401. Further, the display unit 90 includes source drivers (driving circuits, integrated circuits) 10a and 10b, a TFT-LCD panel (display panel) 80, a gate driver 99, and a controller 100. The source driver 10a, that is, the integrated circuits 10a and 10b is a display driving circuit having the above-described self-detection and self-repair functions. Hereinafter, when the integrated circuit 10 or the source driver 10 is simply described, the integrated circuits 10a and 10b, that is, the generic names of the source drivers 10a and 10b are represented.
　以下では、表示部９０における自己検出および自己修復の基本動作を説明した後、液晶テレビジョン４００における自己検出および自己修復の特徴的構成、すなわち、ユーザに故障ではないかと誤解を与えることなく自己検出および自己修復を実行可能な構成について、具体的に説明する。 In the following, after describing the basic operation of self-detection and self-repair in the display unit 90, the characteristic configuration of self-detection and self-repair in the liquid crystal television 400, that is, self-detection without giving the user a misunderstanding that it is a failure. A configuration capable of executing self-repair will be specifically described.
　（表示部９０）
　まず、図２を参照して、本発明の表示部９０の概略構成を説明する。図２は、表示部９０の概略構成を示すブロック図である。図２に示すように、表示部９０は、表示パネル８０と、外部より入力される階調データに基づき表示パネル８０を駆動する表示駆動用半導体集積回路（以下、集積回路またはソースドライバと呼称する）１０とを備えている。また、ソースドライバすなわち集積回路１０（駆動回路）は、切替回路６０（自己検出・自己修復手段、切替手段）、切替回路６１（自己検出・自己修復手段、切替手段）、出力回路ブロック３０（出力回路）、予備出力回路ブロック４０（予備出力回路）、および比較判定回路５０（比較手段、判定手段、自己検出・自己修復手段）を備えている。また、表示パネル８０は、集積回路１０からの階調電圧が印加される画素７０を備えている。 (Display unit 90)
First, the schematic configuration of the display unit 90 of the present invention will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the display unit 90. As shown in FIG. 2, the display unit 90 includes a display panel 80 and a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit or a source driver) that drives the display panel 80 based on gradation data input from the outside. ) 10. Further, the source driver, that is, the integrated circuit 10 (driving circuit) includes a switching circuit 60 (self-detection / self-repairing means, switching means), a switching circuit 61 (self-detection / self-repairing means, switching means), and an output circuit block 30 (output). Circuit), preliminary output circuit block 40 (preliminary output circuit), and comparison determination circuit 50 (comparison means, determination means, self-detection / self-repair means). The display panel 80 includes a pixel 70 to which the gradation voltage from the integrated circuit 10 is applied.
　次に、表示部９０における基本動作を説明する。まず、表示部９０は、基本動作として、２つの基本動作を有している。具体的には、表示部９０は、外部より入力された階調データを、集積回路１０が階調電圧（出力信号）に変換し、この階調電圧に基づいて映像を表示パネル８０に表示する通常動作と、集積回路１０に含まれる出力回路ブロック３０が不良か否かを検出し、出力回路ブロック３０に不良があった場合に、集積回路１０が自身を自己修復する自己検出修復動作との、２つの基本動作を有している。 Next, the basic operation in the display unit 90 will be described. First, the display unit 90 has two basic operations as basic operations. Specifically, in the display unit 90, the integrated circuit 10 converts gradation data input from the outside into a gradation voltage (output signal), and displays an image on the display panel 80 based on the gradation voltage. A normal operation and a self-detection / repair operation in which the integrated circuit 10 detects whether or not the output circuit block 30 included in the integrated circuit 10 is defective and the output circuit block 30 is defective. It has two basic operations.
　以下に、集積回路１０が行う、自己検出修復動作の概略について説明する。まず、自己検出修復動作を行う場合、出力回路ブロック３０と予備出力回路ブロック４０とに、外部より切替回路６１を介して動作確認用の階調データが入力される。 Hereinafter, an outline of the self-detection repair operation performed by the integrated circuit 10 will be described. First, when performing a self-detection repair operation, gradation data for operation confirmation is input to the output circuit block 30 and the spare output circuit block 40 from the outside via the switching circuit 61.
　出力回路ブロック３０および予備出力回路ブロック４０の各々は、入力された階調データを階調電圧に変換し、比較判定回路に出力する。比較判定回路５０は、出力回路ブロックからの階調電圧と、予備出力回路ブロックからの階調電圧とを比較し、この比較結果に基づき、出力回路ブロックが不良か否かを判定する。 Each of the output circuit block 30 and the spare output circuit block 40 converts the input gradation data into a gradation voltage and outputs the gradation voltage to the comparison determination circuit. The comparison determination circuit 50 compares the gradation voltage from the output circuit block with the gradation voltage from the standby output circuit block, and determines whether or not the output circuit block is defective based on the comparison result.
　さらに、比較判定回路５０は、出力回路ブロックが不良か否かを示す判定結果（不良検出情報）を、切替回路６１および切替回路６０に出力する。切替回路６１は、比較判定回路５０からの判定結果に基づいて、外部からの階調データの出力先を切り替える。一方、切替回路６０は、出力回路ブロック３０および予備出力回路ブロック４０の各々より階調電圧が入力され、比較判定回路からの判定結果に基づいて、入力された階調電圧の中から、表示パネル８０に出力する階調電圧を選択する。 Furthermore, the comparison / determination circuit 50 outputs a determination result (failure detection information) indicating whether or not the output circuit block is defective to the switching circuit 61 and the switching circuit 60. The switching circuit 61 switches the output destination of the gradation data from the outside based on the determination result from the comparison determination circuit 50. On the other hand, the switching circuit 60 receives the gradation voltage from each of the output circuit block 30 and the spare output circuit block 40, and displays the display panel from the inputted gradation voltages based on the determination result from the comparison determination circuit. The gradation voltage to be output to 80 is selected.
　より具体的に説明すると、切替回路６１は、出力回路ブロック３０が不良であることを示す判定結果が入力されると、不良と判定された出力回路ブロック３０に出力される階調データと同じ階調データを、予備出力回路ブロック４０にも入力する。一方、切替回路６０は、出力回路ブロック３０が不良であることを示す判定結果が入力されると、不良と判定された出力回路ブロック３０からの階調電圧の代わりに、予備出力回路４０からの階調電圧を、表示パネル８０に出力する。これにより、集積回路１０は、出力回路ブロック３０が不良になったとしても、代わりに予備出力回路ブロックを用いて、正常な階調電圧を表示パネル８０に出力することが可能となる。 More specifically, when the determination result indicating that the output circuit block 30 is defective is input, the switching circuit 61 has the same level as the gradation data output to the output circuit block 30 determined to be defective. The tone data is also input to the spare output circuit block 40. On the other hand, when a determination result indicating that the output circuit block 30 is defective is input to the switching circuit 60, instead of the gradation voltage from the output circuit block 30 determined to be defective, the switching circuit 60 outputs from the standby output circuit 40. The gradation voltage is output to the display panel 80. As a result, even if the output circuit block 30 becomes defective, the integrated circuit 10 can output a normal gradation voltage to the display panel 80 using the spare output circuit block instead.
　以上のように、本実施形態の集積回路１０は、比較判定回路５０、切替回路６０および切替回路６１を備えることによって、自身の不具合を検出し、さらに、自身の不具合を自己修復することが可能となる。言い換えれば、集積回路１０は、自身の不具合を検出し、さらに、自身の不具合を自己修復する自己修復回路（自己修復手段）を備えることになる。なお、ソースドライバ１０すなわち集積回路１０の構成や自己検出および自己修復動作の詳細については後述する。 As described above, the integrated circuit 10 according to the present embodiment includes the comparison determination circuit 50, the switching circuit 60, and the switching circuit 61, so that it can detect its own defect and can self-repair itself. It becomes. In other words, the integrated circuit 10 includes a self-healing circuit (self-repairing means) that detects its own fault and further self-heals the fault. The configuration of the source driver 10, that is, the integrated circuit 10, and details of self-detection and self-repair operations will be described later.
　（表示の不具合）
　図３は、液晶テレビジョン４００に含まれる集積回路１０を構成する出力回路ブロック３０に異常が発生した場合の表示の一例を示す図である。図３に示すとおり、出力回路ブロック３０に異常がある場合、表示に縦線が入る。 (Display defect)
FIG. 3 is a diagram illustrating an example of a display when an abnormality occurs in the output circuit block 30 included in the integrated circuit 10 included in the liquid crystal television 400. As shown in FIG. 3, when there is an abnormality in the output circuit block 30, a vertical line appears on the display.
　通常、ソースドライバは、ＬＳＩとして出荷されるときに、十分機能テストが行われ、表示装置においても表示の確認が十分に行われるため、表示の異常が発生する可能性は非常に低い。つまり、表示装置の通常使用の範囲では、表示不具合が起こる可能性は非常に低い。 Usually, when a source driver is shipped as an LSI, a sufficient function test is performed, and display is sufficiently confirmed even in a display device. Therefore, the possibility of a display abnormality occurring is very low. That is, in the range of normal use of the display device, the possibility of display failure is very low.
　しかしながら、突発的な要因、例えばドライバ製造時の異物混入や傷に起因して出力信号の経路に発生したダメージが、表示装置の使用期間において拡大し、ソースドライバの出力回路に異常が発生し、表示不良を起こす場合がある。このようなことがあった場合、表示用駆動装置の自己修復機能により、図３の縦スジが消えるように、瞬時に自己修復動作を実行する。 However, the damage that occurred in the path of the output signal due to sudden factors such as foreign matter contamination and scratches during the manufacture of the driver expanded during the usage period of the display device, and the output circuit of the source driver became abnormal, Display failure may occur. In such a case, the self-recovering operation is instantaneously executed by the self-recovery function of the display driving device so that the vertical stripe in FIG. 3 disappears.
　（チャンネル切替時の自己検出）
　液晶テレビジョン４００は、チャンネル切替時に自己検出および自己修復を実行する。以下に、チャンネル変更時の自己検出について、より詳細に説明する。図４は、液晶テレビジョン４００において、チャンネル変更時に自己検出および自己修復動作を行う様子を示す図であり、図４の（ａ）はチャンネル変更前の様子を示す図であり、図４の（ｂ）は自己検出動作中の様子を示す図であり、図４の（ｃ）はチャンネル変更後の様子を示す図である。 (Self-detection when switching channels)
The liquid crystal television 400 performs self-detection and self-repair when switching channels. Hereinafter, the self-detection at the time of channel change will be described in more detail. FIG. 4 is a diagram showing how the liquid crystal television 400 performs self-detection and self-repair operations when a channel is changed. FIG. 4A is a diagram showing a state before the channel is changed. FIG. 4B is a diagram showing a state during the self-detection operation, and FIG. 4C is a diagram showing a state after the channel change.
　液晶テレビジョン４００では、ユーザがリモコン４０２を用いてチャンネル変更の操作を行なうと、リモコンＩ／Ｆ４０１を介して選局入力信号を受信し、選局入力信号が選局電圧に変換され、チューナー（放送受信手段）に供給される。チューナーは、選局電圧に対応するチャンネルの放送信号を受信する。そして、液晶テレビジョン４００は、チューナーが受信しているチャンネルの番組を表示する。 In the liquid crystal television 400, when the user performs a channel change operation using the remote controller 402, a channel selection input signal is received via the remote control I / F 401, the channel selection input signal is converted into a channel selection voltage, and a tuner ( Broadcast receiving means). The tuner receives a broadcast signal of a channel corresponding to the channel selection voltage. Then, the liquid crystal television 400 displays the program of the channel received by the tuner.
　図４に示す例では、液晶テレビジョン４００は、はじめに、図４の（ａ）に示すとおり、１ｃｈ（１チャンネル）の番組を受信して表示している。そして、ユーザがリモコン４０２を用いて２ｃｈ（２チャンネル）へのチャンネル切替操作を行うと、液晶テレビジョン４００では、自己検出動作が開始される。このとき、図４の（ｂ）に示すように画面の表示が消える。 In the example shown in FIG. 4, the liquid crystal television 400 first receives and displays a 1ch (one channel) program as shown in FIG. When the user performs a channel switching operation to 2ch (2 channels) using the remote controller 402, the liquid crystal television 400 starts a self-detecting operation. At this time, the display on the screen disappears as shown in FIG.
　つまり、液晶テレビジョン４００では、１ｃｈから２ｃｈへのチャンネルの切替時、すなわち、１ｃｈの番組を表す画像信号に基づく表示が中断するときに、ソースドライバ１０の自己検出が行われる。より具体的には、液晶テレビジョン４００では、図１に示すコントローラ１００が、ユーザの選局操作、すなわち、１ｃｈから２ｃｈへの切替を感知する。換言すれば、コントローラ１００（画像切替手段）は、チューナーから表示パネル８０に供給される画像信号が、１ｃｈの番組を表す画像信号から、２ｃｈの番組を表す画像信号に切り替わることによって、表示パネル８０における１ｃｈの番組の表示が中断することを感知する。 That is, in the liquid crystal television 400, the self-detection of the source driver 10 is performed when the channel is switched from 1ch to 2ch, that is, when the display based on the image signal representing the 1ch program is interrupted. More specifically, in the liquid crystal television 400, the controller 100 shown in FIG. 1 senses the user's channel selection operation, that is, switching from 1ch to 2ch. In other words, the controller 100 (image switching means) switches the image signal supplied from the tuner to the display panel 80 from the image signal representing the 1ch program to the image signal representing the 2ch program, thereby causing the display panel 80 to display. It is detected that the display of the 1ch program is interrupted.
　そして、コントローラ１００がチャンネルの切替を感知すると、ソースドライバ１０に自己検出の処理の実行を指示し、ソースドライバ１０は、自己検出の処理を実行する。すなわち、液晶テレビジョン４００では、表示パネル８０において、１ｃｈの番組を表す画像信号に基づく表示から、２ｃｈの番組を表す画像信号に基づく表示への切替を行うために、１ｃｈの番組を表す画像信号に基づく表示が中断するときに、ソースドライバ１０の自己検出の処理を実行する。このとき、例えば、コントローラ１００は、リモコンＩ／Ｆを介して入力される選局入力信号に基づいて、ソースドライバ１０に自己検出の処理を指示する。 When the controller 100 senses channel switching, it instructs the source driver 10 to execute self-detection processing, and the source driver 10 executes self-detection processing. That is, in the liquid crystal television 400, in order to switch from display based on an image signal representing a 1ch program on the display panel 80 to display based on an image signal representing a 2ch program, an image signal representing a 1ch program is displayed. When the display based on is interrupted, the self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 instructs the source driver 10 to perform self-detection processing based on a channel selection input signal input via the remote control I / F.
　なお、図４に示す例では、１ｃｈから２ｃｈへのチャンネル切替の例を示しているが、例えば、１ｃｈの表示中に、ユーザが再度１ｃｈを選局する操作を行った場合にも、同様に、１ｃｈの番組を表す画像信号に基づく表示が一旦中断する。そして、この場合にも、ソースドライバ１０は、例えば、選局入力信号に基づくコントローラ１００からの指示に従って、自己検出の処理を実行する。 Note that the example shown in FIG. 4 shows an example of channel switching from 1ch to 2ch. For example, when the user performs an operation to select 1ch again during display of 1ch, the same applies. The display based on the image signal representing the 1ch program is temporarily interrupted. Also in this case, the source driver 10 executes self-detection processing in accordance with an instruction from the controller 100 based on the channel selection input signal, for example.
　この自己検出の処理が行われている間は、図４の（ｂ）に示すように画面表示が行われない。しかしながら、チャンネル切替時であるため、短い期間であれば、画面表示が行われなくても、ユーザに対して、違和感を感じさせることがない。特に、液晶テレビジョン４００がデジタルテレビの場合、映像信号や音声信号は符号化されてデジタル放送波として伝送されるため、受信したデジタル放送波に含まれる圧縮された映像信号や音声信号を復号化する必要がある。このため、信号を復号化する処理に数秒の時間を要することになり、ユーザがチャンネルの切り替え操作を行った場合、指定されたチャンネルの番組は即時には表示されずに、少しの期間、黒画面が表示される。したがって、このタイミングで自己検出を行えば、ユーザは違和感を感じない。つまり、液晶テレビジョン４００は、表示に影響のない期間に、自己検出を完了する。 While the self-detection process is being performed, no screen display is performed as shown in FIG. However, since the channel is switched, the user does not feel uncomfortable even if the screen display is not performed for a short period. In particular, when the liquid crystal television 400 is a digital television, the video signal and audio signal are encoded and transmitted as a digital broadcast wave, so that the compressed video signal and audio signal included in the received digital broadcast wave are decoded. There is a need to. For this reason, it takes a few seconds to decode the signal. When the user performs a channel switching operation, the program of the designated channel is not displayed immediately, but is displayed for a short period of time. Is displayed. Therefore, if self-detection is performed at this timing, the user does not feel uncomfortable. That is, the liquid crystal television 400 completes self-detection in a period that does not affect the display.
　その後、ソースドライバ１０において自己修復の処理を実行した後、液晶テレビジョン４００は、図４の（ｃ）に示すように、切替後の番組、すなわち、２ｃｈの番組を表示する。 Thereafter, after the self-repair processing is executed in the source driver 10, the liquid crystal television 400 displays the switched program, that is, the 2ch program, as shown in FIG.
　（ＣＭ移行時の自己検出）
　液晶テレビジョン４００は、ＣＭ移行時に自己検出および自己修復を実行する。以下に、ＣＭ移行時の自己検出について、より詳細に説明する。図５は、液晶テレビジョン４００において、ＣＭ移行時に自己検出および自己修復動作を行う様子を行う図であり、図５の（ａ）はＣＭ移行前の様子を示す図であり、図５の（ｂ）は自己検出動作中の様子を示す図であり、図５の（ｃ）はＣＭ中の様子を示す図であり、図５の（ｄ）は番組再開時の様子を示す図である。 (Self-detection when moving to CM)
The liquid crystal television 400 performs self-detection and self-repair at the time of CM transition. Hereinafter, self-detection at the time of CM migration will be described in more detail. FIG. 5 is a diagram illustrating a state in which the liquid crystal television 400 performs self-detection and self-repair operations during the transition to CM. FIG. 5A illustrates a state before the transition to CM. FIG. 5B is a diagram showing a state during the self-detection operation, FIG. 5C is a diagram showing a state during the CM, and FIG. 5D is a diagram showing a state when the program is resumed.
　図５に示す例では、液晶テレビジョン４００は、はじめに、図５の（ａ）に示すとおり、１ｃｈの放送を受信し、１ｃｈの放送に含まれる番組を表示している。そして、１ｃｈの放送において、番組からＣＭへ移行するとき、液晶テレビジョン４００では、自己検出動作が開始される。このとき、図５の（ｂ）に示すように画面の表示が消える。 In the example shown in FIG. 5, the liquid crystal television 400 first receives a 1ch broadcast and displays a program included in the 1ch broadcast, as shown in FIG. In the 1ch broadcast, when the program shifts to CM, the liquid crystal television 400 starts a self-detection operation. At this time, the display on the screen disappears as shown in FIG.
　つまり、液晶テレビジョン４００では、番組からＣＭへの移行時、すなわち、番組を表す画像信号に基づく表示が中断するときに、ソースドライバ１０の自己検出が行われる。より具体的には、液晶テレビジョン４００では、図１に示すコントローラ１００が、番組からＣＭへの移行を感知する。換言すれば、コントローラ１００（画像切替手段）は、チューナーから表示パネル８０に供給される画像信号が、番組を表す画像信号から、ＣＭを表す画像信号に切り替わることによって、表示パネル８０における番組の表示が中断することを感知する。 That is, in the liquid crystal television 400, the self-detection of the source driver 10 is performed at the time of transition from the program to the CM, that is, when the display based on the image signal representing the program is interrupted. More specifically, in the liquid crystal television 400, the controller 100 shown in FIG. 1 senses a transition from a program to a CM. In other words, the controller 100 (image switching means) displays the program on the display panel 80 by switching the image signal supplied from the tuner to the display panel 80 from the image signal representing the program to the image signal representing the CM. Senses that it is interrupted.
　そして、コントローラ１００が番組からＣＭへの移行を感知すると、ソースドライバ１０に自己検出の処理の実行を指示し、ソースドライバ１０は、自己検出の処理を実行する。すなわち、液晶テレビジョン４００では、表示パネル８０において、番組を表す画像信号に基づく表示から、ＣＭを表す画像信号に基づく表示へ移行するために、番組を表す画像信号に基づく表示が中断するときに、ソースドライバ１０の自己検出の処理を実行する。このとき、例えば、コントローラ１００は、シーン検出を行い、その結果に基づいてＣＭを検知し、ソースドライバ１０に自己検出の処理を指示する。シーン検出とは、無音状態やステレオ／モノラル音声の検出だけでなく、音楽と会話の境などの「音の切り替わり」や場面変化が大きい「映像の切り替わり」を検出する機能である。シーン検出は、例えば、ハードディスクデコーダー等でＣＭ部分をチャプター分割するときなどに用いられる手法である。 Then, when the controller 100 senses the transition from the program to the CM, the source driver 10 is instructed to execute the self-detection process, and the source driver 10 executes the self-detection process. That is, in the liquid crystal television 400, when the display based on the image signal representing the program is interrupted on the display panel 80 in order to shift from the display based on the image signal representing the program to the display based on the image signal representing the CM. The self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 performs scene detection, detects a CM based on the result, and instructs the source driver 10 to perform self-detection processing. Scene detection is a function that detects not only silence and stereo / monaural audio, but also “sound switching” such as the boundary between music and conversation and “video switching” with large scene changes. Scene detection is a technique used when, for example, a CM part is chapter-divided by a hard disk decoder or the like.
　この自己検出の処理が行われている間は、図５の（ｂ）に示すように画面表示が行われない。しかしながら、ＣＭ移行時であるため、これまで表示されていた番組とは内容が完全に変わるため、短い期間であれば、画面表示が行われなくても、ユーザに対して、違和感を感じさせることがない。 During the self-detection process, no screen display is performed as shown in FIG. However, since it is at the time of CM transition, the content completely changes from the program that has been displayed so far, so that the user feels uncomfortable even if screen display is not performed for a short period of time. There is no.
　そして、ソースドライバ１０において自己修復の処理を実行した後、液晶テレビジョン４００は、図４の（ｃ）に示すように、ＣＭを表示する。その後、液晶テレビジョン４００では、図４の（ｄ）に示すように、番組が再開され、表示がＣＭから番組に移行する。 Then, after executing the self-repair process in the source driver 10, the liquid crystal television 400 displays a CM as shown in FIG. Thereafter, in the liquid crystal television 400, as shown in FIG. 4D, the program is resumed, and the display shifts from the CM to the program.
　（複数工程の自己検出処理）
　ところで、詳細については後述するが、自己検出の処理は、複数の工程を含んでいる場合がある。この場合、液晶テレビジョン４００は、１回のチャンネルの切替において、自己修復の処理に含まれる全ての工程を実行する構成であってもよい。あるいは、液晶テレビジョン４００は、番組からＣＭへの１回の移行において、自己修復の処理に含まれる全ての工程を実行する構成であってもよい。 (Multi-step self-detection process)
Incidentally, although details will be described later, the self-detection process may include a plurality of steps. In this case, the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one channel switching. Alternatively, the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one transition from a program to a CM.
　また、自己検出の処理に含まれる全工程が完了するまでに長時間を要し、画面表示が行われない期間（すなわち黒画面の期間）が長くなってしまう場合には、自己検出に含まれる工程を分割し、数回のチャネル変更で自己検出処理に含まれる全ての工程を完了するようにしても良い。 In addition, if it takes a long time to complete all the steps included in the self-detection process and the period during which screen display is not performed (that is, the period of the black screen) becomes long, it is included in self-detection. The process may be divided and all the processes included in the self-detection process may be completed by changing the channel several times.
　つまり、自己修復の処理を、１つ以上の工程を含む複数の工程群に分割し、１回のチャンネル切替において、工程群を１つずつ実行する構成であってもよい。これにより、１回のチャンネル変更時に実行する自己検出処理の時間を短縮し、チャンネル切替の操作後、画面表示が行われない期間があまりにも長くなってしまうような事態を避けることができる。 That is, the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one channel switching. As a result, the time of the self-detection process executed at the time of one channel change can be shortened, and a situation in which the period during which screen display is not performed after the channel switching operation becomes too long can be avoided.
　また、あるいは、自己修復の処理を、１つ以上の工程を含む複数の工程群に分割し、番組からＣＭへの１回の移行において、工程群を１つずつ実行する構成であってもよい。これにより、番組からＣＭへの１回の移行時に実行する自己検出処理の時間を短縮し、ＣＭへの移行時に、画面表示が行われない期間があまりにも長くなってしまうような事態を避けることができる。 Alternatively, the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one transition from the program to the CM. . This shortens the time of the self-detection process that is executed at the time of the transition from the program to the CM, and avoids a situation in which the period during which the screen display is not performed becomes too long at the time of the transition to the CM. Can do.
　例えば、自己修復の処理に含まれる工程をｎ個の工程群に分割した場合、１回のチャンネル切替において、１つの工程群の処理、すなわち、自己検出の工程の１／ｎを行う。そして、ｎ回のチャンネル切替によって、ｎ個の工程群の処理、すなわち、自己検出の全工程を完了する。 For example, when the process included in the self-repair process is divided into n process groups, the process of one process group, that is, 1 / n of the self-detection process is performed in one channel switching. Then, by n times of channel switching, processing of n process groups, that is, all processes of self-detection are completed.
　また、例えば、自己修復の処理に含まれる工程をｎ個の工程群に分割した場合、１回の番組からＣＭへの切替において、１つの工程群の処理、すなわち、自己検出の工程の１／ｎを行う。そして、ｎ回のＣＭへの移行によって、ｎ個の工程群の処理、すなわち、自己検出の全工程を完了する。 Further, for example, when the process included in the self-repair process is divided into n process groups, the process of one process group, that is, 1/1 of the self-detection process is performed in switching from one program to CM. n. Then, the process of n process groups, that is, all processes of self-detection are completed by shifting to CM for n times.
　自己検出の処理が複数の工程を含んでいる場合の例としては、詳細については後述するが、デジタルデータによる多階調の表示装置の駆動回路における自己検出の処理において、１つの階調データに対して、数種類の工程（例えば、出力回路からの出力と予備出力回路からの出力とを比較する複数の比較工程など）が含まれる場合がある。この場合、数種類の工程が全ての階調データについて行われることになる。 As an example of the case where the self-detection process includes a plurality of steps, details will be described later. However, in the self-detection process in the drive circuit of the multi-gradation display device using digital data, one gradation data is obtained. On the other hand, there are cases where several types of steps (for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit) are included. In this case, several types of processes are performed for all the gradation data.
　そこで、このような駆動回路においては、１階調分の自己検出の処理に含まれる工程を分割して処理する構成であってもよい。例えば、液晶テレビジョン４００が、２５６階調の表示装置の場合、１階調分の自己検出の処理に含まれる工程を２つの工程郡に分割し、チャンネル切替ごとに、１つの工程群の処理を実行し、２回のチャンネル切替によって、１階調分の自己検出の処理を完了する構成とすることができる。あるいは、１階調分の自己検出の処理に含まれる工程を２つの工程郡に分割し、ＣＭ移行ごとに、１つの工程群の処理を実行し、２回のＣＭ移行によって、１階調分の自己検出の処理を完了する構成としてもよい。 Therefore, such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed. For example, when the liquid crystal television 400 is a 256-gradation display device, the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is performed for each channel switching. And the self-detection process for one gradation is completed by switching the channel twice. Alternatively, the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each CM transition, and one gradation is obtained by two CM transitions. The self-detection process may be completed.
　なお、自己検出処理に含まれる工程をどのように分割するかについては、特に限定されない。例えば、各工程群を構成する工程が予め設定され、その設定情報がメモリに記憶される構成であってもよい。この場合、ソースドライバ１０は、自己検出の処理を実行するときに、メモリから設定情報を読み出して、チャンネル切替ごとに、１つずつ工程群の処理を実行する。あるいは、各工程群を構成する工程の数が予め設定されていて、ソースドライバ１０は、チャンネル切替ごとに、設定された数の工程を実行する構成であってもよい。 Note that there is no particular limitation on how to divide the steps included in the self-detection process. For example, the process which comprises each process group may be preset, and the structure by which the setting information is memorize | stored in memory may be sufficient. In this case, when executing the self-detection process, the source driver 10 reads the setting information from the memory, and executes the process group process one by one for each channel switching. Alternatively, the number of processes constituting each process group may be set in advance, and the source driver 10 may be configured to execute the set number of processes for each channel switching.
　（水平・垂直ブランキング期間における自己検出）
　以下では、水平・垂直ブランキング期間における自己検出について説明する。上述のとおり、図１示す表示パネル８０は、コントローラ１００、ゲートドライバ９９、ソースドライ１０と共に、表示部９０を構成している。表示パネル８０は、複数本のゲートライン（走査信号線）と、これらに直交する複数本のソースライン（データ信号線）とを有し、これらのゲートラインとソースラインとの交差点に、それぞれ、スイッチング素子と液晶容量とによって構成される画素部を備えている。すなわち、表示パネル８０において、画素部は、マトリクス状に配置されている。 (Self-detection during horizontal and vertical blanking periods)
Hereinafter, self-detection in the horizontal / vertical blanking period will be described. As described above, the display panel 80 shown in FIG. 1 constitutes the display unit 90 together with the controller 100, the gate driver 99, and the source dry 10. The display panel 80 has a plurality of gate lines (scanning signal lines) and a plurality of source lines (data signal lines) orthogonal to the gate lines, and at the intersections of these gate lines and source lines, respectively. A pixel portion including a switching element and a liquid crystal capacitor is provided. That is, in the display panel 80, the pixel portions are arranged in a matrix.
　各画素部の画素スイッチング素子には、ゲート端子にゲートラインが接続され、ソース端子にソースラインが接続され、ドレイン端子に画素電気良くが接続されている。また、画素電極に対向して、全ての画素形成部に共通の対向電極が設けられており、画素電極と対向電極とは、液晶層を間に挟持して、液晶容量を形成している。 In the pixel switching element of each pixel portion, a gate line is connected to the gate terminal, a source line is connected to the source terminal, and a pixel electrical connection is connected to the drain terminal. In addition, a common counter electrode is provided in all the pixel formation portions so as to face the pixel electrode, and the pixel electrode and the counter electrode form a liquid crystal capacitor with a liquid crystal layer interposed therebetween.
　画素電極には、ソースラインおよびゲートラインとによって、表示する画像に応じた電位が与えられると共に、共通電極には、所定の電位が与えられる。この電圧印加によって、液晶層に対する光の透過量が制御されることによって、画像表示が行われる。なお、液晶層への電圧印加による光の透過量を制御するため、偏向板が用いられてもよい。 The pixel electrode is given a potential according to the image to be displayed by the source line and the gate line, and a predetermined potential is given to the common electrode. By applying this voltage, the amount of light transmitted to the liquid crystal layer is controlled, whereby image display is performed. Note that a deflection plate may be used to control the amount of light transmitted by applying a voltage to the liquid crystal layer.
　図６は、液晶テレビジョン４００の表示パネル８０を駆動するための信号を表すタイミングチャートである。図６に示す各種の制御信号がコントローラ１００に供給される。コントローラ１００は、図６に示す制御信号に基づいてゲートドライバ９９およびソースドライバ１０を制御する。そして、ゲートドライバ９９およびソースドライバ１０は、表示パネル８０に対してゲート信号およびデータ信号を供給する。これにより、表示パネル８０が駆動される。 FIG. 6 is a timing chart showing signals for driving the display panel 80 of the liquid crystal television 400. Various control signals shown in FIG. 6 are supplied to the controller 100. The controller 100 controls the gate driver 99 and the source driver 10 based on the control signal shown in FIG. The gate driver 99 and the source driver 10 supply a gate signal and a data signal to the display panel 80. Thereby, the display panel 80 is driven.
　図６において、期間５０１は垂直周期、期間５０２は垂直データ有効期間、期間５０３は垂直ブランキング期間、期間５０４は水平周期、期間５０５は水平データ有効期間、期間５０６は水平ブランキング期間であり、期間５０７は垂直同期信号が入力されてから、有効データの開始までの期間を示す垂直有効データ開始期間、期間５０８は水平同期信号が入力されてから、有効データの開始までの期間を示す水平有効データ開始期間を示す。 In FIG. 6, a period 501 is a vertical period, a period 502 is a vertical data valid period, a period 503 is a vertical blanking period, a period 504 is a horizontal period, a period 505 is a horizontal data valid period, and a period 506 is a horizontal blanking period. A period 507 is a vertical effective data start period indicating a period from the input of the vertical synchronization signal to the start of effective data, and a period 508 is a horizontal effective data indicating a period from the input of the horizontal synchronization signal to the start of effective data. Indicates the data start period.
　ゲートラインは、水平同期信号に基づいてゲートドライバ９９によって順次選択され、走査信号が供給される。そして、走査信号が供給されるゲートラインに接続されたスイッチング素子のゲートがＯＮとなり、該スイッチング素子に接続された画素電極にデータ信号を供給できるアクティブな状態となる。これにより、画素電極には、ソースラインを介してソースドライバ１０からデータ信号が供給され、画像を表す電圧が供給されることになる。 The gate lines are sequentially selected by the gate driver 99 based on the horizontal synchronization signal and supplied with the scanning signal. Then, the gate of the switching element connected to the gate line to which the scanning signal is supplied is turned ON, and an active state in which a data signal can be supplied to the pixel electrode connected to the switching element is obtained. As a result, a data signal is supplied to the pixel electrode from the source driver 10 via the source line, and a voltage representing an image is supplied.
　表示パネル８０においては、データ信号が画面の１ラインごとに左側の画素から右側の画素へ順次供給されて、走査線を形成することになる。そして、ブランキング期間、すなわち、帰線期間とは、画面を走査した走査線が元へ戻るための時間である。水平ブランキング期間５０６とは、画面の１ラインにおいて左から右へ走査後、再び、左へ戻る時間であり、垂直ブランキング期間５０３とは、画面の全ラインにおいて左上から順次左右に走査しながら右下へ走査した後、再度、左上に戻るまでの時間である。駆動するパネルの規格や駆動方法等により、図６に示す制御信号の期間は異なるが、一例としては、垂直ブランキング期間が１．１４ｍｓ、水平ブランキング期間は９μｓである。 In the display panel 80, a data signal is sequentially supplied from the left pixel to the right pixel for each line of the screen to form a scanning line. The blanking period, that is, the blanking period is the time for the scanning line that has scanned the screen to return to the original state. The horizontal blanking period 506 is a time for scanning from left to right in one line of the screen and then returning to the left again. The vertical blanking period 503 is performed while scanning from left to right sequentially from the upper left in all lines of the screen. This is the time from scanning to the lower right until returning to the upper left again. Although the control signal period shown in FIG. 6 varies depending on the standard of the panel to be driven, the driving method, and the like, as an example, the vertical blanking period is 1.14 ms and the horizontal blanking period is 9 μs.
　そして、これらの水平ブランキング期間５０６および垂直ブランキング期間５０３においては、データラインの駆動は行われず、表示パネル８０を構成する各画素には、データ信号が供給されない。つまり、これらの期間においては、各画素への画像データの書き込みは行われないため、表示用駆動素子であるソースドライバ１０の出力がハイインピーダンスであっても、画像の表示には影響しない。そこで、液晶テレビジョン４００では、これらの期間を利用して、ソースドライバ１０の自己検出・自己修復を行うようにする。 In the horizontal blanking period 506 and the vertical blanking period 503, the data line is not driven, and no data signal is supplied to each pixel constituting the display panel 80. In other words, since image data is not written to each pixel during these periods, even if the output of the source driver 10 that is a display driving element is high impedance, it does not affect image display. Therefore, in the liquid crystal television 400, the source driver 10 is self-detected and self-repaired using these periods.
　つまり、液晶テレビジョン４００では、データ信号（画像信号）の供給を停止している水平ブランキング期間５０６や垂直ブランキング期間５０３（供給停止期間）に、自己検出が行われる。より具体的には、液晶テレビジョン４００では、図１に示すコントローラ１００が、図６に示す制御信号の供給を受けて、水平ブランキング期間５０６または垂直ブランキング期間５０３を感知する。 That is, in the liquid crystal television 400, self-detection is performed during the horizontal blanking period 506 and the vertical blanking period 503 (supply stop period) during which the supply of data signals (image signals) is stopped. More specifically, in the liquid crystal television 400, the controller 100 shown in FIG. 1 senses the horizontal blanking period 506 or the vertical blanking period 503 in response to the supply of the control signal shown in FIG.
　そして、コントローラ１００（期間切替検知手段）が水平ブランキング期間５０６または垂直ブランキング期間５０３を感知すると、ソースドライバ１０に自己検出の処理の実行を指示し、ソースドライバ１０は、自己検出の処理を実行する。 When the controller 100 (period switching detection means) senses the horizontal blanking period 506 or the vertical blanking period 503, the controller 100 instructs the source driver 10 to execute self-detection processing, and the source driver 10 performs self-detection processing. Execute.
　水平ブランキング期間５０６に自己修復・自己検出を行った場合、１ライン毎に修復が行われるため、リアルタイムで自己検出・自己修復を行っているといえる。また、垂直ブランキング期間５０３に自己検出・自己修復を行った場合、１画面毎に修復が行われるため、やはり、リアルタイムで自己検出・自己修復を行っているといえる。つまり、液晶テレビジョン４００によれば、ユーザの視聴を妨げることなく、リアルタイムに自己検出の処理を実行できる。 When self-repair and self-detection are performed during the horizontal blanking period 506, it can be said that self-detection and self-repair are performed in real time because repair is performed for each line. In addition, when self-detection / self-repair is performed during the vertical blanking period 503, since the repair is performed for each screen, it can be said that self-detection / self-repair is performed in real time. That is, according to the liquid crystal television 400, the self-detection process can be executed in real time without disturbing the viewing of the user.
　なお、垂直ブランキング期間５０３においては、文字放送等他の情報がコントローラ１００等に供給される場合があるが、自己検出・自己修復は表示用駆動装置すなわちソースドライバ１０単独で行うことができるので、コントローラ１００等の他の装置には関係なく、自己検出・自己修復動作が可能である。 In the vertical blanking period 503, other information such as teletext may be supplied to the controller 100 or the like, but self-detection and self-restoration can be performed by the display driver, that is, the source driver 10 alone. Regardless of other devices such as the controller 100, self-detection and self-repair operations are possible.
　なお、垂直ブランキング期間は、垂直帰線期間とも呼ばれる。垂直帰線期間における自己検出の例については再度後述する。 The vertical blanking period is also called the vertical blanking period. An example of self-detection in the vertical blanking period will be described later again.
　ところで、上述したとおり、自己修復の処理は、複数の工程を含んでいる場合がある。この場合、液晶テレビジョン４００は、１回の水平ブランキング期間５０６において、自己修復の処理に含まれる全ての工程を実行する構成であってもよい。あるいは、液晶テレビジョン４００は、１回の垂直ブランキング期間５０３において、自己修復の処理に含まれる全ての工程を実行する構成であってもよい。 Incidentally, as described above, the self-repairing process may include a plurality of steps. In this case, the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one horizontal blanking period 506. Alternatively, the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one vertical blanking period 503.
　また、水平ブランキング期間に自己検出・自己修復を行う場合、表示用駆動装置すなわちソースドライバ１０の規模にもよるが、水平ブランキング期間５０６において、自己検出の処理に含まれる全ての工程が終了しないことも考えられる。この場合には、自己検出に含まれる工程を分割し、数回の水平ブランキング期間５０６で自己検出処理に含まれる全ての工程を完了するようにしても良い。 When self-detection / self-repair is performed during the horizontal blanking period, all processes included in the self-detection process are completed in the horizontal blanking period 506, depending on the scale of the display driving device, that is, the source driver 10. It is also possible not to. In this case, the steps included in the self-detection may be divided and all the steps included in the self-detection process may be completed in several horizontal blanking periods 506.
　また、垂直ブランキング期間に自己検出・自己修復を行う場合においても、同様に、垂直ブランキング期間５０３において、自己検出の処理に含まれる全ての工程が終了しないことも考えられる。この場合には、自己検出に含まれる工程を分割し、数回の水平ブランキング期間５０６で自己検出処理に含まれる全ての工程を完了するようにしても良い。 Also, when performing self-detection / self-repair during the vertical blanking period, it is also conceivable that all processes included in the self-detection process are not completed in the vertical blanking period 503. In this case, the steps included in the self-detection may be divided and all the steps included in the self-detection process may be completed in several horizontal blanking periods 506.
　つまり、自己修復の処理を、１つ以上の工程を含む複数の工程群に分割し、１回の水平ブランキング期間５０６または垂直ブランキング期間５０３において、工程群を１つずつ実行する構成であってもよい。これにより、１回の水平ブランキング期間５０６または垂直ブランキング期間５０３に実行する自己検出処理の時間を短縮し、チャンネル切替の操作後、画面表示が行われない期間があまりにも長くなってしまうような事態を避けることができる。 In other words, the self-repair process is divided into a plurality of process groups including one or more processes, and the process groups are executed one by one in one horizontal blanking period 506 or vertical blanking period 503. May be. As a result, the time of the self-detection process executed in one horizontal blanking period 506 or the vertical blanking period 503 is shortened, and the period during which the screen display is not performed after the channel switching operation becomes too long. Can avoid the situation.
　例えば、自己修復の処理に含まれる工程をｎ個の工程群に分割した場合、１回の水平ブランキング期間５０６または垂直ブランキング期間５０３において、１つの工程群の処理、すなわち、自己検出の工程の１／ｎを行う。そして、ｎ回の水平ブランキング期間５０６または垂直ブランキング期間５０３によって、ｎ個の工程群の処理、すなわち、自己検出の全工程を完了する。 For example, when the process included in the self-repair process is divided into n process groups, in one horizontal blanking period 506 or vertical blanking period 503, the process of one process group, that is, the self-detection process. Of 1 / n. Then, in n horizontal blanking periods 506 or vertical blanking periods 503, processing of n process groups, that is, all processes of self-detection are completed.
　自己検出の処理が複数の工程を含んでいる場合の例としては、詳細については後述するが、デジタルデータによる多階調の表示装置の駆動回路における自己検出の処理において、１つの階調データに対して、数種類の工程（例えば、出力回路からの出力と予備出力回路からの出力とを比較する複数の比較工程など）が含まれる場合がある。この場合、数種類の工程が全ての階調データについて行われることになる。 As an example of the case where the self-detection process includes a plurality of steps, details will be described later. However, in the self-detection process in the drive circuit of the multi-gradation display device using digital data, one gradation data is obtained. On the other hand, there are cases where several types of steps (for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit) are included. In this case, several types of processes are performed for all the gradation data.
　そこで、このような駆動回路においては、１階調分の自己検出の処理に含まれる工程を分割して処理する構成であってもよい。例えば、液晶テレビジョン４００が、２５６階調の表示装置の場合、１階調分の自己検出の処理に含まれる工程を２つの工程郡に分割し、水平ブランキング期間５０６ごとに、１つの工程群の処理を実行し、２回の水平ブランキング期間５０６によって、１階調分の自己検出の処理を完了する構成とすることができる。あるいは、１階調分の自己検出の処理に含まれる工程を２つの工程郡に分割し、垂直ブランキング５０３ごとに、１つの工程群の処理を実行し、２回の垂直ブランキング５０３によって、１階調分の自己検出の処理を完了する構成としてもよい。 Therefore, such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed. For example, when the liquid crystal television 400 is a 256-gradation display device, the process included in the self-detection process for one gradation is divided into two process groups, and one process is performed for each horizontal blanking period 506. The group processing is executed, and the self-detection processing for one gradation can be completed by two horizontal blanking periods 506. Alternatively, the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each vertical blanking 503, and the vertical blanking 503 is performed twice. The self-detection process for one gradation may be completed.
　（集積回路１０の構成）
　次に、図７を参照して、本発明に係るソースドライバ１０ａの構成について説明する。なお、上述したとおり、予備ソースドライバ１０ｂは、ソースドライバ１０ａよりも簡単な構成とすることもできるが、ソースドライバ１０ａと同様の構成とすることもできる。以下では、ソースドライバ１０ａと同様の自己検出および自己修復動作を実行可能な回路を、集積回路１０と呼称して説明する。 (Configuration of integrated circuit 10)
Next, the configuration of the source driver 10a according to the present invention will be described with reference to FIG. As described above, the spare source driver 10b can have a simpler configuration than the source driver 10a, but can also have the same configuration as the source driver 10a. Hereinafter, a circuit capable of performing self-detection and self-recovery operations similar to those of the source driver 10a will be referred to as an integrated circuit 10 and will be described.
　図７は、集積回路１０（駆動回路）の構成を示す説明図である。同図に示すように、集積回路１０は、階調データ入力端子（図示しない）より、データバスを介して、ｎ個の液晶駆動用信号出力端子ＯＵＴ１～ＯＵＴｎ（以下、出力端子ＯＵＴ１～ＯＵＴｎとする）のそれぞれに対応する階調データを入力するｎ個のサンプリング回路６－１～６－ｎ（以下、総称する場合は、サンプリング回路６とする）と、ｎ個のホールド回路７－１～７－ｎ（以下、総称する場合は、ホールド回路７とする）と、階調データを階調電圧信号に変換するｎ個のＤＡＣ回路８－１～８－ｎ（以下、総称する場合は、ＤＡＣ回路８とする）と、ＤＡＣ回路８からの階調電圧信号に対するバッファ回路の役割を有するｎ個のオペアンプ１－１～１－ｎ（以下、総称する場合は、オペアンプ１とする）と、ｎ個の判定回路３－１～３－ｎ（以下、総称する場合は、判定回路３とする）と、ｎ個の判定フラグ４－１～４－ｎ（以下、総称する場合は、判定フラグ４とする）と、ｎ個のプルアップ・プルダウン回路５－１～５－ｎ（以下、総称する場合は、プルアップ・プルダウン回路５とする）を備えている。 FIG. 7 is an explanatory diagram showing the configuration of the integrated circuit 10 (drive circuit). As shown in the figure, the integrated circuit 10 includes n liquid crystal driving signal output terminals OUT1 to OUTn (hereinafter referred to as output terminals OUT1 to OUTn) via a data bus from a grayscale data input terminal (not shown). N sampling circuits 6-1 to 6-n (hereinafter collectively referred to as sampling circuit 6), and n hold circuits 7-1 to 7-n (hereinafter collectively referred to as a hold circuit 7) and n DAC circuits 8-1 to 8-n (hereinafter collectively referred to as “hold circuit 7”) that convert gradation data into gradation voltage signals. DAC circuit 8), n operational amplifiers 1-1 to 1-n (hereinafter collectively referred to as operational amplifier 1) having a role of a buffer circuit for the gradation voltage signal from the DAC circuit 8, n judgment circuits 3-1 3-n (hereinafter collectively referred to as determination circuit 3), n determination flags 4-1 to 4-n (hereinafter collectively referred to as determination flag 4), n number of determination flags Pull-up / pull-down circuits 5-1 to 5-n (hereinafter collectively referred to as pull-up / pull-down circuits 5) are provided.
　さらに、同図に示すように、集積回路１０は、ｔｅｓｔ信号によってＯＮ，ＯＦＦが切り替わる複数のスイッチ２ａと、ｔｅｓｔＢ信号によってＯＮ，ＯＦＦが切り替わる複数のスイッチ２ｂと、判定フラグ４からの出力信号である、Ｆｌａｇ１～ＦｌａｇｎによってＯＮ，ＯＦＦが切り替わる複数のスイッチ２ｃ（接続切替手段）および２ｄ（接続切替手段）と、を備えている。なお、スイッチ２ａ、２ｂ、２ｄは、「Ｈ」の信号を入力した場合にＯＮとなり、「Ｌ」の信号を入力した場合にＯＦＦとなる。一方、スイッチ２ｃは、「Ｈ」の信号を入力した場合にＯＦＦとなり、「Ｈ」の信号を入力した場合にＯＮとなる。 Further, as shown in the figure, the integrated circuit 10 includes a plurality of switches 2 a that are turned on and off by a test signal, a plurality of switches 2 b that are turned on and off by a test B signal, and an output signal from the determination flag 4. There are provided a plurality of switches 2c (connection switching means) and 2d (connection switching means) that are switched ON / OFF by Flag1 to Flagn. The switches 2a, 2b, and 2d are turned on when an “H” signal is input, and are turned off when an “L” signal is input. On the other hand, the switch 2c is turned off when an “H” signal is inputted, and is turned on when an “H” signal is inputted.
　また、集積回路１０は、予備のサンプリング回路２６と、予備のホールド回路２７と、予備のＤＡＣ回路２８（予備出力回路）と、予備のオペアンプ２１を、各１回路づつ備えている。 Further, the integrated circuit 10 includes a spare sampling circuit 26, a spare hold circuit 27, a spare DAC circuit 28 (spare output circuit), and a spare operational amplifier 21, one for each circuit.
　なお、図７において、サンプリング回路６、ホールド回路７、およびＤＡＣ回路８が、図２に示した出力回路ブロック３０に相当し、サンプリング回路２６、ホールド回路２７、およびＤＡＣ回路２８が、図２に示した予備回路ブロック４０に相当し、オペアンプ１、判定回路３、および判定フラグ４が、図２に示した比較判定回路５０に相当し、出力端子ＯＵＴ１～ＯＵＴｎに接続するスイッチ２ｄおよびスイッチ２ｃが、図２に示した切替回路６０に相当し、サンプリング回路６に接続するスイッチ２ｄが、図２に示した切替回路６１に相当する。なお、図７に示す集積回路１０は、出力端子ＯＵＴ１～ＯＵＴｎを介して、図２に示す表示パネル８０と接続しており、図７においては、表示パネル８０の図示を省略している。 In FIG. 7, the sampling circuit 6, the hold circuit 7, and the DAC circuit 8 correspond to the output circuit block 30 shown in FIG. 2, and the sampling circuit 26, the hold circuit 27, and the DAC circuit 28 are shown in FIG. The operational amplifier 1, the determination circuit 3, and the determination flag 4 correspond to the preliminary circuit block 40 shown, the comparison determination circuit 50 shown in FIG. 2, and the switches 2d and 2c connected to the output terminals OUT1 to OUTn. 2 corresponds to the switching circuit 60 shown in FIG. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in FIG. Note that the integrated circuit 10 shown in FIG. 7 is connected to the display panel 80 shown in FIG. 2 via output terminals OUT1 to OUTn, and the display panel 80 is not shown in FIG.
　（集積回路１０の通常動作）
　次に、集積回路１０における、表示パネル８０（図２を参照）に階調電圧を出力する、通常の動作を、図７を参照して以下に説明する。 (Normal operation of integrated circuit 10)
Next, a normal operation in the integrated circuit 10 that outputs a grayscale voltage to the display panel 80 (see FIG. 2) will be described below with reference to FIG.
　まず、通常動作の場合は、ｔｅｓｔ信号は「Ｌ」であり、ｔｅｓｔＢ信号は「Ｈ」となる。ｔｅｓｔ信号が「Ｌ」のときスイッチ２ａはＯＦＦとなり、スイッチ２ｂはＯＮとなる。これにより、図示しないポインター用シフトレジスタからの信号である、ＳＴＲ１～ＳＴＲｎ信号（以下、総称する場合は、ＳＴＲ信号とする）を、対応する各サンプリング回路６が入力する。サンプリング回路６は、入力したＳＴＲ信号に基づき、階調データ入力端子より、データバスを介して自身に対応する階調データを取得する。ホールド回路７は、サンプリング回路６が取得した階調データを、データＬＯＡＤ信号に基づき、サンプリング回路６より入力する。次に、ＤＡＣ回路８（出力回路）は、ホールド回路７より階調データを入力する。ＤＡＣ回路８は、入力した階調データを階調電圧信号に変換し、オペアンプ１（比較手段）の正極性入力端子に出力する。ここでオペアンプ１の出力は、スイッチ２ｂがＯＮしているため、自身の負極性入力端子への負帰還となる。これにより、オペアンプ１は、ボルテージフォロワとして動作する。よって、オペアンプ１は、ＤＡＣ回路８からの階調電圧に対して、バッファ回路の役割を有することになり、自身の正極性入力端子に入力した階調電圧信号を、対応する出力端子ＯＵＴ１～ＯＵＴｎに出力する。なお、ここでは、スイッチ２ｃがＯＮ、スイッチ２ｄがＯＦＦとなっているものとする。スイッチ２ｃおよび２ｄの動作については、後述とする。上述した、出力端子ごとに直列に接続された、サンプリング回路６と、ホールド回路７と、ＤＡＣ回路８と、オペアンプ１とを含むブロックを、出力回路ブロックとすると、この出力回路ブロックは、階調データ入力端子より入力した階調データを、表示パネル８０を駆動するための階調電圧に変換し、変換した階調電圧を出力端子を介して表示パネル８０に出力することを目的としている。 First, in the case of normal operation, the test signal is “L” and the test B signal is “H”. When the test signal is “L”, the switch 2a is turned off and the switch 2b is turned on. As a result, the corresponding sampling circuits 6 input STR1 to STRn signals (hereinafter collectively referred to as STR signals), which are signals from a pointer shift register (not shown). Based on the input STR signal, the sampling circuit 6 acquires gradation data corresponding to itself from the gradation data input terminal via the data bus. The hold circuit 7 inputs the gradation data acquired by the sampling circuit 6 from the sampling circuit 6 based on the data LOAD signal. Next, the DAC circuit 8 (output circuit) inputs gradation data from the hold circuit 7. The DAC circuit 8 converts the input gradation data into a gradation voltage signal, and outputs the gradation voltage signal to the positive input terminal of the operational amplifier 1 (comparing means). Here, the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON. As a result, the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 serves as a buffer circuit for the grayscale voltage from the DAC circuit 8, and the grayscale voltage signal input to its positive input terminal is used as the corresponding output terminals OUT1 to OUTn. Output to. Here, it is assumed that the switch 2c is ON and the switch 2d is OFF. The operation of the switches 2c and 2d will be described later. Assuming that the block including the sampling circuit 6, the hold circuit 7, the DAC circuit 8, and the operational amplifier 1 connected in series for each output terminal is an output circuit block, the output circuit block has gradation An object of the present invention is to convert gradation data input from a data input terminal into a gradation voltage for driving the display panel 80, and to output the converted gradation voltage to the display panel 80 via an output terminal.
　（動作確認テストへの切り替え）
　次に、ＤＡＣ回路８の動作確認を行う動作確認テストへの切り替えは、ｔｅｓｔ信号を「Ｈ」とし、ｔｅｓｔＢ信号を「Ｌ」とする。まず、スイッチ２ａがＯＮとなることにより、予備のサンプリング回路２６には、動作確認テスト用のＳＴＲ信号である、ＴＳＴＲ１信号が入力され、サンプリング回路６には、動作確認テスト用のＳＴＲ信号である、ＴＳＴＲ２信号が入力される。さらに、オペアンプ１の負極性入力端子には、予備のＤＡＣ回路２８からの階調電圧が入力される。また、スイッチ２ｂがＯＦＦになったことにより、オペアンプ１の出力は、自身の負極性入力端子への負帰還が遮断される。その結果、オペアンプ１は、自身の正極性入力端子に直列に接続されたＤＡＣ回路８からの出力電圧と、予備のＤＡＣ回路２８からの出力電圧とを比較するコンパレータとなる。 (Switch to operation check test)
Next, switching to the operation check test for checking the operation of the DAC circuit 8 sets the test signal to “H” and the test B signal to “L”. First, when the switch 2a is turned ON, the spare sampling circuit 26 receives the TSTR1 signal, which is an STR signal for an operation check test, and the sampling circuit 6 receives an STR signal for an operation check test. , TSTR2 signal is input. Further, the gradation voltage from the spare DAC circuit 28 is input to the negative input terminal of the operational amplifier 1. Further, since the switch 2b is turned off, the negative feedback to the negative input terminal of the output of the operational amplifier 1 is cut off. As a result, the operational amplifier 1 becomes a comparator that compares the output voltage from the DAC circuit 8 connected in series with its positive input terminal with the output voltage from the spare DAC circuit 28.
　なお、ｔｅｓｔ信号およびｔｅｓｔＢ信号は、動作確認テストの切り替え、および動作確認テストの動作をコントロールする、制御回路（図示しない）より出力される。また、この制御回路（制御手段）は、動作確認テストにおける、データバスを介して入力される階調データ、および、データＬＯＡＤ信号を制御する回路でもある。さらに、この制御回路は、通常動作中の階調データ、データＬＯＡＤ信号、シフトクロック用入力信号を制御する制御回路と同一であってもよいし、異なる制御回路であってもよい。 Note that the test signal and the test B signal are output from a control circuit (not shown) that controls switching of the operation check test and operation of the operation check test. The control circuit (control means) is also a circuit for controlling gradation data and a data LOAD signal input via the data bus in the operation check test. Further, the control circuit may be the same as or different from the control circuit that controls the gradation data, the data LOAD signal, and the shift clock input signal during normal operation.
　（実施形態１の動作確認テスト１）
　次に、動作確認テストの１つ目の手順を、図８を参照して以下に説明する。図８は、第１の実施形態に係る、動作確認テストの１つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 1 of Embodiment 1)
Next, the first procedure of the operation check test will be described below with reference to FIG. FIG. 8 is a flowchart showing a first procedure of the operation check test according to the first embodiment.
　同図に示すステップＳ２１（以下、Ｓ２１と略称する）において、ｔｅｓｔ信号を「Ｈ」とし、ｔｅｓｔＢ信号を「Ｌ」とする。すでに上述したように、Ｓ２１により、オペアンプ１はコンパレータの役割を有することとなる。 In step S21 (hereinafter abbreviated as S21) shown in the figure, the test signal is set to “H” and the test B signal is set to “L”. As already described above, the operational amplifier 1 serves as a comparator by S21.
　次に、Ｓ２２において、図示しない制御回路が備えるカウンタｍを０に初期化する。さらに、制御回路は、カウンタｍの値に対応する階調ｍの階調データを、ここでは、階調０の階調データを、ＴＳＴＲ１信号をアクティブにし、データバスを介して予備のサンプリング回路２６に格納する。さらに、制御回路は、カウンタｍの値に１を加算した、階調ｍ＋１の階調データを、ここでは、階調１の階調データを、ＴＳＴＲ２信号をアクティブにし、データバスを介して、サンプリング回路６に格納する。次に、予備のホールド回路２７は、データＬＯＡＤ信号に基づいて、サンプリング回路２６より、階調０の階調データを取得する。さらに、ＤＡＣ回路２８は、ホールド回路２７より階調データを入力し、階調０の階調電圧を、オペアンプ１の負極性入力端子に出力する（Ｓ２３）。一方、ホールド回路７は、データＬＯＡＤ信号に基づいて、サンプリング回路６より、階調１の階調データを取得する。さらに、ＤＡＣ回路８は、ホールド回路７より階調データを入力する。各ＤＡＣ回路８は、自身に直列に接続された、各オペアンプ１の正極性入力端子に、階調１の階調電圧を出力する（Ｓ２３）。なお、本発明の集積回路１０は、ｎ階調の階調電圧を出力するものであり、階調０の階調電圧が一番低い電圧値であり、階調ｎの階調電圧が一番高い電圧値であるものとする。 Next, in S22, a counter m provided in a control circuit (not shown) is initialized to zero. Further, the control circuit activates the gradation data corresponding to the value of the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR1 signal, and the spare sampling circuit 26 via the data bus. To store. Further, the control circuit samples the gradation data of gradation m + 1 obtained by adding 1 to the value of the counter m, the gradation data of gradation 1 here, the TSTR2 signal active, and the data via the data bus. Store in circuit 6. Next, the spare hold circuit 27 acquires gradation data of gradation 0 from the sampling circuit 26 based on the data LOAD signal. Further, the DAC circuit 28 receives the gradation data from the hold circuit 27 and outputs a gradation voltage of gradation 0 to the negative input terminal of the operational amplifier 1 (S23). On the other hand, the hold circuit 7 acquires gradation data of gradation 1 from the sampling circuit 6 based on the data LOAD signal. Further, the DAC circuit 8 inputs gradation data from the hold circuit 7. Each DAC circuit 8 outputs a gradation voltage of gradation 1 to the positive input terminal of each operational amplifier 1 connected in series with itself (S23). Note that the integrated circuit 10 of the present invention outputs an n gradation voltage, the gradation voltage of gradation 0 is the lowest voltage value, and the gradation voltage of gradation n is the lowest. It is assumed that the voltage value is high.
　次に、オペアンプ１は、正極性入力端子に入力したＤＡＣ回路８からの階調電圧と、負極性入力端子に入力したＤＡＣ回路２８からの階調電圧とを比較する（Ｓ２４）。具体的には、オペアンプ１は、自身の正極性入力端子に階調１の階調電圧を入力し、自身の負極性入力端子に階調０の階調電圧を入力する。ここで、ＤＡＣ回路８が正常であれば、階調１の階調電圧が階調０の階調電圧よりも高いため、オペアンプ１は、「Ｈ」レベルの信号を出力する。ここで、オペアンプの出力が「Ｌ」レベルの信号であった場合、ＤＡＣ回路８は不良であることになる。 Next, the operational amplifier 1 compares the gradation voltage from the DAC circuit 8 input to the positive input terminal and the gradation voltage from the DAC circuit 28 input to the negative input terminal (S24). Specifically, the operational amplifier 1 inputs a gradation voltage of gradation 1 to its own positive input terminal, and inputs a gradation voltage of gradation 0 to its own negative input terminal. If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs an “H” level signal. Here, if the output of the operational amplifier is an “L” level signal, the DAC circuit 8 is defective.
　次に、判定回路３（判定手段）は、オペアンプ１からの出力信号を入力し、入力した信号のレベルと、自身が記憶する期待値とを比較する。なお、判定回路３が記憶する期待値は、制御回路より与えられたものである。この動作確認テスト１においては、判定回路３は期待値を「Ｈ」レベルとして記憶している。 Next, the determination circuit 3 (determination means) receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. Note that the expected value stored by the determination circuit 3 is given by the control circuit. In this operation check test 1, the determination circuit 3 stores the expected value as the “H” level.
　ここで、判定回路３は、オペアンプ１より入力した信号が、自身が記憶する期待値と同じ、「Ｈ」レベルであれば、ＤＡＣ回路８が正常であると判定する。一方、判定回路３は、オペアンプ１より入力した信号が「Ｌ」レベルであれば、ＤＡＣ回路８が不良であると判定し、判定フラグ４に「Ｈ」フラグを出力する。判定フラグ４は、判定回路３より「Ｈ」フラグを入力した場合、入力した「Ｈ」フラグを自身の内部メモリに記憶する。（Ｓ２５）
　なお、判定回路３は、オペアンプ１からの出力信号を入力し、入力した信号が「Ｈ」レベルであれば、判定フラグ４に「Ｌ」フラグを出力し、入力した信号が「Ｌ」レベルであれば、判定フラグ４に「Ｈ」フラグを出力する構成としてもよい。この場合、判定フラグ４は、判定回路３より一度でも「Ｈ」フラグを入力した場合、その後、判定回路３より「Ｌ」フラグを入力しても、判定フラグ４は「Ｈ」フラグを保持しつづける。 Here, the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is at the “H” level, which is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “L” level, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory. (S25)
The determination circuit 3 receives the output signal from the operational amplifier 1 and outputs an “L” flag to the determination flag 4 if the input signal is “H” level, and the input signal is “L” level. If there is, the configuration may be such that the “H” flag is output to the determination flag 4. In this case, when the “H” flag is input from the determination circuit 3 even once, the determination flag 4 holds the “H” flag even if the “L” flag is input from the determination circuit 3 thereafter. Continue.
　また、不良であると判断され、判定フラグ４が「Ｈ」になった場合以後の判定動作を行わない構成にしても良い。 Further, when it is determined that it is defective and the determination flag 4 becomes “H”, the subsequent determination operation may not be performed.
　次に、カウンタｍの値が、ｎ－１であるかを判定する（Ｓ２６）。カウンタｍの値がｎ－１以下の場合は、カウンタｍの値を１つ増やし、Ｓ２３～Ｓ２５のステップを、ｍの値がｎ－１となるまで、繰り返し行う。なお、このｎとは、集積回路１０が出力できる階調数である。 Next, it is determined whether the value of the counter m is n−1 (S26). When the value of the counter m is n−1 or less, the value of the counter m is incremented by 1, and the steps from S23 to S25 are repeated until the value of m becomes n−1. Note that n is the number of gradations that the integrated circuit 10 can output.
　（実施形態１の動作確認テスト２）
　次に、動作確認テストの２つ目の手順を、図９を参照して以下に説明する。図９は、第１の実施形態に係る、動作確認テストの２つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 2 of Embodiment 1)
Next, the second procedure of the operation check test will be described below with reference to FIG. FIG. 9 is a flowchart showing a second procedure of the operation check test according to the first embodiment.
　まず、動作確認テスト１においては、常にオペアンプ１の正極性入力端子に入力される階調電圧が、負極性入力端子に入力される階調電圧より高いため、ＤＡＣ回路２８に、低い電圧しか出力しないような不具合がある場合や、ＤＡＣ回路８に高い電圧しか出力しないような不具合がある場合には、判定回路３は、正常を示す「Ｌ」フラグを出力してしまう。 First, in the operation check test 1, since the grayscale voltage input to the positive input terminal of the operational amplifier 1 is always higher than the grayscale voltage input to the negative input terminal, only a low voltage is output to the DAC circuit 28. If there is a malfunction that does not occur, or if there is a malfunction such that only a high voltage is output to the DAC circuit 8, the determination circuit 3 outputs an “L” flag indicating normality.
　したがって、動作確認テスト２においては、オペアンプ１の正極性入力端子に、負極性入力端子より低い階調電圧を入力して動作確認を行う。 Therefore, in the operation check test 2, the operation check is performed by inputting a gradation voltage lower than that of the negative input terminal to the positive input terminal of the operational amplifier 1.
　まず、動作確認テスト１が終了した後、カウンタｍの値を０に初期化する（Ｓ３１）。次に、制御回路は、カウンタｍの値に１を加算した、階調ｍ＋１の階調データを、ここでは、階調１の階調データを、ＴＳＴＲ１信号をアクティブにし、データバスを介して予備のサンプリング回路２６に格納する。次に、制御回路は、カウンタｍに対応する、階調ｍの階調データを、ここでは、階調０の階調データを、ＴＳＴＲ２信号をアクティブにし、データバスを介して、サンプリング回路６に格納する。 First, after the operation check test 1 is completed, the value of the counter m is initialized to 0 (S31). Next, the control circuit activates the TSTR1 signal for the gradation data of gradation m + 1, in this case, the gradation data of gradation m + 1 by adding 1 to the value of the counter m, and reserves the data via the data bus. Is stored in the sampling circuit 26. Next, the control circuit activates the gradation data corresponding to the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR2 signal to the sampling circuit 6 via the data bus. Store.
　ここで、動作確認テスト１のＳ２３と同様に、ＤＡＣ回路２８は、サンプリング回路２６が格納した階調データを、ホールド回路２７を介して入力する。さらに、ＤＡＣ回路２８は、入力した階調データに対応する、階調ｍ＋１の階調電圧を、ここでは、階調１の階調電圧を、オペアンプ１の負極性入力端子に出力する。一方、ＤＡＣ回路８は、サンプリング回路６が格納した階調データを、ホールド回路７を介して入力する。さらに、各ＤＡＣ回路８は、入力した階調データに対応する、階調ｍの階調電圧を、ここでは、階調０の階調電圧を、自身に直列に接続された、各オペアンプ１の正極性入力端子に出力する（Ｓ３２）。 Here, as in S23 of the operation check test 1, the DAC circuit 28 inputs the gradation data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 outputs the gradation voltage of gradation m + 1 corresponding to the inputted gradation data, here, the gradation voltage of gradation 1 to the negative input terminal of the operational amplifier 1. On the other hand, the DAC circuit 8 inputs the gradation data stored by the sampling circuit 6 via the hold circuit 7. Further, each DAC circuit 8 has a gradation voltage of gradation m corresponding to the inputted gradation data, here a gradation voltage of gradation 0, of each operational amplifier 1 connected in series to itself. Output to the positive input terminal (S32).
　次に、オペアンプ１は、正極性入力端子に入力したＤＡＣ回路８からの階調０の階調電圧と、負極性入力端子に入力したＤＡＣ回路２８からの階調１の階調電圧とを比較する（Ｓ３３）。ここで、ＤＡＣ回路８が正常であれば、階調１の階調電圧が階調０の階調電圧よりも高いため、オペアンプ１は、「Ｌ」フラグの信号を出力する。ここで、オペアンプの出力が「Ｈ」レベルの信号であった場合、ＤＡＣ回路８は不良であることになる。 Next, the operational amplifier 1 compares the gradation voltage of gradation 0 from the DAC circuit 8 input to the positive input terminal with the gradation voltage of gradation 1 from the DAC circuit 28 input to the negative input terminal. (S33). If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs a signal of the “L” flag. Here, if the output of the operational amplifier is an “H” level signal, the DAC circuit 8 is defective.
　次に、判定回路３は、オペアンプ１からの出力信号を入力し、入力した信号のレベルと、自身が記憶する期待値とを比較する。この動作確認テスト１においては、判定回路３は期待値を「Ｌ」レベルとして記憶している。ここで、判定回路３は、オペアンプ１より入力した信号が、自身が記憶する期待値と同じ、「Ｌ」レベルであれば、ＤＡＣ回路８が正常であると判定する。一方、判定回路３は、オペアンプ１より入力した信号が「Ｈ」であれば、ＤＡＣ回路８が不良であると判定し、判定フラグ４に「Ｈ」フラグを出力する。判定フラグ４は、判定回路３より「Ｈ」フラグを入力した場合、入力した「Ｈ」フラグを自身の内部メモリに記憶する（Ｓ３４）。以上の、Ｓ３３～Ｓ３４のステップを、ｍの値がｎ－１となるまで繰り返し行う（Ｓ３５、Ｓ３６）。 Next, the determination circuit 3 receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. In this operation check test 1, the determination circuit 3 stores the expected value as the “L” level. Here, the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is the “L” level that is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “H”, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory (S34). The above steps S33 to S34 are repeated until the value of m becomes n−1 (S35, S36).
　（実施形態１の動作確認テスト３）
　次に、動作確認テストの３つ目の手順を、図１０を参照して以下に説明する。図１０は、第１の実施形態に係る、動作確認テストの３つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 3 of Embodiment 1)
Next, the third procedure of the operation check test will be described below with reference to FIG. FIG. 10 is a flowchart showing a third procedure of the operation check test according to the first embodiment.
　ＤＡＣ回路８において、出力がオープンとなる不具合がある場合、実行済の確認テストによる、オペアンプ１に入力された階調電圧を、オペアンプ１が保持し続け、動作確認テスト１および２において、不具合を検出できない場合がある。ここで、動作確認テスト３においては、オペアンプ１の正極性入力端子にプルダウン回路を接続する。これにより、ＤＡＣ回路８の出力がオープンとなる場合、オペアンプ１の正極性入力端子に、低い電圧を入力することになる。結果、ＤＡＣ回路８の出力がオープンとなる場合、言い換えれば、ＤＡＣ回路８より出力がない場合において、実行済の確認テストによる、オペアンプ１の入力された階調電圧を、オペアンプ１が保持し続けることを防ぐことができる。 In the DAC circuit 8, when there is a problem that the output is open, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 by the executed confirmation test, and the malfunction is confirmed in the operation confirmation tests 1 and 2. It may not be detected. Here, in the operation check test 3, a pull-down circuit is connected to the positive input terminal of the operational amplifier 1. As a result, when the output of the DAC circuit 8 is open, a low voltage is input to the positive input terminal of the operational amplifier 1. As a result, when the output of the DAC circuit 8 is open, in other words, when there is no output from the DAC circuit 8, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 according to the executed confirmation test. Can be prevented.
　動作確認テスト３の具体的な手順は、図１０に示すように、まず、カウンタｍを０に初期化する（Ｓ４１）。次に、プルアップ・プルダウン回路５は、オペアンプ１の正極性入力端子をプルダウンする（Ｓ４２）。ここからのＳ４３～Ｓ４７のステップは、既に上述した動作確認テスト１の、Ｓ２３～Ｓ２７のステップと同様であるため、ここではその説明を省略する。 The specific procedure of the operation check test 3 is as follows. First, the counter m is initialized to 0 (S41). Next, the pull-up / pull-down circuit 5 pulls down the positive input terminal of the operational amplifier 1 (S42). Steps S43 to S47 from here are the same as the steps S23 to S27 of the operation check test 1 already described above, and the description thereof is omitted here.
　以上のように、オペアンプ１の正極性入力端子をプルダウンし、動作確認テスト１の手順を行うことにより、ＤＡＣ回路８の出力がオープンとなった場合、オペアンプ１は、「Ｌ」レベルの信号を出力することになる。結果、判定回路３は、入力した「Ｌ」レベルの信号より、ＤＡＣ回路８に不具合があると判定し、判定フラグ４が「Ｈ」フラグを記憶することになる。 As described above, when the output of the DAC circuit 8 is opened by pulling down the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 1, the operational amplifier 1 outputs the “L” level signal. Will be output. As a result, the determination circuit 3 determines from the inputted “L” level signal that the DAC circuit 8 is defective, and the determination flag 4 stores the “H” flag.
　（実施形態１の動作確認テスト４）
　次に、動作確認テストの４つ目の手順を、図１１を参照して以下に説明する。図１１は、第１の実施形態に係る、動作確認テストの４つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 4 of Embodiment 1)
Next, a fourth procedure of the operation check test will be described below with reference to FIG. FIG. 11 is a flowchart showing a fourth procedure of the operation check test according to the first embodiment.
　ここで、動作確認テスト４は、動作確認テスト３と同様に、ＤＡＣ回路８の出力がオープンとなる不具合に対応するためのものである。同図に示すように、まず、カウンタｍを０に初期化する（Ｓ５１）。次に、プルアップ・プルダウン回路５は、オペアンプ１の正極性入力端子をプルアップする（Ｓ５２）。ここからのＳ５３～Ｓ５７のステップは、既に上述した動作確認テスト２の、Ｓ３２～Ｓ３６のステップと同様であるため、ここではその説明を省略する。 Here, like the operation check test 3, the operation check test 4 is for dealing with a problem that the output of the DAC circuit 8 is open. As shown in the figure, first, the counter m is initialized to 0 (S51). Next, the pull-up / pull-down circuit 5 pulls up the positive input terminal of the operational amplifier 1 (S52). The subsequent steps S53 to S57 are the same as the steps S32 to S36 of the operation check test 2 already described above, and therefore the description thereof is omitted here.
　以上のように、オペアンプ１の正極性入力端子をプルアップし、動作確認テスト２の手順を行うことにより、ＤＡＣ回路８の出力がオープンとなった場合、オペアンプ１は、「Ｈ」レベルの信号を出力することになる。結果、判定回路３は、入力した「Ｈ」レベルの信号より、ＤＡＣ回路８に不具合があると判定し、判定フラグ４が「Ｈ」を記憶することになる。 As described above, when the output of the DAC circuit 8 is opened by pulling up the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 2, the operational amplifier 1 outputs the “H” level signal. Will be output. As a result, the determination circuit 3 determines that the DAC circuit 8 has a problem from the input “H” level signal, and the determination flag 4 stores “H”.
　（実施形態１の動作確認テスト５）
　次に、動作確認テストの５つ目の手順を、図１２を参照して以下に説明する。図１２は、第１の実施形態に係る、動作確認テストの５つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 5 of Embodiment 1)
Next, a fifth procedure of the operation check test will be described below with reference to FIG. FIG. 12 is a flowchart showing the fifth procedure of the operation check test according to the first embodiment.
　ＤＡＣ回路８においては、自身における隣接する２つ階調がショートするという不具合が発生する場合がある。このように、隣接する２つ階調がショートした場合、ＤＡＣ回路８は、ショートした２つの階調の中間電圧を出力することになる。この不具合の場合、ＤＡＣ回路８が出力する階調電圧は、正常な場合と比べて、１階調以上の電圧のずれとならない。したがって、動作確認テスト１～４において、この不具合を検出することはできない。ここで、動作確認テスト５においては、このようなＤＡＣ回路８における、隣接する２つの階調がショートした不具合を検出することが目的である。 In the DAC circuit 8, there may be a problem that two adjacent gradations in itself are short-circuited. As described above, when two adjacent gradations are short-circuited, the DAC circuit 8 outputs an intermediate voltage between the two short-circuited gradations. In the case of this defect, the gradation voltage output from the DAC circuit 8 does not cause a voltage shift of one gradation or more compared to a normal case. Therefore, this malfunction cannot be detected in the operation confirmation tests 1 to 4. Here, the purpose of the operation check test 5 is to detect a problem in which the two adjacent gradations in the DAC circuit 8 are short-circuited.
　同図に示すように、まず、カウンタｍを０に初期化する（Ｓ６１）。次に、ＴＳＴＲ１およびＴＳＴＲ２をアクティブにし、さらに、データバスを介して、階調ｍの階調データを、ここでは、階調０の階調データを、サンプリング回路２６およびサンプリング回路６が入力する。次に、ＤＡＣ回路２８および８は、ホールド回路２７および７を介して、サンプリング回路２６および６より、階調０の階調データを取得する。さらにＤＡＣ回路２８および８は、オペアンプ１の正極性入力端子および負極性入力端子に、階調０の階調電圧を出力する（Ｓ６２）。 As shown in the figure, first, the counter m is initialized to 0 (S61). Next, TSTR1 and TSTR2 are activated, and further, gradation data of gradation m and here gradation data of gradation 0 are input to sampling circuit 26 and sampling circuit 6 via a data bus. Next, the DAC circuits 28 and 8 acquire gradation data of gradation 0 from the sampling circuits 26 and 6 via the hold circuits 27 and 7. Further, the DAC circuits 28 and 8 output a gradation voltage of gradation 0 to the positive input terminal and the negative input terminal of the operational amplifier 1 (S62).
　次に、図示しないスイッチにより、オペアンプ１の正極性入力端子と、負極性入力端子とをショートする。なお、動作確認テスト１および２において、ＤＡＣ回路８に不具合がないと判定されている場合は、正極性入力端子と負極性入力端子に入力される階調電圧の差は、１階調以上の電圧差にならない。したがって、正極性入力端子と負極性入力端子とをショートすることによって、大きな電流が流れるという問題はない。 Next, the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited by a switch (not shown). If it is determined in the operation check tests 1 and 2 that the DAC circuit 8 is not defective, the difference between the gradation voltages input to the positive input terminal and the negative input terminal is equal to or greater than one gradation. There is no voltage difference. Therefore, there is no problem that a large current flows by short-circuiting the positive input terminal and the negative input terminal.
　ここで、オペアンプ１の正極性入力端子と負極性入力端子とをショートしたことにより、オペアンプ１の２つの入力端子は、同じ階調電圧を入力することになる。ここで、本来オペアンプ１は、入出力のオフセット電圧を有しているため、自身の２つの入力端子に同じ階調電圧を入力したとしても、オペアンプ１の出力は、「Ｈ」または「Ｌ」のどちらかを出力することになる。この、オペアンプ１の正極性入力端子と負極性入力端子とをショートした場合の、オペアンプ１の出力のレベルを、判定回路３は、期待値として記憶する（Ｓ６３）。 Here, since the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited, the two input terminals of the operational amplifier 1 input the same gradation voltage. Here, since the operational amplifier 1 originally has an input / output offset voltage, the output of the operational amplifier 1 is “H” or “L” even if the same gradation voltage is input to its two input terminals. Either of these will be output. The determination circuit 3 stores the output level of the operational amplifier 1 when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S63).
　次に、図示しないスイッチをＯＦＦにして、オペアンプ１の正極性入力端子と負極性入力端子とのショートを解除する。このとき、オペアンプ１の正極性入力端子には、ＤＡＣ回路８からの階調０の階調電圧が入力され、負極性入力端子には、ＤＡＣ回路２８からの階調０の階調電圧が入力される。ここで、ＤＡＣ回路２８および８に不具合がなければ、オペアンプ１の出力は、判定回路３に記憶した期待値と同じ出力となる。したがって、判定回路３は、オペアンプ１からの出力と、自身が記憶する期待値とを比較する（Ｓ６４）。判定回路３は、オペアンプ１からの出力値が、期待値と異なる値であれば、判定フラグ４に「Ｈ」フラグを出力する（Ｓ６５）。 Next, the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1. At this time, the gradation voltage of gradation 0 from the DAC circuit 8 is input to the positive input terminal of the operational amplifier 1, and the gradation voltage of gradation 0 from the DAC circuit 28 is input to the negative input terminal. Is done. Here, if the DAC circuits 28 and 8 are not defective, the output of the operational amplifier 1 is the same as the expected value stored in the determination circuit 3. Therefore, the determination circuit 3 compares the output from the operational amplifier 1 with the expected value stored by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs the “H” flag to the determination flag 4 (S65).
　次に、図示しないスイッチによって、オペアンプ１の正極性入力端子にＤＡＣ回路２８からの階調電圧を入力し、負極性入力端子にＤＡＣ回路８からの階調電圧を入力するように、オペアンプ１の入力を切り替える（Ｓ６６）。ここで、Ｓ６４と同様の処理を行う（Ｓ６７）。Ｓ６７において、判定回路３が、オペアンプ１からの出力と、自身が記憶する期待値とが異なれば、判定フラグ４に「Ｈ」フラグを出力する（Ｓ６８）。このように、正極性入力端子と負極性入力端子とを切り替えることにより、判定回路３が記憶する期待値が「Ｈ」レベルまたは「Ｌ」レベルのどちらであっても、ＤＡＣ回路８の不具合を検出可能となる。 Next, the gradation voltage from the DAC circuit 28 is input to the positive input terminal of the operational amplifier 1 and the gradation voltage from the DAC circuit 8 is input to the negative input terminal by a switch (not shown). The input is switched (S66). Here, the same processing as S64 is performed (S67). In S67, if the output from the operational amplifier 1 is different from the expected value stored in the determination circuit 3, the determination circuit 3 outputs an “H” flag to the determination flag 4 (S68). In this way, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the expected value stored in the determination circuit 3 is either the “H” level or the “L” level, the problem of the DAC circuit 8 is prevented. It can be detected.
　以上のＳ６２～Ｓ６８のステップを、カウンタｍの値がｎとなるまで、カウンタｍの値を１つ増加させて繰り返し行う（Ｓ６９、Ｓ７０）。 The above steps S62 to S68 are repeated by incrementing the value of the counter m until the value of the counter m reaches n (S69, S70).
　（自己修復）
　次に、判定フラグ４が「Ｈ」フラグを記憶している場合、言い換えれば、上記動作確認テスト１～５において、ＤＡＣ回路８－１～８－ｎのいずれかに不具合があると判定回路３が判定した場合の修復について、図１３を参照して以下に説明する。図１３は、不良と判定したＤＡＣ回路８と、予備のＤＡＣ回路２８とを切り替え、自己修復する手順を示すフローチャート図である。 (Self-healing)
Next, when the determination flag 4 stores the “H” flag, in other words, in the operation check tests 1 to 5, if any of the DAC circuits 8-1 to 8-n is defective, the determination circuit 3 The repair in the case where the determination is made will be described below with reference to FIG. FIG. 13 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuit 28 and performing self-repair.
　判定回路３は、ＤＡＣ回路８が不良であると判定した場合、「Ｈ」フラグを判定フラグ４に出力する。さらに、判定フラグ４は、判定回路３からの「Ｈ」フラグを入力し、自身の内部に記憶する。ここで、制御回路は、判定フラグ４が「Ｈ」を記録しているかどうかを検出する（Ｓ７１）。制御回路は、判定フラグ４が「Ｈ」を記憶していないことを検出した場合は、Ｓ７５の処理に移る。一方、制御回路は、判定フラグ４が「Ｈ」を記憶していることを検出した場合、判定フラグ４－１～４－ｎのそれぞれが記憶している「Ｈ」のフラグ数を確認する。ここで、判定フラグ４が記憶している「Ｈ」のフラグ数が複数の場合、Ｓ７３の処理にうつる。一方、判定フラグ４が記憶している「Ｈ」のフラグ数が１つの場合は、Ｓ７４の処理にうつる（Ｓ７２）。 When the determination circuit 3 determines that the DAC circuit 8 is defective, the determination circuit 3 outputs an “H” flag to the determination flag 4. Further, the determination flag 4 receives the “H” flag from the determination circuit 3 and stores it in the inside thereof. Here, the control circuit detects whether or not the determination flag 4 records “H” (S71). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S75. On the other hand, when the control circuit detects that the determination flag 4 stores “H”, the control circuit checks the number of “H” flags stored in each of the determination flags 4-1 to 4-n. Here, when the number of “H” flags stored in the determination flag 4 is plural, the process proceeds to S73. On the other hand, when the number of “H” flags stored in the determination flag 4 is one, the process proceeds to S74 (S72).
　Ｓ７４においては、「Ｈ」フラグを記憶している判定フラグ４に対応するＤＡＣ回路８を、予備のＤＡＣ回路２８に切り替える処理を行う（Ｓ７４）。まず、不良のＤＡＣ回路８と予備のＤＡＣ回路２８との切り替えの手順を説明するにあたり、ここでは、液晶駆動用信号出力端子ＯＵＴ１に対応する判定フラグ４－１が「Ｈ」フラグを記憶しているものとする。 In S74, a process of switching the DAC circuit 8 corresponding to the determination flag 4 storing the “H” flag to the spare DAC circuit 28 is performed (S74). First, in explaining the switching procedure between the defective DAC circuit 8 and the spare DAC circuit 28, here, the determination flag 4-1 corresponding to the liquid crystal driving signal output terminal OUT1 stores the “H” flag. It shall be.
　判定フラグ４－１は、スイッチ２ｃおよび２ｄに対して、「Ｈ」レベルとなるＦｌａｇ１の出力信号を出力する。Ｆｌａｇ１の出力信号によって、「Ｈ」レベルの信号を入力したスイッチ２ｃはＯＦＦとなり、スイッチ２ｄはＯＮとなる。これにより、スイッチ２ｃはオペアンプ１－１からの出力と、液晶駆動用信号出力端子ＯＵＴ１との接続を遮断することになる。一方、スイッチ２ｄは、サンプリング回路６－１に入力されるＳＴＲ１信号を、サンプリング回路２６に出力することになる。これにより、液晶駆動用信号出力端子ＯＵＴ１に対応する階調データは、サンプリング回路２６も格納することになる。さらに、スイッチ２ｄは、オペアンプ２１の出力と、液晶駆動用信号出力端子ＯＵＴ１とを接続する。このように、判定フラグ４－１からのＦｌａｇ１の出力信号によって、スイッチ２ｃおよび２ｄが切り替わることにより、不良であるＤＡＣ回路８－１を予備のＤＡＣ回路２８に切り替えることになる。 Judgment flag 4-1 outputs an output signal of Flag1 which becomes “H” level to the switches 2c and 2d. The switch 2c to which the “H” level signal is input is turned OFF and the switch 2d is turned ON by the output signal of Flag1. As a result, the switch 2c cuts off the connection between the output from the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1. On the other hand, the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit 26. As a result, the gradation data corresponding to the liquid crystal driving signal output terminal OUT1 also stores the sampling circuit 26. Furthermore, the switch 2d connects the output of the operational amplifier 21 and the liquid crystal driving signal output terminal OUT1. As described above, the switches 2c and 2d are switched by the output signal of Flag1 from the determination flag 4-1, so that the defective DAC circuit 8-1 is switched to the spare DAC circuit 28.
　次に、Ｓ７３の処理について説明する。判定フラグ４が記憶する「Ｈ」フラグの数が、複数であった場合、確率的に予備のＤＡＣ回路２８が不良であると考えられる。したがって、Ｓ７３において、制御回路は、判定フラグ４が記憶するフラグを全て「Ｌ」フラグにし、Ｓ７５の処理に移行する。次に、Ｓ７１においてＮＯと判定された場合、Ｓ７３の処理後、または、Ｓ７４の処理後、制御回路は、ｔｅｓｔ信号を「Ｌ」に、ｔｅｓｔＢ信号を「Ｈ」に切り替え、通常動作に移行する（Ｓ７５）。 Next, the process of S73 will be described. When the number of “H” flags stored in the determination flag 4 is plural, it is considered that the spare DAC circuit 28 is defective in probability. Therefore, in S73, the control circuit sets all the flags stored in the determination flag 4 to the “L” flag, and proceeds to the process of S75. Next, when it is determined NO in S71, after the process of S73 or the process of S74, the control circuit switches the test signal to “L” and the test B signal to “H”, and shifts to the normal operation. (S75).
　以上のように、動作確認テスト１～５、および、自己修復の処理を行うことにより、集積回路１０は、不良のＤＡＣ回路を予備のＤＡＣ回路２８に切り替えることができる。さらに、第１の実施形態においては、予備のＤＡＣ回路２８に対応する、予備のサンプリング回路２６およびホールド回路２７を備えている。したがって、ＤＡＣ回路８だけでなく、サンプリング回路６またはホールド回路７に不具合があった場合においても、予備のサンプリング回路２６およびホールド回路２８に切り替えることができる。 As described above, the integrated circuit 10 can switch the defective DAC circuit to the spare DAC circuit 28 by performing the operation check tests 1 to 5 and the self-repair process. Further, in the first embodiment, a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28 are provided. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
　次に、集積回路１０を搭載する表示装置の電源投入から、動作確認テストを行い、通常動作を行うまでの手順を、図１４を参照して以下に説明する。図１４は、表示装置の電源投入から、動作確認テストを行い通常動作に移行するまでの処理手順を示すフローチャート図である。 Next, the procedure from the power-on of the display device on which the integrated circuit 10 is mounted to the operation check test to the normal operation will be described with reference to FIG. FIG. 14 is a flowchart showing a processing procedure from when the display device is turned on until the operation check test is performed and the normal operation is started.
　同図に示すように、まず、表示装置に電源投入し、集積回路１０を初期化することにより、判定フラグ４は全て「Ｌ」フラグになる（Ｓ８１）。次に、制御回路は、ｔｅｓｔ信号を「Ｈ」に、ｔｅｓｔＢ信号を「Ｌ」にし、動作確認テストの状態に集積回路１０を切り替える（Ｓ８２）。次に、制御回路および集積回路１０は、上述した動作確認テストを行う（Ｓ８３）。さらに、全ての動作確認テスト１～５が終了したかどうかを、制御回路は確認し、不良となる回路は、予備の回路に切り替え、通常動作に移行する（Ｓ８４）。 As shown in the figure, first, when the display device is powered on and the integrated circuit 10 is initialized, all the determination flags 4 become “L” flags (S81). Next, the control circuit sets the test signal to “H” and the test B signal to “L”, and switches the integrated circuit 10 to the operation check test state (S82). Next, the control circuit and the integrated circuit 10 perform the above-described operation check test (S83). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed, and the defective circuit is switched to a spare circuit to shift to a normal operation (S84).
　（オペアンプ１の動作確認）
　上述した動作確認テストは、オペアンプ１に不具合がないことを前提としている。しかしながら、オペアンプ１においても不具合が発生する可能性がある。したがって、上記動作確認テストを行う前に、オペアンプ１の動作確認を行うことが、本実施形態においては好ましい。そこで、以下に、オペアンプ１の動作確認についても、図１５を参照して説明する。図１５は、オペアンプ１とオペアンプ１の動作確認のための周辺回路との構成を示す説明図である。 (Operation check of operational amplifier 1)
The operation check test described above is based on the premise that the operational amplifier 1 is not defective. However, the operational amplifier 1 may also have a problem. Therefore, in this embodiment, it is preferable to check the operation of the operational amplifier 1 before performing the operation check test. Therefore, the operation check of the operational amplifier 1 will be described below with reference to FIG. FIG. 15 is an explanatory diagram showing a configuration of the operational amplifier 1 and peripheral circuits for confirming the operation of the operational amplifier 1.
　同図に示すように、オペアンプ１の正極性入力端子には、ＤＡＣ回路８からの出力と、所定の電圧との入力を切り替えるスイッチＳ５が接続されている。さらにスイッチＳ５のＢ側（所定の電圧の入力側）には、２つの所定の電圧Ｖｒｅｆ１およびＶｒｅｆ２を切り替えるスイッチＳ３が接続されている。一方、オペアンプ１の負極性入力端子には、オペアンプ１からの負帰還を行うためのオペアンプ１の出力と、所定の電圧との入力を切り替えるスイッチＳ６が接続されている。さらに、スイッチＳ４のＢ側（所定の電圧の入力側）には、２つの所定の電圧Ｖｒｅｆ１およびＶｒｅｆ２を切り替えるスチッチＳ４が接続されている。 As shown in the figure, the positive input terminal of the operational amplifier 1 is connected to a switch S5 for switching input between an output from the DAC circuit 8 and a predetermined voltage. Further, a switch S3 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S5. On the other hand, the negative input terminal of the operational amplifier 1 is connected to a switch S6 for switching input between an output of the operational amplifier 1 for performing negative feedback from the operational amplifier 1 and a predetermined voltage. Further, a switch S4 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S4.
　次に、オペアンプ１の通常動作について説明する。オペアンプ１の通常動作時は、スイッチＳ５をＡ側（ＤＡＣ回路８の出力側）にし、スイッチＳ６をＡ側にすることにより、オペアンプ１は、ボルテージフォロワの回路として動作する。 Next, the normal operation of the operational amplifier 1 will be described. During the normal operation of the operational amplifier 1, the operational amplifier 1 operates as a voltage follower circuit by setting the switch S5 to the A side (output side of the DAC circuit 8) and the switch S6 to the A side.
　次に、オペアンプ１の動作確認動作確認を行うための手順を以下に説明する。まず、スイッチＳ１およびＳ２をＢ側に切り替える。これにより、オペアンプ１の負帰還はなくなり、オペアンプ１はコンパレータとして動作する。次に、スイッチＳ３およびＳ４をＡ側に切り替える。これにより、オペアンプ１の正極性入力端子は、Ｖｒｅｆ１を入力し、負極性入力端子は、Ｖｒｅｆ２を入力することになる。ここで、Ｖｒｅｆ１およびＶｒｅｆ２は予め生成された電圧であり、Ｖｒｅｆ１の電圧値は、Ｖｒｅｆ２の電圧値より大きい値とする。なお、Ｖｒｅｆ１とＶｒｅｆ２との電圧値の差は、オペアンプ１の入出力オフセット値よりも大きい値とする。このとき、オペアンプ１は、負極性入力端子に入力したＶｒｅｆ２より、正極性入力端子に入力したＶｒｅｆ１の電圧の方が高いため、「Ｈ」レベルの信号を出力する。このオペアンプ１からの出力を、判定回路３が検出し、自身が記憶する期待値「Ｈ」と比較する。ここで、オペアンプ１の出力が「Ｌ」レベルであった場合、判定回路３は、オペアンプ１に不具合があると判定できる。なお、判定回路３が記憶する期待値は、制御回路より与えられたものである。 Next, the procedure for confirming the operation of the operational amplifier 1 will be described below. First, the switches S1 and S2 are switched to the B side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 operates as a comparator. Next, the switches S3 and S4 are switched to the A side. Thus, Vref1 is input to the positive input terminal of the operational amplifier 1, and Vref2 is input to the negative input terminal. Here, Vref1 and Vref2 are voltages generated in advance, and the voltage value of Vref1 is larger than the voltage value of Vref2. The difference in voltage value between Vref1 and Vref2 is set to a value larger than the input / output offset value of the operational amplifier 1. At this time, the operational amplifier 1 outputs a signal of “H” level because the voltage of Vref1 input to the positive input terminal is higher than Vref2 input to the negative input terminal. The determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “H” stored by itself. Here, when the output of the operational amplifier 1 is at the “L” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the expected value stored by the determination circuit 3 is given by the control circuit.
　次に、オペアンプ１のコンパレータ動作に不具合があり、オペアンプ１は「Ｈ」レベルしか出力できない場合も考えられる。したがって、スイッチＳ３およびＳ４をＢ側に切り替え、オペアンプ１の正極性入力端子にＶｒｅｆ２を入力し、負極性入力端子にＶｒｅｆ１を入力する。このとき、オペアンプ１は、正極性入力端子に入力したＶｒｅｆ２よりも、負極性入力端子に入力したＶｒｅｆ１の電圧値の方が高いため、「Ｌ」レベルを出力する。このオペアンプ１からの出力を、判定回路３が検出し、自身が記憶する期待値「Ｌ」と比較する。ここで、オペアンプ１の出力が「Ｈ」レベルであった場合、判定回路３は、オペアンプ１に不具合があると判定できる。なお、スイッチＳ３～Ｓ６は、制御回路によって切り替えられるものとする。 Next, there is a case where there is a malfunction in the comparator operation of the operational amplifier 1 and the operational amplifier 1 can output only “H” level. Therefore, the switches S3 and S4 are switched to the B side, Vref2 is input to the positive input terminal of the operational amplifier 1, and Vref1 is input to the negative input terminal. At this time, the operational amplifier 1 outputs the “L” level because the voltage value of Vref1 input to the negative input terminal is higher than Vref2 input to the positive input terminal. The determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “L” stored by itself. Here, when the output of the operational amplifier 1 is at the “H” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the switches S3 to S6 are switched by the control circuit.
　〔実施形態２〕
　次に、本発明に係る第２の実施形態について、図１６～図２２を参照して、以下に説明する。なお、なお、実施形態２の説明に関しては、実施形態１と異なる箇所についてのみ説明し、重複する箇所についてはその説明を省略する。 [Embodiment 2]
Next, a second embodiment according to the present invention will be described below with reference to FIGS. In addition, regarding the description of the second embodiment, only portions that are different from the first embodiment will be described, and descriptions of overlapping portions will be omitted.
　まず、実施形態１と実施形態２の違いについて簡単に説明する。実施形態１は、ＤＡＣ回路８の出力と、予備のＤＡＣ回路２８の出力を、オペアンプ１において比較している。一方、実施形態２は、互いに隣接する２つのＤＡＣ回路８を一組とし、互いのＤＡＣ回路８からの出力を、オペアンプ１において比較する。 First, the difference between the first embodiment and the second embodiment will be briefly described. In the first embodiment, the operational amplifier 1 compares the output of the DAC circuit 8 with the output of the spare DAC circuit 28. On the other hand, in the second embodiment, two adjacent DAC circuits 8 are set as one set, and the outputs from the DAC circuits 8 are compared in the operational amplifier 1.
　（表示駆動用半導体集積回路２０の構成）
　図１６を参照して、本発明の表示駆動用半導体集積回路（以下、集積回路とする）２０の構成について説明する。図１６は、集積回路２０（表示装置駆動用の集積回路）の構成を示す説明図である。 (Configuration of display driving semiconductor integrated circuit 20)
With reference to FIG. 16, the structure of a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit) 20 of the present invention will be described. FIG. 16 is an explanatory diagram showing the configuration of the integrated circuit 20 (integrated circuit for driving the display device).
　オペアンプ１は、自身に直列に接続されるＤＡＣ回路８からの出力を、自身の正極性入力端子に入力する。さらに、オペアンプ１は、自身に隣り合うオペアンプに直列に接続されるＤＡＣ回路８からの出力を、自身の負極性入力端子に入力する。具値的には、同図に示すように、オペアンプ１－１は、ＤＡＣ回路８－１からの出力を、自身の正極性入力端子に入力し、ＤＡＣ回路８－２にからの出力を、スイッチ２ａを介して自身の負極性入力端子に入力する。同様に、オペアンプ１－２は、ＤＡＣ回路８－２からの出力を、自身の正極性入力端子に入力し、ＤＡＣ回路８－１からの出力を、スイッチ２ａを介して自身の負極性入力端子に入力する。また、集積回路２０は、予備のサンプリング回路２６Ａおよび２６Ｂと、予備のホールド回路２７Ａおよび２７Ｂと、予備のＤＡＣ回路２８Ａおよび２８Ｂと、オペアンプ２１Ａおよび２１Ｂと、プルアップ・プルダウン回路２５Ａおよび２５Ｂとを備えている。オペアンプ２１Ａにおいても、ＤＡＣ回路２８Ａからの出力を自身の正極性入力端子に、ＤＡＣ回路２８Ｂからの出力を、スイッチ２ａを介して自身の負極性入力端子に入力する。さらに、オペアンプ２１Ｂにおいても、ＤＡＣ回路２８Ｂからの出力を、自身の正極性入力端子に、ＤＡＣ回路２８Ａからの出力を、スイッチ２ａを介して自身の負極性入力端子に入力している。 The operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier 1 to its positive input terminal. Furthermore, the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier adjacent to the operational amplifier 1 to its negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8-1 to its positive input terminal, and outputs the output from the DAC circuit 8-2. It inputs to its own negative input terminal via the switch 2a. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8-2 to its own positive input terminal, and outputs the output from the DAC circuit 8-1 through its switch 2a to its own negative input terminal. To enter. The integrated circuit 20 also includes spare sampling circuits 26A and 26B, spare hold circuits 27A and 27B, spare DAC circuits 28A and 28B, operational amplifiers 21A and 21B, and pull-up / pull- down circuits 25A and 25B. I have. Also in the operational amplifier 21A, the output from the DAC circuit 28A is input to its own positive input terminal, and the output from the DAC circuit 28B is input to its own negative input terminal via the switch 2a. Further, in the operational amplifier 21B, the output from the DAC circuit 28B is input to its own positive input terminal, and the output from the DAC circuit 28A is input to its own negative input terminal via the switch 2a.
　（集積回路２０の通常動作）
　集積回路２０における通常動作においては、実施形態１と同様に、制御回路は、ｔｅｓｔ信号を「Ｌ」レベルに、ｔｅｓｔＢ信号を「Ｈ」レベルにする。これにより、ＤＡＣ回路８は、ホールド回路７より入力した階調データを階調電圧信号に変換し、階調電圧としてオペアンプ１の正極性入力端子に出力する。ここでオペアンプ１の出力は、スイッチ２ｂがＯＮしているため、自身の負極性入力端子への負帰還となる。これにより、オペアンプ１は、ボルテージフォロワとして動作する。よって、オペアンプ１は、ＤＡＣ回路８からの階調電圧をバッファし、対応する各出力端子ＯＵＴ１～ＯＵＴｎに出力する。 (Normal operation of integrated circuit 20)
In the normal operation in the integrated circuit 20, as in the first embodiment, the control circuit sets the test signal to the “L” level and the test B signal to the “H” level. As a result, the DAC circuit 8 converts the grayscale data input from the hold circuit 7 into a grayscale voltage signal and outputs the grayscale voltage to the positive input terminal of the operational amplifier 1. Here, the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON. As a result, the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 buffers the gradation voltage from the DAC circuit 8 and outputs it to the corresponding output terminals OUT1 to OUTn.
　（動作確認テストの切り替え）
　集積回路２０における動作確認テストへの切り替えは、制御回路がｔｅｓｔ信号を「Ｈ」レベルとし、ｔｅｓｔＢ信号を「Ｌ」レベルとする。まず、スイッチ２ａがＯＮとなることにより、サンプリング回路２６Ａおよび奇数番目のサンプリング回路６（サンプリング回路６－１，６－３，・・・，６－（ｎ－１））には、ＴＳＴＲ１信号が入力される。さらに、サンプリング回路２６Ｂおよび偶数番目のサンプリング回路６（サンプリング回路６－２，６－３，・・・，６－ｎ）には、ＴＳＴＲ２信号が入力される。さらに、スイッチ２ａがＯＮとなることにより、奇数番目のオペアンプ１の負極性入力端子には、隣り合う偶数番目のＤＡＣ回路８からの出力が入力され、偶数番目のオペアンプ１の負極性入力端子には、隣り合う奇数番目のＤＡＣ回路８からの出力が入力される。また、ｔｅｓｔＢ信号が「Ｌ」レベルとなることにより、スイッチ２ｂはＯＦＦとなる。これにより、オペアンプ１における、自身の出力の負極性入力端子への負帰還が遮断されることになる。その結果、オペアンプ１は、自身に直列に接続されたＤＡＣ回路８からの出力と、隣り合うＤＡＣ回路８からの出力とを比較するコンパレータとなる。 (Switch operation test)
In the switching to the operation check test in the integrated circuit 20, the control circuit sets the test signal to the “H” level and sets the test B signal to the “L” level. First, when the switch 2a is turned ON, the TSTR1 signal is sent to the sampling circuit 26A and the odd-numbered sampling circuits 6 (sampling circuits 6-1, 6-3,..., 6- (n−1)). Entered. Further, the TSTR2 signal is input to the sampling circuit 26B and the even-numbered sampling circuits 6 (sampling circuits 6-2, 6-3,..., 6-n). Further, when the switch 2a is turned ON, the output from the adjacent even-numbered DAC circuit 8 is input to the negative-polarity input terminal of the odd-numbered operational amplifier 1, and the negative-polarity input terminal of the even-numbered operational amplifier 1 is input. Are supplied with outputs from adjacent odd-numbered DAC circuits 8. Further, when the test B signal becomes “L” level, the switch 2b is turned OFF. As a result, negative feedback of the output of the operational amplifier 1 to the negative input terminal is cut off. As a result, the operational amplifier 1 becomes a comparator that compares the output from the DAC circuit 8 connected in series with the operational amplifier 1 with the output from the adjacent DAC circuit 8.
　（実施形態２の動作確認テスト１）
　次に、第２の実施形態に係る、動作確認テストの１つ目の手順を、図１７を参照して以下に説明する。図１７は、第２の実施形態に係る、動作確認テストの１つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 1 of Embodiment 2)
Next, the first procedure of the operation check test according to the second embodiment will be described below with reference to FIG. FIG. 17 is a flowchart showing a first procedure of the operation check test according to the second embodiment.
　まず、制御回路はｔｅｓｔ信号を「Ｈ」レベルに、ｔｅｓｔＢ信号を「Ｌ」レベルにする（Ｓ１０１）。これにより、オペアンプ１はコンパレータとして動作する（Ｓ１０２）。次に、制御回路は、奇数番目の判定回路３（判定回路３－１，３－３，・・・，３－（ｎ－１））の期待値を「Ｌ」レベルに設定する。一方、制御回路は、偶数番目の判定回路３（判定回路３－２，３－４，・・・，３－ｎ）の期待値を「Ｈ」レベルに設定する。 First, the control circuit sets the test signal to the “H” level and the test B signal to the “L” level (S101). As a result, the operational amplifier 1 operates as a comparator (S102). Next, the control circuit sets the expected value of the odd-numbered determination circuit 3 (determination circuits 3-1, 3-3,..., 3- (n−1)) to the “L” level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuit 3 (determination circuits 3-2, 3-4,..., 3-n) to the “H” level.
　次に、制御回路は、自身が備えるカウンタｍを０に初期化する（Ｓ１０３）。さらに、制御回路は、ＴＳＴＲ１をアクティブにし、サンプリング回路２６Ａおよび奇数番目のサンプリング回路６がデータバスを介して、階調ｍの階調データを入力する。また、制御回路は、ＴＳＴＲ２をアクティブにし、サンプリング回路２６Ｂおよび偶数番目のサンプリング回路６がデータバスを介して、階調ｍ＋１の階調データを入力する（Ｓ１０４）。 Next, the control circuit initializes a counter m included in the control circuit to 0 (S103). Further, the control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m through the data bus. In addition, the control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m + 1 through the data bus (S104).
　ここで、カウンタｍの値が０の場合を考えると、奇数番目のオペアンプ１は、自身の正極性入力端子に階調０の階調電圧を、自身に直列に接続される、奇数番目のＤＡＣ回路８より入力する。また、奇数番目のオペアンプ１は、自身の負極性入力端子に階調１の階調電圧を、隣り合う偶数番目のＤＡＣ回路８より入力する。ここで、オペアンプ１の２つの入力端子に接続するＤＡＣ回路８が正常であれば、奇数番目のオペアンプ１の出力は「Ｌ」になる。一方、偶数番目のオペアンプ１は、自身の正極性入力端子に階調１の階調電圧を、自身に直列に接続される、偶数番目のＤＡＣ回路８より入力する。また、偶数番目のオペアンプ１は、自身の負極性入力端子に階調０の階調電圧を、隣り合う奇数番目のＤＡＣ回路８より入力する。ここで、オペアンプ１の２つの入力端子に接続するＤＡＣ回路８が正常であれば、偶数番目のオペアンプ１の出力は「Ｈ」になる。 Here, considering the case where the value of the counter m is 0, the odd-numbered operational amplifier 1 has an odd-numbered DAC in which a gradation voltage of gradation 0 is connected in series to its positive polarity input terminal. Input from circuit 8. The odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from its adjacent even-numbered DAC circuit 8 to its negative input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 becomes “L”. On the other hand, the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself. The even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent odd-numbered DAC circuit 8 to its negative input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “H”.
　次に、判定回路３は、オペアンプ１からの出力信号のレベルが、自身が記憶する期待値に合致するかを判定する（Ｓ１０５）。ここで、オペアンプ１からの出力が、期待値と異なる場合、判定回路３は、判定フラグ４に「Ｈ」フラグを出力する（Ｓ１０６）。以上のＳ１０４～Ｓ１０６までの処理を、カウンタｍの値を１つづつ増やし、カウンタｍの値がｎ－１となるまで繰り返し行う（Ｓ１０７，Ｓ１０８）。 Next, the determination circuit 3 determines whether the level of the output signal from the operational amplifier 1 matches the expected value stored by itself (S105). Here, when the output from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs an “H” flag to the determination flag 4 (S106). The above processing from S104 to S106 is repeated until the value of the counter m is incremented by one until the value of the counter m reaches n−1 (S107, S108).
　（実施形態２の動作確認テスト２）
　次に、第２の実施形態に係る、動作確認テストの２つ目の手順を、図１８を参照して以下に説明する。図１８は、第２の実施形態に係る、動作確認テストの２つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 2 of Embodiment 2)
Next, a second procedure of the operation check test according to the second embodiment will be described below with reference to FIG. FIG. 18 is a flowchart showing a second procedure of the operation check test according to the second embodiment.
　第２の実施形態における動作確認テスト２は、第２の実施形態における動作確認テスト１における、奇数番目と偶数番目との階調の電圧関係を逆にした動作確認であり、その他は、第２の実施形態における動作確認テストと同様である。 The operation check test 2 in the second embodiment is an operation check in which the voltage relationship of the odd-numbered and even-numbered gradations is reversed in the operation check test 1 in the second embodiment. This is the same as the operation check test in the embodiment.
　まず、制御回路は、奇数番目の判定回路３の期待値を「Ｈ」に設定し、一方、偶数番目の判定回路３の期待値を「Ｌ」に設定する。さらに、制御回路は、自身が備えるカウンタｍを０に初期化する（Ｓ１１１）。 First, the control circuit sets the expected value of the odd-numbered determination circuit 3 to “H”, while setting the expected value of the even-numbered determination circuit 3 to “L”. Further, the control circuit initializes a counter m included in the control circuit to 0 (S111).
　次に、制御回路は、ＴＳＴＲ１をアクティブにし、サンプリング回路２６Ａおよび奇数番目のサンプリング回路６がデータバスを介して、階調ｍ＋１の階調データを入力する。また、制御回路は、ＴＳＴＲ２をアクティブにし、サンプリング回路２６Ｂおよび偶数番目のサンプリング回路６がデータバスを介して、階調ｍの階調データを入力する（Ｓ１１２）。 Next, the control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m + 1 via the data bus. In addition, the control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m via the data bus (S112).
　ここで、カウンタｍの値が０の場合を考えると、奇数番目のオペアンプ１は、自身の正極性入力端子に階調１の階調電圧を、自身に直列に接続される、奇数番目のＤＡＣ回路８より入力する。また、奇数番目のオペアンプ１は、自身の負極性入力端子に階調０の階調電圧を、隣り合う偶数番目のＤＡＣ回路８より入力する。ここで、オペアンプ１の２つの入力端子に接続するＤＡＣ回路８が正常であれば、奇数番目のオペアンプ１の出力は「Ｈ」レベルになる。一方、偶数番目のオペアンプ１は、自身の正極性入力端子に階調０の階調電圧を、自身に直列に接続される、偶数番目のＤＡＣ回路８より入力する。また、偶数番目のオペアンプ１は、自身の負極性入力端子に階調１の階調電圧を、隣り合う奇数番目のＤＡＣ回路８より入力する。ここで、オペアンプ１の２つの入力端子に接続するＤＡＣ回路８が正常であれば、偶数番目のオペアンプ１の出力は「Ｌ」レベルになる。 Here, considering the case where the value of the counter m is 0, the odd-numbered operational amplifier 1 is connected to the positive-polarity input terminal of the grayscale voltage of grayscale 1 in series with the odd-numbered DAC. Input from circuit 8. In addition, the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent even-numbered DAC circuit 8 to its negative input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 becomes “H” level. On the other hand, the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself. Further, the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from the adjacent odd-numbered DAC circuit 8 to its negative polarity input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “L” level.
　次に、判定回路３はオペアンプ１からの出力のレベルと、自身が記憶する期待値とを比較する（Ｓ１１３）。ここで、判定回路３は、オペアンプ１からの出力が期待値と異なる場合、判定フラグ４に「Ｈ」フラグを出力する。以上のＳ１１２～Ｓ１１４の処理を、カウンタｍの値を１つづつ増やし、カウンタｍの値がｎ－１となるまで繰り返し行う（Ｓ１１５、Ｓ１１６）。 Next, the determination circuit 3 compares the level of the output from the operational amplifier 1 with the expected value stored in itself (S113). Here, the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value. The above processes of S112 to S114 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n−1 (S115, S116).
　（実施形態２の動作確認テスト３）
　次に、第２の実施形態に係る、動作確認テストの３つ目の手順を、図１９を参照して以下に説明する。図１９は、第２の実施形態に係る、動作確認テストの３つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 3 of Embodiment 2)
Next, a third procedure of the operation check test according to the second embodiment will be described below with reference to FIG. FIG. 19 is a flowchart showing a third procedure of the operation check test according to the second embodiment.
　第１の実施形態の動作確認テスト３において説明したように、ＤＡＣ回路８において、出力がオープンとなる不具合がある場合、実行済の確認テストによる、オペアンプ１の入力された階調電圧を、オペアンプ１が保持し続け、実施形態２の動作確認テスト１および２において、不具合を検出できない場合がある。 As described in the operation check test 3 of the first embodiment, when there is a problem that the output is open in the DAC circuit 8, the gradation voltage input to the operational amplifier 1 by the executed check test is used as the operational amplifier. 1 may continue to be held, and in the operation check tests 1 and 2 of the second embodiment, there may be a case where a failure cannot be detected.
　まず、動作確認テスト１～２と同様に、制御回路は、自身が備えるカウンタｍの値を０に初期化する（Ｓ１２１）。また、集積回路２０は、ＤＡＣ回路８の正極性入力端子に、プルアップ・プルダウン回路５を接続している。ここで、奇数番目のオペアンプ１の正極性入力端子をプルアップするように、制御回路は、プルアップ・プルダウン回路５を制御する（Ｓ１２２）。結果、奇数番目のＤＡＣ回路８の出力がオープンとなる場合に、奇数番目のオペアンプ１の正極性入力端子に高い電圧を入力することになる。一方、偶数番目のオペアンプ１の正極性入力端子については、プルダウンとなるように、制御回路は、プルアップ・プルダウン回路５を制御する（Ｓ１２２）。結果、偶数番目のＤＡＣ回路８の出力がオープンとなる場合に、偶数番目のオペアンプ１の正極性入力端子に低い電圧を入力することになる。 First, similarly to the operation check tests 1 and 2, the control circuit initializes the value of the counter m included therein to 0 (S121). In the integrated circuit 20, the pull-up / pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8. Here, the control circuit controls the pull-up / pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier 1 (S122). As a result, when the output of the odd-numbered DAC circuit 8 is open, a high voltage is input to the positive input terminal of the odd-numbered operational amplifier 1. On the other hand, the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled down (S122). As a result, when the output of the even-numbered DAC circuit 8 is open, a low voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
　この後のＳ１２３～Ｓ１２７の処理については、第２の実施形態の動作確認テスト１と同様であるため、ここではその説明を省略する。 Since the subsequent processes of S123 to S127 are the same as those in the operation check test 1 of the second embodiment, the description thereof is omitted here.
　（実施形態２の動作確認テスト４）
　次に、第２の実施形態に係る、動作確認テストの４つ目の手順を、図２０を参照して以下に説明する。図２０は、第２の実施形態に係る、動作確認テストの４つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 4 of Embodiment 2)
Next, a fourth procedure of the operation check test according to the second embodiment will be described below with reference to FIG. FIG. 20 is a flowchart showing a fourth procedure of the operation check test according to the second embodiment.
　ここでは、上記の動作確認テスト３と同様の不具合を検出することを目的としている。まず、これまでの動作確認テストと同様に、制御回路は、自身が備えるカウンタｍの値を０に初期化する（Ｓ１３１）。次に、制御回路は、奇数番目のオペアンプ１の正極性入力端子をプルダウンするように、プルアップ・プルダウン回路５を制御する（Ｓ１２２）。結果、奇数番目のＤＡＣ回路８の出力がオープンとなる場合に、奇数番目のオペアンプ１の正極性入力端子に低い電圧を入力することになる。一方、偶数番目のオペアンプ１の正極性入力端子については、プルアップとなるように、制御回路は、プルアップ・プルダウン回路５を制御する（Ｓ１２２）。結果、偶数番目のＤＡＣ回路８の出力がオープンとなる場合に、偶数番目のオペアンプ１の正極性入力端子に高い電圧を入力することになる。 Here, the purpose is to detect the same defect as in the operation check test 3 described above. First, as in the previous operation check test, the control circuit initializes the value of the counter m included in the control circuit to 0 (S131). Next, the control circuit controls the pull-up / pull-down circuit 5 so as to pull down the positive input terminal of the odd-numbered operational amplifier 1 (S122). As a result, when the output of the odd-numbered DAC circuit 8 is open, a low voltage is input to the positive input terminal of the odd-numbered operational amplifier 1. On the other hand, the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled up (S122). As a result, when the output of the even-numbered DAC circuit 8 is open, a high voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
　この後のＳ１３３～Ｓ１３７の処理については、第２の実施形態の動作確認テスト２と同様であるため、ここではその説明を省略する。 Since the subsequent processing of S133 to S137 is the same as the operation check test 2 of the second embodiment, the description thereof is omitted here.
　（実施形態２の動作確認テスト５）
　次に、第２の実施形態に係る、動作確認テストの５つ目の手順を、図２１を参照して以下に説明する。図２１は、第２の実施形態に係る、動作確認テストの５つ目の手順を示すフローチャート図である。 (Operation Confirmation Test 5 of Embodiment 2)
Next, a fifth procedure of the operation check test according to the second embodiment will be described below with reference to FIG. FIG. 21 is a flowchart showing a fifth procedure of the operation check test according to the second embodiment.
　第１の実施形態の動作確認テスト５において説明したように、ＤＡＣ回路８においては、自身における隣接する２つ階調がショートするという不具合が発生する場合がある。第２の実施形態の動作確認テスト５においては、このような不具合を検出することが目的である。 As described in the operation check test 5 of the first embodiment, the DAC circuit 8 may have a problem that two adjacent gray scales in itself are short-circuited. The purpose of the operation check test 5 of the second embodiment is to detect such a problem.
　同図に示すように、まず、制御回路は、自身が備えるカウンタｍの値を０に初期化する（Ｓ１４１）。次に、ＴＳＴＲ１およびＴＳＴＲ２をアクティブにし、さらに、データバスを介して、階調ｍの階調データを、サンプリング回路２６Ａ、サンプリング回路２６Ｂ、およびサンプリング回路６が入力する。さらに、データＬＯＡＤ信号をアクティブにすることにより、奇数番目のＤＡＣ回路８および偶数番目のＤＡＣ回路８は、同じ階調ｍの階調電圧を出力することになる（Ｓ１４２）。次に、図示しないスイッチを介して、制御回路は、オペアンプ１の正極性入力端子と負極性入力端子とをショートさせる。このオペアンプ１の正極性入力端子と負極性入力端子とをショートさせたことにより、オペアンプ１の正極性入力端子および負極性入力端子は、同じ階調電圧を入力することになる。次に、オペアンプ１の正極性入力端子と負極性入力端子とをショートした場合の、オペアンプの出力のレベルを、判定回路３は、期待値として記憶する（Ｓ１４３）。 As shown in the figure, first, the control circuit initializes the value of the counter m included in itself to 0 (S141). Next, TSTR1 and TSTR2 are activated, and further, gradation data of gradation m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 through the data bus. Further, by activating the data LOAD signal, the odd-numbered DAC circuit 8 and the even-numbered DAC circuit 8 output the gradation voltage of the same gradation m (S142). Next, the control circuit short-circuits the positive input terminal and the negative input terminal of the operational amplifier 1 through a switch (not shown). By short-circuiting the positive input terminal and the negative input terminal of the operational amplifier 1, the same gradation voltage is input to the positive input terminal and the negative input terminal of the operational amplifier 1. Next, the determination circuit 3 stores the output level of the operational amplifier when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S143).
　次に、図示しないスイッチをＯＦＦにして、オペアンプ１の正極性入力端子と負極性入力端子とのショートを解除する。このとき、奇数番目のオペアンプ１の正極性入力端子は、自身に直列に接続された奇数番目のＤＡＣ回路８からの、階調ｍの階調電圧が入力され、負極性入力端子には、自身に隣り合う偶数番目のＤＡＣ回路８からの、階調ｍの階調電圧が入力される。一方、偶数番目のオペアンプ１の正極性入力端子は、自身に直列に接続された偶数番目のＤＡＣ回路８からの、階調ｍの階調電圧が入力され、負極性入力端子には、自身に隣り合う奇数番目のＤＡＣ回路８からの、階調ｍの階調電圧が入力される。ここで、判定回路３は、自身が記憶した期待値と、オペアンプ１からの出力とを比較する（Ｓ１４４）。さらに、判定回路３は、オペアンプ１からの出力が、自身が記憶する期待値と異なる場合は、判定フラグ４に「Ｈ」フラグを出力する。さらに、判定フラグ４は、判定回路３より入力した「Ｈ」フラグを、自身の内部に記憶する。 Next, the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1. At this time, the positive polarity input terminal of the odd-numbered operational amplifier 1 is input with the grayscale voltage of grayscale m from the odd-numbered DAC circuit 8 connected in series to itself, Are supplied with the gradation voltage of gradation m from the even-numbered DAC circuit 8 adjacent thereto. On the other hand, the gradation input of the gradation m from the even-numbered DAC circuit 8 connected in series to the positive-polarity input terminal of the even-numbered operational amplifier 1 is input to the negative-polarity input terminal. The gradation voltage of gradation m from the adjacent odd-numbered DAC circuit 8 is input. Here, the determination circuit 3 compares the expected value stored by itself with the output from the operational amplifier 1 (S144). Further, the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value stored by itself. Further, the determination flag 4 stores therein the “H” flag input from the determination circuit 3.
　次に、制御回路は、図示しないスイッチを用いて、ＤＡＣ回路８からの、オペアンプ１の正極性入力端子に入力される信号と、負極性入力端子に入力される信号とを入れ替える（Ｓ１４６）。この後、Ｓ１４７の処理と同じ処理を行う（Ｓ１４７）。また、Ｓ１４５と同様に、判定回路３は、オペアンプ１からの出力が、自身が記憶する期待値と異なる場合には、判定フラグ４に「Ｈ」を出力する（Ｓ１４８）。 Next, the control circuit switches the signal input to the positive input terminal of the operational amplifier 1 and the signal input to the negative input terminal from the DAC circuit 8 using a switch (not shown) (S146). Thereafter, the same processing as S147 is performed (S147). Similarly to S145, when the output from the operational amplifier 1 is different from the expected value stored in the operational amplifier 1, the determination circuit 3 outputs “H” to the determination flag 4 (S148).
　以上のＳ１４２～Ｓ１４８の処理を、カウンタｍの値がｎとなるまで、カウンタｍの値を１つ増加させて繰り返し行う（Ｓ１４９、Ｓ１５０）。 The processes of S142 to S148 described above are repeated by incrementing the value of the counter m by one until the value of the counter m reaches n (S149, S150).
　（実施形態２の自己修復）
　次に、判定フラグ４が「Ｈ」を記憶している場合、言い換えれば、上記動作確認テスト１～５において、ＤＡＣ回路８のいずれかに不具合があると判定回路３が判定した場合の修復について、図２２を参照して以下に説明する。図２２は、不良と判定したＤＡＣ回路８と、予備のＤＡＣ回路２８Ａおよび２８Ｂとを切り替え、自己修復する手順を示すフローチャート図である。 (Self-repair of Embodiment 2)
Next, when the determination flag 4 stores “H”, in other words, in the operation check tests 1 to 5 described above, when the determination circuit 3 determines that any of the DAC circuits 8 is defective. This will be described below with reference to FIG. FIG. 22 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuits 28A and 28B and performing self-repair.
　まず、制御回路は、判定フラグ４が「Ｈ」を記憶しているかどうかを検出する（Ｓ１５１）。制御回路は、判定フラグ４が「Ｈ」を記憶していないことを検出した場合は、Ｓ１５３の処理に移行する。一方、制御回路が、「Ｈ」を記憶している判定フラグ４を検出した場合、「Ｈ」を記憶する判定フラグ４に対応するＤＡＣ回路８を、予備のＤＡＣ回路２８Ａまたは２８Ｂに切り替える。ここで、実施形態２においては、２つのＤＡＣ回路８を１組として動作確認を行っているため、判定フラグ４が「Ｈ」フラグを記憶していたとしても、１組のうちの、どちらのＤＡＣ回路が不良なのか判断がつかない。したがって、実施形態２においては、「Ｈ」を記憶する判定フラグ４に対応する１組のＤＡＣ回路８を、言い換えれば、奇数番目および偶数番目の２つのＤＡＣ回路８を、予備のＤＡＣ回路２８Ａおよび２８Ｂに切り替える（Ｓ１５２）。具体的な説明として、以下においては、ＤＡＣ回路８－１に不具合があるものとして説明する。 First, the control circuit detects whether or not the determination flag 4 stores “H” (S151). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S153. On the other hand, when the control circuit detects the determination flag 4 storing “H”, the DAC circuit 8 corresponding to the determination flag 4 storing “H” is switched to the spare DAC circuit 28A or 28B. Here, in the second embodiment, since the operation confirmation is performed with the two DAC circuits 8 as one set, even if the determination flag 4 stores the “H” flag, It cannot be determined whether the DAC circuit is defective. Therefore, in the second embodiment, the set of DAC circuits 8 corresponding to the determination flag 4 storing “H”, in other words, the odd-numbered and even-numbered DAC circuits 8 are replaced with the spare DAC circuit 28A and Switch to 28B (S152). As a specific description, the following description assumes that the DAC circuit 8-1 has a problem.
　ここで、ＤＡＣ回路８－１に不具合があった場合、動作確認テスト１～５によって、判定回路３－１および３－２は、ともに「Ｈ」を判定フラグ４－１および４－２に出力することになる。さらに判定フラグ４－１および４－２は、判定回路３－１および３－２より入力した「Ｈ」フラグをスイッチ２ｃおよび２ｄに出力し、スイッチ２ｃをＯＦＦ、スイッチ２ｄをＯＮする。結果、サンプリング回路２６ＡはＳＴＲ１信号を入力し、サンプリング回路２６ＢはＳＴＲ２信号を入力する。これにより、サンプリング回路２６Ａは、液晶駆動用信号出力端子ＯＵＴ１に対応する階調データをデータバスより取得することになり、また、サンプリング回路２６Ｂは、液晶駆動用信号出力端子ＯＵＴ２に対応する階調データをデータバスより取得することになる。さらに、スイッチ２ｃがＯＦＦとなることにより、オペアンプ１－１の出力と、液晶駆動用信号出力端子ＯＵＴ１との接続は遮断され、オペアンプ１－２の出力と、液晶駆動用信号出力端子ＯＵＴ２との接続も遮断される。さらに、スイッチ２ｄがＯＮしたことにより、オペアンプ２１Ａの出力は、液晶駆動用信号出力端子ＯＵＴ１に接続し、オペアンプ２１Ｂの出力は、液晶駆動用信号出力端子ＯＵＴ２に接続する。 Here, when there is a problem in the DAC circuit 8-1, the determination circuits 3-1 and 3-2 output “H” to the determination flags 4-1 and 4-2 by the operation check tests 1 to 5. Will do. Further, the determination flags 4-1 and 4-2 output the “H” flag input from the determination circuits 3-1 and 3-2 to the switches 2c and 2d, thereby turning the switch 2c OFF and turning the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 signal, and the sampling circuit 26B inputs the STR2 signal. As a result, the sampling circuit 26A acquires gradation data corresponding to the liquid crystal driving signal output terminal OUT1 from the data bus, and the sampling circuit 26B acquires the gradation data corresponding to the liquid crystal driving signal output terminal OUT2. Data is acquired from the data bus. Further, when the switch 2c is turned OFF, the connection between the output of the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1 is cut off, and the output of the operational amplifier 1-2 and the liquid crystal driving signal output terminal OUT2 are disconnected. The connection is also cut off. Further, when the switch 2d is turned on, the output of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2.
　以上のように、不具合があるＤＡＣ回路８と、これに対となるＤＡＣ回路８とを１組として、予備のＤＡＣ回路２８Ａおよび２８Ｂに切り替えることにより、不具合のあるＤＡＣ回路８を予備のＤＡＣ回路２６Ａまたは２６Ｂに切り替えることができる。 As described above, the defective DAC circuit 8 is switched to the spare DAC circuit 28A and 28B by taking the defective DAC circuit 8 and the DAC circuit 8 paired therewith as a set, thereby switching the defective DAC circuit 8 to the spare DAC circuit. It can be switched to 26A or 26B.
　次に、制御回路は、ｔｅｓｔ信号を「Ｌ」、ｔｅｓｔＢ信号を「Ｈ」にし、通常動作に移行する（Ｓ１５３）。 Next, the control circuit sets the test signal to “L” and the test B signal to “H”, and shifts to normal operation (S153).
　〔実施形態３〕
　以上に説明した実施形態１および実施形態２においては、出力回路ブロック３０（図２を参照）からの階調電圧と、予備出力回路ブロック４０（図２を参照）からの階調電圧とを切り替える切替回路６０（図２を参照）は、集積回路１０および２０に備えられる構成であったが、本発明はこれに限るものではなく、切替回路６０が、表示パネル側に備えられる構成であってもよい。 [Embodiment 3]
In the first and second embodiments described above, the gradation voltage from the output circuit block 30 (see FIG. 2) and the gradation voltage from the standby output circuit block 40 (see FIG. 2) are switched. Although the switching circuit 60 (see FIG. 2) is configured to be provided in the integrated circuits 10 and 20, the present invention is not limited to this, and the switching circuit 60 is configured to be provided on the display panel side. Also good.
　以下に、表示パネル側に切替回路６０を備えた表示部９０’の構成および動作を、本発明に係る第３の実施形態として説明する。なお、本実施形態では、実施形態１と異なる箇所について説明し、重複する箇所についてはその説明を省略する。 Hereinafter, the configuration and operation of the display unit 90 ′ including the switching circuit 60 on the display panel side will be described as a third embodiment according to the present invention. In addition, in this embodiment, a different part from Embodiment 1 is demonstrated and the description is abbreviate | omitted about the overlapping part.
　（表示部９０’の概略構成）
　まず、図２３を参照して、本実施形態に係る表示部９０’の概略構成を説明する。図２３は、表示部９０’の概略構成を示すブロック図である。 (Schematic configuration of display unit 90 ')
First, a schematic configuration of the display unit 90 ′ according to the present embodiment will be described with reference to FIG. FIG. 23 is a block diagram showing a schematic configuration of the display unit 90 ′.
　図２３に示すように、表示部９０’は、表示パネル８０’と、外部より入力される階調データに基づき表示パネル８０’を駆動する集積回路１０’（駆動回路）とを備えている。ここで、集積回路１０’において、実施形態１の集積回路１０と異なる点は、切替回路６０を備えていないことであり、その他の構成は、集積回路１０と同じ構成である。また、表示パネル８０’において、実施形態１の表示パネル８０と異なる点は、切替回路６０を備えていることであり、その他の構成は、表示パネル８０と同じ構成である。 As shown in FIG. 23, the display unit 90 'includes a display panel 80' and an integrated circuit 10 '(drive circuit) that drives the display panel 80' based on gradation data input from the outside. Here, the integrated circuit 10 ′ is different from the integrated circuit 10 of the first embodiment in that the switching circuit 60 is not provided, and the other configuration is the same as that of the integrated circuit 10. The display panel 80 ′ is different from the display panel 80 of the first embodiment in that it includes a switching circuit 60, and other configurations are the same as the display panel 80.
　（表示部９０’の構成）
　次に、図２４を参照して、本実施形態に係る表示部９０’の、より詳細な構成を説明する。図２４は、集積回路１０’の構成を示すブロック図である。 (Configuration of display unit 90 ')
Next, with reference to FIG. 24, a more detailed configuration of the display unit 90 ′ according to the present embodiment will be described. FIG. 24 is a block diagram showing a configuration of the integrated circuit 10 ′.
　図２４に示すよに、集積回路１０’は、階調データ入力端子（図示しない）より、データバスを介してｎ個の出力端子ＯＵＴ１～ＯＵＴｎの各々に対応する階調データが入力されるｎ個のサンプリング回路６と、ｎ個のホールド回路７と、階調データを階調電圧信号に変換するＤＡＣ回路８と、ＤＡＣ回路８からの階調電圧信号に対するバッファ回路の役割を有するオペアンプ１と、ｎ個の判定回路３と、ｎ個のプルアップ・プルダウン回路５とを備えている。 As shown in FIG. 24, the integrated circuit 10 ′ receives n grayscale data corresponding to each of the n output terminals OUT1 to OUTn via a data bus from a grayscale data input terminal (not shown). A sampling circuit 6, n holding circuits 7, a DAC circuit 8 for converting gradation data into a gradation voltage signal, and an operational amplifier 1 serving as a buffer circuit for the gradation voltage signal from the DAC circuit 8; , N determination circuits 3 and n pull-up / pull-down circuits 5 are provided.
　さらに、図２４に示すように、集積回路１０’は、ｔｅｓｔ信号によってＯＮ，ＯＦＦが切替わる複数のスイッチ２ａと、ｔｅｓｔＢ信号によってＯＮ，ＯＦＦが切替わる複数のスイッチ２ｂと、ＬＦ信号によってＯＮ，ＯＦＦが切替わる複数のスイッチ２ｆと、を備えている。なお、スイッチ２ａ、２ｂおよび２ｆは、「Ｈ」の信号を入力された場合にＯＮとなり、「Ｌ」の信号を入力された場合にＯＦＦとなる。さらに、集積回路１０’予備のサンプリング回路２６と、予備のホールド回路２７と、予備のＤＡＣ回路２８と、予備のオペアンプ２１と、予備の出力端子ＯＵＴ０とを、各１回路づつ備えている。 Further, as shown in FIG. 24, the integrated circuit 10 ′ includes a plurality of switches 2a that are switched ON / OFF by a test signal, a plurality of switches 2b that is switched ON / OFF by a test B signal, and an ON, OFF by an LF signal. And a plurality of switches 2f for switching OFF. The switches 2a, 2b, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input. Further, each of the integrated circuit 10 'spare sampling circuit 26, spare hold circuit 27, spare DAC circuit 28, spare operational amplifier 21, and spare output terminal OUT0 is provided.
　一方、表示パネル８０’は、図２４に示すように、集積回路１０’が備える出力端子ＯＵＴ１～ＯＵＴｎの各々に接続する接続端子（図示せず）と、判定フラグ９－１～９－ｎ（以下、総称する場合は、判定フラグ９とする）と、制御回路（図示せず）からのＬＦ信号によってＯＮ，ＯＦＦが切替わるスイッチ２ｆと、ＬＦ信号の反転信号であるＬＦＢ信号によってＯＮ，ＯＦＦが切替わるスイッチ２ｅと、判定フラグ９からの出力信号であるＦｌａｇ１～ＦｌａｇｎによってＯＮ，ＯＦＦが切替わるスイッチ２ｃおよび２ｄと、を備えている。なお、スイッチ２ｄ、２ｅ、および２ｆは、「Ｈ」の信号を入力された場合にＯＮとなり、「Ｌ」の信号を入力された場合にＯＦＦとなる。また、スイッチ２ｃは、「Ｌ」の信号を入力された場合にＯＮとなり、「Ｈ」の信号を入力された場合にＯＦＦとなる。 On the other hand, as shown in FIG. 24, the display panel 80 ′ includes a connection terminal (not shown) connected to each of the output terminals OUT1 to OUTn included in the integrated circuit 10 ′ and determination flags 9-1 to 9-n ( Hereinafter, when collectively referred to as a determination flag 9), a switch 2 f that is switched ON / OFF by an LF signal from a control circuit (not shown), and an ON / OFF by an LFB signal that is an inverted signal of the LF signal. Switch 2e, and switches 2c and 2d that are turned on and off by Flag1 to Flagn that are output signals from the determination flag 9. The switches 2d, 2e, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input. The switch 2c is turned on when an “L” signal is input, and is turned off when an “H” signal is input.
　また、本実施形態における表示パネル８０’は、液晶表示パネルであり、図２４に示すように、集積回路１０’の出力端子ＯＵＴの各々に、スイッチ２ｅおよび２ｃを介して、データ信号線ＳＬ－１～ＳＬ－ｎ（以下、総称する場合、データ信号線ＳＬとする）が接続されている。また、データ信号線ＳＬの各々には、走査信号線ＧＬの本数と同数の画素Ｐが接続されている。なお、図２４においては、データ信号線ＳＬ－１に接続する画素Ｐを画素Ｐ－１とし、データ信号線ＳＬ－ｎに接続する画素Ｐを画素Ｐ－ｎとしている。 Further, the display panel 80 ′ in the present embodiment is a liquid crystal display panel, and as shown in FIG. 24, the data signal line SL− is connected to each of the output terminals OUT of the integrated circuit 10 ′ via the switches 2e and 2c. 1 to SL-n (hereinafter collectively referred to as data signal lines SL) are connected. Further, the same number of pixels P as the number of scanning signal lines GL are connected to each of the data signal lines SL. In FIG. 24, the pixel P connected to the data signal line SL-1 is a pixel P-1, and the pixel P connected to the data signal line SL-n is a pixel Pn.
　（実施形態３の自己修復）
　次に、本実施形態に係る表示部９０’において、動作確認テストを行った結果、判定フラグ４が「Ｈ」フラグを記憶している場合での、自己修復動作について説明する。なお、本実施形態における、動作確認テストの方法は、実施形態１に述べた動作確認テスト１～５と同様であるため、ここでは、動作確認テストの説明は省略する。 (Self-repair of Embodiment 3)
Next, the self-repair operation in the case where the determination flag 4 stores the “H” flag as a result of the operation check test in the display unit 90 ′ according to the present embodiment will be described. The method of the operation check test in this embodiment is the same as that of the operation check tests 1 to 5 described in the first embodiment, and therefore the description of the operation check test is omitted here.
　まず、動作確認テスト１～５が終了した時点においては、ｔｅｓｔ信号は「Ｈ」であり、ｔｅｓｔＢ信号は「Ｌ」となっている。したがって、オペアンプ１と出力端子ＯＵＴとの接続は、スイッチ２ｂによって切り離されている。ここで、制御回路は、動作確認テスト１～５が完了した後、「Ｈ」のＬＦ信号を出力するとともに、「Ｌ」のＬＦＢ信号を出力する。この「Ｈ」のＬＦ信号が出力されることにより、スイッチ２ｆはＯＮし、判定フラグ４の各々は、各出力端子ＯＵＴを介して、各判定フラグ９に接続することになる。さらに、判定フラグ４の各々は、自身が記憶する「Ｈ」フラグまたは「Ｌ」フラグを、Ｆｌａｇ１～Ｆｌａｇｎとして、各出力端子ＯＵＴを介して、各判定フラグ９に出力する。各判定フラグ９は、判定フラグ４より出力されたＦｌａｇ１～Ｆｌａｇｎを、自身の内部メモリに記憶するとともに、自身に接続するスイッチ２ｃおよび２ｄに出力する。なお、ＬＦ信号が「Ｈ」の期間、ＬＦＢ信号が「Ｌ」となることにより、各スイッチ２ｅはＯＦＦとなる。これにより、判定フラグ４が出力するＦｌａｇ１～Ｆｌａｇｎが、データ信号線ＳＬ－１～ＳＬ－ｎに出力されることを防止し、結果、判定フラグ４が出力するＦｌａｇ１～Ｆｌａｇｎが、画素Ｐに影響を及ぼすことはない。 First, when the operation check tests 1 to 5 are completed, the test signal is “H” and the test B signal is “L”. Therefore, the connection between the operational amplifier 1 and the output terminal OUT is disconnected by the switch 2b. Here, after the operation check tests 1 to 5 are completed, the control circuit outputs an “H” LF signal and also outputs an “L” LFB signal. When the “H” LF signal is output, the switch 2 f is turned on, and each determination flag 4 is connected to each determination flag 9 via each output terminal OUT. Further, each of the determination flags 4 outputs the “H” flag or “L” flag stored therein as Flag1 to Flagn to each determination flag 9 via each output terminal OUT. Each determination flag 9 stores Flag1 to Flagn output from the determination flag 4 in its own internal memory and outputs it to the switches 2c and 2d connected to itself. Each switch 2e is turned OFF when the LFB signal becomes “L” during the period when the LF signal is “H”. This prevents Flag1 to Flagn output from the determination flag 4 from being output to the data signal lines SL-1 to SL-n. As a result, Flag1 to Flagn output from the determination flag 4 affects the pixel P. Will not affect.
　以下に、表示部９０’における自己修復動作の詳細な説明として、出力端子ＯＵＴ１に対応する判定フラグ４－１が「Ｈ」フラグを記憶している場合を例にとって説明する。 Hereinafter, as a detailed description of the self-repair operation in the display unit 90 ', a case where the determination flag 4-1 corresponding to the output terminal OUT1 stores the "H" flag will be described as an example.
　まず、出力端子ＯＵＴ１に対応する判定フラグ４－１が「Ｈ」フラグを記憶している場合、言い換えれば、ＤＡＣ回路８－１が不良であった場合、判定フラグ９－１は、判定フラグ４より「Ｈ」フラグが出力され、出力された「Ｈ」フラグを、自身が備える内部メモリに記録する。なお、この例においては、判定フラグ４－２～４－ｎは、「Ｌ」フラグを記録しているものとする。 First, when the determination flag 4-1 corresponding to the output terminal OUT1 stores the “H” flag, in other words, when the DAC circuit 8-1 is defective, the determination flag 9-1 is determined by the determination flag 4 The “H” flag is then output, and the output “H” flag is recorded in the internal memory of the device. In this example, it is assumed that the determination flags 4-2 to 4-n record the “L” flag.
　次に、判定フラグ９－１は、「Ｈ」フラグのＦｌａｇ１を、自身に接続するスイッチ２ｃおよび２ｄに出力する。これにより、判定フラグ９－１に接続するスイッチ２ｃは、出力端子ＯＵＴ１とデータ信号線ＳＬ－１との接続を切断することになり、さらに、判定フラグ９－１に接続するスイッチ２ｄは、出力端子ＯＵＴ０とデータ信号線ＳＬ－１とを接続することになる。一方、判定フラグ９－２～９－ｎの各々は、自身に接続するスイッチ２ｃおよび２ｄに、「Ｌ」フラグのＦｌａｇ２～Ｆｌａｇｎを出力するため、判定フラグ９－２～９－ｎに接続するスイッチ２ｃはＯＮとなり、判定フラグ９－２～９－ｎに接続するスイッチ２ｄはＯＦＦとなる。結果、データ信号線ＳＬ－２～ＳＬ－ｎの各々は、スイッチ２ｅを介して、出力端子ＯＵＴ２～ＯＵＴｎの各々に接続することになる。 Next, the determination flag 9-1 outputs Flag1 of the “H” flag to the switches 2c and 2d connected to the determination flag 9-1. As a result, the switch 2c connected to the determination flag 9-1 disconnects the output terminal OUT1 from the data signal line SL-1, and the switch 2d connected to the determination flag 9-1 The terminal OUT0 and the data signal line SL-1 are connected. On the other hand, each of the determination flags 9-2 to 9-n is connected to the determination flags 9-2 to 9-n in order to output the Flag 2 to Flagn of the “L” flag to the switches 2c and 2d connected thereto. The switch 2c is turned on, and the switch 2d connected to the determination flags 9-2 to 9-n is turned off. As a result, each of the data signal lines SL-2 to SL-n is connected to each of the output terminals OUT2 to OUTn via the switch 2e.
　各判定フラグ９が、判定フラグ４からのＦｌａｇ１～Ｆｌａｇｎに基づいて、自身に接続するスイッチ２ｃおよび２ｄを切り替えた後、制御回路は、「Ｌ」のＬＦ信号を出力するとももに、「Ｈ」のＬＦＢ信号を出力する。これにより、出力端子ＯＵＴ２～ＯＵＴｎの各々と、データ信号線ＳＬ－２～ＳＬ－ｎの各々とが接続することになる。 After each determination flag 9 switches the switches 2c and 2d connected to itself based on Flag1 to Flagn from the determination flag 4, the control circuit outputs an “L” LF signal and outputs “H”. LFB signal is output. As a result, each of the output terminals OUT2 to OUTn is connected to each of the data signal lines SL-2 to SL-n.
　次に、制御回路が、「Ｌ」のＬＦ信号を出力した後、「Ｌ」のｔｅｓｔ信号と、「Ｈ」のｔｅｓｔＢ信号を出力することにより、データ信号線ＳＬ－１は、出力端子ＯＵＴ０を介して、オペアンプ２１の出力に接続し、一方、データ信号線ＳＬ－２～ＳＬ－ｎの各々は、出力端子ＯＵＴ２～ＯＵＴｎを介して、オペアンプ１－２～１－ｎに接続する。なお、サンプリング回路６－１に接続するスイッチ２ｄは、判定フラグ４－１からのＦｌａｇ１によってＯＮしているため、サンプリング回路６－１に入力される階調データ（データ信号線ＳＬ－１に対応する階調データ）は、サンプリング回路２６にも入力される。結果、データ信号線ＳＬ－１には、データ信号線ＳＬ－１に対応する階調データが、出力端子ＯＵＴ１の代わりに、出力端子ＯＵＴ０より入力される。なお、サンプリング回路６および予備のサンプリング回路２６の各々に入力される階調データの切替については、実施形態１における動作と同様でため、ここでは、その詳細な説明を省略する。 Next, after the control circuit outputs the “L” LF signal and then outputs the “L” test signal and the “H” test B signal, the data signal line SL-1 is connected to the output terminal OUT0. The data signal lines SL-2 to SL-n are connected to the operational amplifiers 1-2 to 1-n via the output terminals OUT2 to OUTn. Since the switch 2d connected to the sampling circuit 6-1 is turned on by Flag1 from the determination flag 4-1, the grayscale data (corresponding to the data signal line SL-1) input to the sampling circuit 6-1. Gradation data to be input) is also input to the sampling circuit 26. As a result, gradation data corresponding to the data signal line SL-1 is input to the data signal line SL-1 from the output terminal OUT0 instead of the output terminal OUT1. Note that switching of the gradation data input to each of the sampling circuit 6 and the spare sampling circuit 26 is the same as the operation in the first embodiment, and thus detailed description thereof is omitted here.
　以上のように、表示部９０’は、自己修復動作を行うことにより、不良と検出されたＤＡＣ回路８の代わりに、予備のＤＡＣ回路２８を用いて、データ信号線ＳＬに正常な階調電圧を出力することができる。なお、実施形態１と同様に、本実施形態においても、予備のＤＡＣ回路２８に対応する、予備のサンプリング回路２６およびホールド回路２７を備えている。したがって、ＤＡＣ回路８だけでなく、サンプリング回路６またはホールド回路７に不具合があった場合においても、予備のサンプリング回路２６およびホールド回路２８に切り替えることができる。

　次に、表示部９０’における、電源投入から、動作確認テストを行い、通常動作に移行するまでの手順を、図２５を参照して以下に説明する。図２５は、表示部９０’の電源投入から、動作確認テストを行い通常動作に移行するまでの処理手順を示すフローチャート図である。 As described above, the display unit 90 ′ performs a self-repair operation, so that the normal grayscale voltage is applied to the data signal line SL using the spare DAC circuit 28 instead of the DAC circuit 8 detected as defective. Can be output. Similar to the first embodiment, this embodiment also includes a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.

Next, a procedure in the display unit 90 ′ from when the power is turned on to when the operation check test is performed and the normal operation is started will be described with reference to FIG. FIG. 25 is a flowchart showing a processing procedure from when the display unit 90 ′ is turned on to when an operation check test is performed and the normal operation is started.
　図２５に示すように、まず、表示部９０’は、ユーザーによって電源投入されたことを検出すると、集積回路１０を初期化することにより、判定フラグ４が記憶する全てのフラグを「Ｌ」フラグにする（Ｓ１６１）。次に、制御回路は、ｔｅｓｔ信号を「Ｈ」に、ｔｅｓｔＢ信号を「Ｌ」にし、集積回路１０’を動作確認テストの状態に切り替える（Ｓ１６２）。次に、制御回路および集積回路１０は、上述した動作確認テストを行う（Ｓ１６３）。さらに、全ての動作確認テスト１～５が終了したか否かを、制御回路は確認する（Ｓ１６４）。このＳ１６４において、制御回路が、全ての動作確認テスト１～５が完了していないことを検出すると、表示部９０’は、制御回路からの指示に基づき、処理をＳ１６３に移行し、未完了の動作確認テストを行う。一方、Ｓ１６４において、制御回路は、表示部９０’において全ての動作確認テストが完了したことを確認すると、「Ｈ」のＬＦ信号および「Ｌ」のＬＦＢ信号を出力し、不良となる回路（サンプリング回路６、ホールド回路７、ＤＡＣ回路９、オペアンプ１）を検出した場合は、当該不良回路を、予備の回路（サンプリング回路２６、ホールド回路２７、ＤＡＣ回路２９、オペアンプ２１）に切替、通常動作に移行する（Ｓ１６５）。 As shown in FIG. 25, first, when the display unit 90 ′ detects that the power is turned on by the user, the display unit 90 ′ initializes the integrated circuit 10, thereby setting all the flags stored in the determination flag 4 to the “L” flag. (S161). Next, the control circuit sets the test signal to “H”, the test B signal to “L”, and switches the integrated circuit 10 ′ to the operation check test state (S 162). Next, the control circuit and the integrated circuit 10 perform the above-described operation check test (S163). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed (S164). In S164, when the control circuit detects that all the operation confirmation tests 1 to 5 are not completed, the display unit 90 ′ moves the process to S163 based on an instruction from the control circuit, and has not completed it. Perform an operation check test. On the other hand, in S164, when the control circuit confirms that all the operation confirmation tests are completed in the display unit 90 ′, the control circuit outputs an “H” LF signal and an “L” LFB signal, and becomes a defective circuit (sampling). When the circuit 6, the hold circuit 7, the DAC circuit 9, and the operational amplifier 1) are detected, the defective circuit is switched to a spare circuit (sampling circuit 26, hold circuit 27, DAC circuit 29, operational amplifier 21), and normal operation is performed. Transition is made (S165).
　なお、本実施形態における表示部９０’においては、判定回路３－１における判定結果であるフラグを記憶する回路として、判定フラグ４および判定フラグ９を備える構成であるが、表示部９０’の変形例として、判定フラグ９、スイッチ２ｆ、スイッチ２ｅを備えず、判定フラグ４が、スイッチ２ｃおよび２ｄを制御する構成であってもよい。この場合、スイッチ２ｆおよび２ｅを制御するＬＦ信号およびＬＦＢ信号も不要となる一方、判定フラグ４と、スイッチ２ｃおよび２ｄを接続するための配線および接続端子が必要となる。 Note that the display unit 90 ′ in the present embodiment is configured to include the determination flag 4 and the determination flag 9 as a circuit for storing a flag that is a determination result in the determination circuit 3-1, but the display unit 90 ′ is a modified example. As an example, the determination flag 9, the switch 2f, and the switch 2e may not be provided, and the determination flag 4 may control the switches 2c and 2d. In this case, the LF signal and the LFB signal for controlling the switches 2f and 2e are also unnecessary, while the determination flag 4 and wiring and connection terminals for connecting the switches 2c and 2d are required.
　〔実施形態４〕
　以上に説明した実施形態１～実施形態３においては、集積回路と表示パネルとが、出力端子ＯＵＴを介して接続する構成であったが、出力端子ＯＵＴを介さず、集積回路と表示パネルとが一体となる表示装置も、本発明の範疇に含むものである。 [Embodiment 4]
In the first to third embodiments described above, the integrated circuit and the display panel are connected via the output terminal OUT. However, the integrated circuit and the display panel are not connected via the output terminal OUT. An integrated display device is also included in the scope of the present invention.
　以下に、集積回路と表示パネルとが一体となる表示部９０”を、第４の実施形態として、図２６を参照して説明する。なお、本実施形態に係る表示部９０”は、実施形態１に係る表示部９０の変形例であり、本実施形態では、実施形態１と異なる箇所について説明し、重複する箇所についてはその説明を省略する。 Hereinafter, a display unit 90 ″ in which an integrated circuit and a display panel are integrated will be described as a fourth embodiment with reference to FIG. 26. Note that the display unit 90 ″ according to the present embodiment is an embodiment. 1 is a modification of the display unit 90 according to the first embodiment. In the present embodiment, portions different from those of the first embodiment will be described, and descriptions of overlapping portions will be omitted.
　（表示部９０”の構成）
　まず、図２６を参照して、本実施形態に係る表示部９０”の構成を説明する。図２６は、表示部９０”の構成を示すブロック図である。 (Configuration of display unit 90 ")
First, the configuration of the display unit 90 ″ according to the present embodiment will be described with reference to FIG. 26. FIG. 26 is a block diagram illustrating the configuration of the display unit 90 ″.
　図２６に示すように、表示部９０”は、実施形態１に示した集積回路１０と表示パネル８０との区別はなく、オペアンプ１および２１の出力が、スイッチ２ｂ、２ｃ、および２ｄを介して、データ信号線ＳＬに直接接続している。つまり、本実施形態の表示部９０”において、実施形態１の表示部９０と異なる点は、出力端子ＯＵＴを備えているか否かの違いであり、その他の構成は実施形態１の表示部９０と同じである。 As shown in FIG. 26, the display unit 90 ″ has no distinction between the integrated circuit 10 and the display panel 80 shown in the first embodiment, and the outputs of the operational amplifiers 1 and 21 are connected via the switches 2b, 2c, and 2d. In other words, the display unit 90 ″ of the present embodiment is different from the display unit 90 of the first embodiment in whether or not the output terminal OUT is provided. Other configurations are the same as those of the display unit 90 of the first embodiment.
　なお、本実施形態においては、実施形態１の変形例として説明したが、実施形態２および３も同様に、出力端子ＯＵＴを介さず、集積回路と表示パネルとを一体にした表示装置も、本発明の範疇に含まれることは言うまでもない。 Although the present embodiment has been described as a modification of the first embodiment, similarly to the second and third embodiments, a display device in which an integrated circuit and a display panel are integrated without using the output terminal OUT is also provided. Needless to say, it is included in the scope of the invention.
　（テレビジョンシステム）
　次に、実施形態１に係る表示部９０を備えるテレビジョンシステム３００について、図２７を参照して説明する。なお、図２７は、テレビジョンシステム３００の構成を示すブロック図である。なお、以下では、テレビジョンシステム３００が、実施形態１に係る表示部９０を備えるものとして説明するが、本発明に係るテレビジョンシステムは、これに限るものではなく、表示部９０の代わりに、実施形態２～４に係る表示装置を備える構成であってもよい。 (Television system)
Next, a television system 300 including the display unit 90 according to the first embodiment will be described with reference to FIG. FIG. 27 is a block diagram illustrating a configuration of the television system 300. In the following description, the television system 300 is described as including the display unit 90 according to the first embodiment. However, the television system according to the present invention is not limited to this, and instead of the display unit 90, The display device according to Embodiments 2 to 4 may be provided.
　（テレビジョンシステム３００の構成）
　図２７に示すように、テレビジョンシステム３００は、放送波を受信するアンテナ３０１と、受信した放送波を映像音声信号に復調するチューナー部３０２と、復調された映像音声信号を、映像信号と音声信号とに分離する信号分離部３０３と、分離された映像信号をデジタル映像信号に復号する映像信号処理部３０４と、復号されたデジタル映像信号を、階調データとして取得し、取得した階調データに基づいて映像を表示パネル８０（図２を参照）に表示する表示部９０と、分離された音声信号をデジタル音声信号に復号する音声信号処理部３０５と、復号されたデジタル音声信号を、アナログ音声信号に変換した後、変換したアナログ音声信号を音声としてスピーカより出力する音声信号出力部３０６とを、備えている。 (Configuration of television system 300)
As shown in FIG. 27, a television system 300 includes an antenna 301 that receives a broadcast wave, a tuner unit 302 that demodulates the received broadcast wave into a video / audio signal, and the demodulated video / audio signal as a video signal and an audio. A signal separation unit 303 that separates the signal into a signal, a video signal processing unit 304 that decodes the separated video signal into a digital video signal, and obtains the decoded digital video signal as gradation data. , A display unit 90 that displays video on the display panel 80 (see FIG. 2), an audio signal processing unit 305 that decodes the separated audio signal into a digital audio signal, and the decoded digital audio signal as an analog signal. An audio signal output unit 306 is provided that outputs the converted analog audio signal as audio from a speaker after conversion into the audio signal.
　（テレビジョンシステム３００の動作）
　次に、テレビジョンシステム３００における動作処理を説明する。まず、放送局からの放送波を、アンテナ３０１が受信し、受信した放送波を、チューナー部３０２に出力する。チューナー部３０２は、出力された放送波を映像音声信号に復調し、信号分離部３０３に出力する。信号分離部３０３は、出力された映像音声信号を、映像信号と音声信号とに分離し、それぞれを映像信号処理部３０４および音声信号処理部３０５に出力する。映像信号処理部３０４は、出力された映像信号をデジタル映像信号に復号し、復号したデジタル映像信号を階調データとして表示部９０に出力する。表示部９０は、出力された階調データを、自身が備える表示パネル８０を用いて表示する。一方、音声信号処理部３０５は、信号分離部３０３によって分離された音声信号を、デジタル音声信号に復号し、音声出力部３０６に出力する。音声信号出力部３０６は、出力されたデジタル音声信号をアナログ音声信号に変換した後、自身が備えるスピーカを用いて、アナログ音声信号を音声として出力する。 (Operation of the television system 300)
Next, operation processing in the television system 300 will be described. First, the antenna 301 receives a broadcast wave from a broadcast station, and outputs the received broadcast wave to the tuner unit 302. The tuner unit 302 demodulates the output broadcast wave into a video / audio signal, and outputs it to the signal separation unit 303. The signal separation unit 303 separates the output video / audio signal into a video signal and an audio signal, and outputs them to the video signal processing unit 304 and the audio signal processing unit 305, respectively. The video signal processing unit 304 decodes the output video signal into a digital video signal, and outputs the decoded digital video signal to the display unit 90 as gradation data. The display unit 90 displays the output gradation data using the display panel 80 provided therein. On the other hand, the audio signal processing unit 305 decodes the audio signal separated by the signal separation unit 303 into a digital audio signal and outputs it to the audio output unit 306. The audio signal output unit 306 converts the output digital audio signal into an analog audio signal, and then outputs the analog audio signal as audio using a speaker provided therein.
　なお、本発明に係るテレビジョンシステム３００は、映像音声信号を取得する手段として、アンテナ３０１およびチューナー部３０２を用いて放送局より取得する構成としたが、本発明はこれに限るものではなく、記録媒体より当該記録媒体に記録されたコンテンツデータを読み出す、ＤＶＤプレーヤー等のコンテンツ読み取り装置や、インターネット等よりＰＣ（パーソナルコンピュータ）を介して取得する構成であってもよい。 Note that the television system 300 according to the present invention is configured to acquire from a broadcasting station using the antenna 301 and the tuner unit 302 as means for acquiring a video / audio signal, but the present invention is not limited to this. The content data recorded on the recording medium may be read from the recording medium, and may be acquired via a PC (personal computer) from a content reading device such as a DVD player or the Internet.
　実施形態１および実施形態４において説明した、動作確認テストおよび自己修復の処理動作は、液晶駆動用半導体集積回路１０に電源が投入された直後に行う構成としたが、本発明はこれに限るものではなく、液晶駆動用半導体集積回路１０へ制御信号を入力することにより行う構成にし、任意のタイミングで行ってもよい。例えば、表示装置のコントローラから表示の帰線期間を示す信号を液晶駆動用半導体集積回路１０に入力し、このタイミングで動作確認テスト、自己修復を行ってもよい。 The operation check test and the self-repair processing operation described in the first and fourth embodiments are performed immediately after power is supplied to the liquid crystal driving semiconductor integrated circuit 10, but the present invention is not limited to this. Instead, it may be configured by inputting a control signal to the liquid crystal driving semiconductor integrated circuit 10 and may be performed at an arbitrary timing. For example, a signal indicating a display blanking period may be input to the liquid crystal driving semiconductor integrated circuit 10 from the controller of the display device, and an operation check test and self-repair may be performed at this timing.
　また、動作確認テストおよび自己修復の処理動作は、液晶駆動用半導体集積回路１０に液晶駆動用半導体集積回路１０の異常を検知する回路を構成し、液晶駆動用半導体集積回路１０に異常が発生したときに行ってもよい。例えば、液晶駆動用半導体集積回路１０から出力される信号の電流を検知し、検知した電流が設定電流より多くなった場合、動作確認テストおよび自己修復の処理動作を行ってもよい。 Further, in the operation check test and the self-repair processing operation, the liquid crystal driving semiconductor integrated circuit 10 is configured to detect a malfunction of the liquid crystal driving semiconductor integrated circuit 10, and the liquid crystal driving semiconductor integrated circuit 10 has an abnormality. Sometimes you can go. For example, the current of the signal output from the liquid crystal driving semiconductor integrated circuit 10 may be detected, and when the detected current exceeds the set current, an operation check test and a self-repair processing operation may be performed.
　また、動作確認テストおよび自己修復の処理動作は、定期的に行なってもよい。例えば、表示を行わない垂直帰線期間毎に行なう、または、あらかじめ設定した累計表示時間毎に行ってもよい。 Also, the operation check test and the self-repair processing operation may be performed periodically. For example, it may be performed every vertical blanking period in which no display is performed, or may be performed every preset total display time.
　また、動作確認テストおよび自己修復の処理動作は、表示を行っている期間の一部で行っても良い。例えば、液晶表示装置では画素が表示電圧を記憶するので、表示電圧の充電が終了した後は、液晶駆動用半導体集積回路１０の出力をハイインピーダンスにしても表示に問題ない。表示期間の一部で、液晶駆動用半導体集積回路１０の出力をハイインピーダンスにして、動作確認テストおよび自己修復の処理動作を行う。このとき、動作確認テストのパターンをすべて行う時間が無ければ、１ラインの表示期間の一部で、例えば１パターンの判定を行い、１画面での表示期間もしくは数画面を表示する期間で行う事もできる。 Also, the operation check test and the self-repair processing operation may be performed during a part of the display period. For example, since a pixel stores a display voltage in a liquid crystal display device, there is no problem in display even if the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance after charging of the display voltage is completed. During a part of the display period, the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance, and an operation check test and a self-repair processing operation are performed. At this time, if there is no time for performing all of the operation check test patterns, for example, one pattern is determined in a part of the display period of one line, and it is performed in a display period of one screen or a period of displaying several screens. You can also.
　なお、本発明に係る集積回路１０（図７参照）は、自身の欠陥を自己検出（動作確認テスト）するために、表示パネル８０（図２参照）を駆動するための出力信号を停止する必要がある。すなわち、集積回路１０は、自己検出の期間において、表示パネル８０を駆動できない。したがって、集積回路１０が自己検出を行うタイミングは、表示装置の映像の表示に影響を与えない期間において行う必要がある。 Note that the integrated circuit 10 according to the present invention (see FIG. 7) needs to stop the output signal for driving the display panel 80 (see FIG. 2) in order to self-detect its own defect (operation check test). There is. That is, the integrated circuit 10 cannot drive the display panel 80 during the self-detection period. Therefore, the timing at which the integrated circuit 10 performs self-detection needs to be performed in a period that does not affect the display of video on the display device.
　そこで、本発明に係る実施形態においては、集積回路１０が自己検出を行う期間として、表示装置の電源投入時における起動プロセス中に、集積回路１０が自己検出および自己修復を行うものとして説明した。これは、表示装置の起動プロセス中であれば、表示装置は映像の表示を行っていないため、表示装置の映像の表示に影響を及ぼすことなく、集積回路１０が、自己検出および自己修復を行えるためである。 Therefore, in the embodiment according to the present invention, the case where the integrated circuit 10 performs self-detection and self-repair is described as the period during which the integrated circuit 10 performs self-detection during the startup process when the display device is turned on. This is because the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device because the display device does not display video during the startup process of the display device. Because.
　以上のように、本実施形態における、集積回路１０は、表示装置の電源投入時における起動プロセス中に、自身の欠陥を検出する自己検出を行っていたが、本発明はこれに限るものではなく、表示装置の起動プロセス中以外の期間において、自己検出および自己修復を行うことが可能である。 As described above, the integrated circuit 10 in the present embodiment performs self-detection to detect its own defect during the startup process when the display device is turned on. However, the present invention is not limited to this. Self-detection and self-repair can be performed in a period other than during the startup process of the display device.
　以下に、表示装置に起動プロセス中以外の、自己検出および自己修復を行うことが可能な期間を、実施例として説明する。 Hereinafter, a period in which the display device can perform self-detection and self-repair other than during the startup process will be described as an example.
　〔実施例１〕
　（垂直帰線期間における自己検出および自己修復）
　まず、一つ目の実施例として、表示装置の垂直帰線期間中においては、表示装置の映像の表示に影響を及ぼすことなく、集積回路１０は、自己検出および自己修復を行うことが可能となる。以下にその理由を説明する。 [Example 1]
(Self-detection and self-repair in the vertical blanking period)
First, as a first embodiment, during the vertical blanking period of the display device, the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device. Become. The reason will be described below.
　以下に、表示装置に入力される各信号のタイミングについて、図２８の（ａ）～（ｆ）を参照して説明する。図２８の（ａ）～（ｆ）は、液晶表示装置に入力する各信号のタイミングを示すタイムチャート図である。 Hereinafter, the timing of each signal input to the display device will be described with reference to (a) to (f) of FIG. (A) to (f) of FIG. 28 are time charts showing timings of signals inputted to the liquid crystal display device.
　図２８の（ａ）は、表示装置の走査線を駆動する走査側駆動回路より出力される、表示装置の１本目の走査信号線に与えられる走査信号線ＳＣＮ１を示し、同図の（ｂ）は、走査側駆動回路より出力される、表示装置の２本目の走査信号線に与えられる走査信号線ＳＣＮ２を示し、同図の（ｃ）は、集積回路１０（図７参照）から映像信号反転回路に与えられる、表示装置のｊ本目のデータ信号線に対応する映像信号ＤＳｊを示し、同図の（ｄ）は、映像信号反転回路からデータ側駆動回路に与えられる、表示装置のｊ本目のデータ信号線に対応する映像信号ＤＲＶｊを示し、同図の（ｅ）は、表示装置のｊ本目のデータ信号線に与えられる映像信号ＤＡＴＡｊを示し、同図の（ｆ）は、表示装置における１本目の走査信号線とｊ本目のデータ信号線とに接続される画素に印加される駆動電圧ＶＤ１ｊを示している。また、図２８に示す、時刻ｔ１～ｔ５の期間ＴＶは、表示装置の垂直走査期間であり、期間ＴＶ１は垂直帰線期間であり、時刻ｔ１～ｔ３の期間ＴＨは水平走査期間であり、時刻ｔ２～ｔ３の期間ＴＨ１は水平帰線期間である。なお、上記映像信号反転回路は、水平走査期間ＴＨおよび垂直走査期間ＴＶ毎に、表示装置の各画素における表示電極の極性を反転させるために、集積回路１０からの映像信号ＤＳｊの極性を反転させる回路である。 FIG. 28A shows the scanning signal line SCN1 that is output from the scanning side driving circuit that drives the scanning lines of the display device and is given to the first scanning signal line of the display device, and FIG. Indicates a scanning signal line SCN2 output from the scanning side drive circuit and applied to the second scanning signal line of the display device, and (c) in FIG. 8 is a video signal inversion from the integrated circuit 10 (see FIG. 7). A video signal DSj corresponding to the j-th data signal line of the display device, which is given to the circuit, is shown, and (d) in the same figure shows the j-th data signal line from the video signal inversion circuit to the data side drive circuit. The video signal DRVj corresponding to the data signal line is shown, (e) in the figure shows the video signal DATAj given to the jth data signal line of the display device, and (f) in the figure shows 1 in the display device. The first scanning signal line and the jth It shows a driving voltage VD1j applied to pixels connected to the data signal line. 28, a period TV from time t1 to t5 is a vertical scanning period of the display device, a period TV1 is a vertical blanking period, a period TH from time t1 to t3 is a horizontal scanning period, A period TH1 from t2 to t3 is a horizontal blanking period. The video signal inversion circuit inverts the polarity of the video signal DSj from the integrated circuit 10 in order to invert the polarity of the display electrode in each pixel of the display device every horizontal scanning period TH and vertical scanning period TV. Circuit.
　図２８の（ａ）および（ｂ）に示すように、走査側駆動回路は、表示装置の各走査信号線に対して、走査信号線の１本目から、順次水平走査ＴＨずつタイミングを遅延させて、走査信号ＳＣＮ１、走査信号ＳＣＮ２、…、走査信号ＳＣＮｍを出力する。また、走査側駆動回路は、各走査信号ＳＣＮ１～走査信号ＳＣＮｍを、表示装置の各走査信号線に対して、垂直走査期間ＴＶ毎に繰り返し出力する。なお、ここでは、表示装置は、ｍ本の走査信号線を有するものである。 As shown in (a) and (b) of FIG. 28, the scanning side drive circuit sequentially delays the timing by the horizontal scanning TH from the first scanning signal line for each scanning signal line of the display device. , Scan signal SCN1, scan signal SCN2,..., Scan signal SCNm. Further, the scanning side driving circuit repeatedly outputs each scanning signal SCN1 to scanning signal SCNm to each scanning signal line of the display device every vertical scanning period TV. Note that here, the display device has m scanning signal lines.
　図２８の（ｃ）に示す、集積回路１０からの映像信号ＤＳｊは、映像信号反転回路に入力される。次に、映像信号反転回路は、映像信号ＤＳｊを、水平走査期間ＴＨ毎に極性を反転するとともに、垂直走査期間ＴＶ毎にも極性を反転し、図２８の（ｄ）に示す映像信号ＤＲＶｊを生成する。さらに映像信号反転回路は、生成した映像信号ＤＲＶｊを、データ側駆動回路に入力する。 28 (c), the video signal DSj from the integrated circuit 10 is input to the video signal inversion circuit. Next, the video signal inversion circuit inverts the polarity of the video signal DSj every horizontal scanning period TH and also inverts the polarity every vertical scanning period TV, so that the video signal DRVj shown in FIG. Generate. Further, the video signal inversion circuit inputs the generated video signal DRVj to the data side driving circuit.
　次に、データ側駆動回路は、映像信号反転回路からの映像信号ＤＲＶｊを、水平走査期間ＴＨ毎にサンプリングし、サンプリングした信号値を、一水平走査期間ＴＨ遅延させて、図２８の（ｅ）に示す映像信号ＤＡＴＡｊとして、表示装置のｊ本目のデータ信号線に出力する。 Next, the data side driving circuit samples the video signal DRVj from the video signal inverting circuit every horizontal scanning period TH, delays the sampled signal value by one horizontal scanning period TH, and (e) of FIG. Is output to the jth data signal line of the display device.
　次に、１本目の走査信号線とｊ本目のデータ信号線とに接続している表示装置の画素（以下、画素１ｊとする）においては、時刻ｔ１～ｔ２の水平走査期間ＴＨにおける走査信号ＳＣＮ１によって、画素１ｊ内のＴＦＴが導通し、結果、ｊ本目のデータ信号線を介して、時刻ｔ１～ｔ２における映像信号ＤＡＴＡｊの映像信号電圧が、駆動電圧ＶＤ１ｊとして、画素１ｊ内の表示電極に印加される。ここで、画素１ｊの表示電極に印加された駆動電圧ＶＤ１ｊは、時刻ｔ２～ｔ５において、画素１ｊ内のＴＦＴの導通が遮断されても、時刻ｔ１～ｔ２の間の電圧レベルを保持し続ける。同様に、２本目の走査信号線とｊ本目のデータ信号線とに接続している表示装置の画素（以下、画素２ｊとする）においては、時刻ｔ３～ｔ４の水平走査期間ＴＨにおける走査信号ＳＣＮ２によって、画素２ｊ内のＴＦＴが導通し、結果、ｊ本目のデータ信号線を介して、時刻ｔ３～ｔ４における映像信号ＤＡＴＡｊの映像信号電圧が、駆動電圧として画素２ｊ内の表示電極に印加される。ここでも、画素２ｊの表示電極に印加された駆動電圧は、画素２ｊ内のＴＦＴの導通が遮断されても、時刻ｔ３～ｔ４の間の電圧レベルを保持し続けることになる。 Next, in the pixel of the display device (hereinafter referred to as pixel 1j) connected to the first scanning signal line and the jth data signal line, the scanning signal SCN1 in the horizontal scanning period TH from time t1 to t2 is used. As a result, the TFT in the pixel 1j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t1 to t2 is applied to the display electrode in the pixel 1j via the jth data signal line as the drive voltage VD1j. Is done. Here, the drive voltage VD1j applied to the display electrode of the pixel 1j continues to hold the voltage level during the time t1 to t2 even when the TFT in the pixel 1j is cut off during the time t2 to t5. Similarly, in the pixel of the display device (hereinafter referred to as pixel 2j) connected to the second scanning signal line and the jth data signal line, the scanning signal SCN2 in the horizontal scanning period TH from time t3 to t4. As a result, the TFT in the pixel 2j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t3 to t4 is applied to the display electrode in the pixel 2j via the jth data signal line as a drive voltage. . Again, the drive voltage applied to the display electrode of the pixel 2j continues to hold the voltage level between times t3 and t4 even when the TFT in the pixel 2j is turned off.
　以上のように、表示装置の各画素における駆動電圧は、各画素内のＴＦＴの導通が遮断されても、ＴＦＴの導通時に印加された駆動電圧の電圧レベルを保持し続ける。よって、走査側駆動回路が、各画素のＴＦＴを導通させる走査信号ＳＣＮ１～ＳＣＮｍを、走査信号線に出力していない、言い換えれば、各画素のＴＦＴの導通が遮断している期間である、垂直帰線期間ＴＶ１においては、表示装置は、各画素の表示電極に電圧を印加する必要がない。つまり、駆動電圧の基となる映像信号ＤＳｊを、集積回路１０は出力する必要がなく、集積回路１０と、表示装置とを電気的に切り離しても、表示装置の映像の表示に影響を及ぼすことはない。 As described above, the drive voltage in each pixel of the display device continues to maintain the voltage level of the drive voltage applied when the TFT is turned on even if the TFT in each pixel is turned off. Therefore, the scanning-side driving circuit does not output the scanning signals SCN1 to SCNm for conducting the TFTs of the respective pixels to the scanning signal line, in other words, the period in which the conduction of the TFTs of the respective pixels is cut off. In the blanking period TV1, the display device does not need to apply a voltage to the display electrode of each pixel. That is, it is not necessary for the integrated circuit 10 to output the video signal DSj that is the basis of the drive voltage, and even if the integrated circuit 10 and the display device are electrically disconnected, the display of the video on the display device is affected. There is no.
　したがって、表示装置の垂直帰線期間であれば、表示装置の映像の表示に影響を及ぼすことなく、集積回路１０は、自己検出および自己修復を行うことができる。 Therefore, during the vertical blanking period of the display device, the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device.
　（集積回路１０全体の動作不良検出）
　本実施形態における、集積回路１０が行う、自身が備える出力回路ブロックの不良を検出する自己検出処理は、各データ信号線ごとに対応する、出力回路ブロック毎に、かつ、各出力回路ブロック全てを対象としている。よって、この自己検出処理は、時間を要することになる。 (Detection of malfunction of entire integrated circuit 10)
In the present embodiment, the integrated circuit 10 performs a self-detection process for detecting a defect in an output circuit block included in the integrated circuit 10 for each output circuit block corresponding to each data signal line and for all the output circuit blocks. It is targeted. Therefore, this self-detection process takes time.
　このことから、集積回路１０が備える各出力回路ブロックに、動作不良が起こっている可能性がない場合に、集積回路１０が自己検出処理を行う必要はない。言い換えれば、各出力回路ブロックに、動作不良が起こっている可能性がある場合のみ、集積回路１０は、自己検出処理を行えばよい。 Therefore, the integrated circuit 10 does not need to perform self-detection processing when there is no possibility of malfunction in each output circuit block included in the integrated circuit 10. In other words, the integrated circuit 10 only needs to perform self-detection processing only when there is a possibility of malfunction in each output circuit block.
　ここで、集積回路１０は、集積回路１０全体に対して、動作不良の可能性があるかどうかを判定する動作判定回路を備え、動作判定回路によって、集積回路１０のどこかに動作不良があると判定された場合にのみ、自己検出処理を行えば、無駄な自己検出処理を行うことを防止できる。 Here, the integrated circuit 10 includes an operation determination circuit that determines whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10, and there is an operation failure somewhere in the integrated circuit 10 by the operation determination circuit. If the self-detection process is performed only when it is determined, it is possible to prevent performing a useless self-detection process.
　以下に、集積回路１０が備える、集積回路１０全体に対して、動作不良の可能性があるかどうかを判定する動作判定回路２００について、図２９～図３１を参照して説明する。 Hereinafter, the operation determination circuit 200 for determining whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10 included in the integrated circuit 10 will be described with reference to FIGS. 29 to 31. FIG.
　まず、集積回路１０に動作不良が発生した場合、集積回路１０に供給される電源電流は、正常動作時と比べて、言い換えれば、製品として出荷される時に良品と判定された初期段階と比べて多くなる。したがって、集積回路１０に供給される電源電流の値が、正常動作時に比べて一定の値以上大きくなった場合に、集積回路１０に動作不良が発生していることになる。そこで、動作判定回路２００は、集積回路１０に供給される電源電流の値を検出し、検出した電源電流の値から、集積回路１０に動作不良が発生しているかどうかを判定する。 First, when an operation failure occurs in the integrated circuit 10, the power supply current supplied to the integrated circuit 10 is compared with that during normal operation, in other words, compared with the initial stage that is determined to be good when shipped as a product. Become more. Therefore, when the value of the power supply current supplied to the integrated circuit 10 becomes larger than a certain value compared with the normal operation, an operation failure has occurred in the integrated circuit 10. Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 10 and determines whether an operation failure has occurred in the integrated circuit 10 from the detected value of the power supply current.
　（動作判定回路２００の構成）
　以下に、動作判定回路２００の構成を、図２９を参照して説明する。図２９は、動作判定回路２００の構成を示すブロック図である。 (Configuration of Operation Determination Circuit 200)
Hereinafter, the configuration of the operation determination circuit 200 will be described with reference to FIG. FIG. 29 is a block diagram showing a configuration of the operation determination circuit 200.
　図２９に示すように、動作判定回路２００は、集積回路１０の電源を供給するＶＡ２０１と、集積回路１０との間に、抵抗２０２（検出手段）およびスイッチ２０３を備えている。なお、抵抗２０２とスイッチ２０３とは、互いに並列となるように接続されている。さらに、動作判定回路２００は、抵抗２０２およびスイッチ２０３の、集積回路１０側の一端に接続された、Ａ／Ｄコンバータ２０４（検出手段）と、Ａ／Ｄコンバータ２０４からの出力信号を入力するスイッチ２０５と、スイッチ２０５の一方の出力端子に接続された不揮発性メモリーであるＥＥＰＲＯＭ２０６（正常電流値記憶手段）と、スイッチ２０５のもう一方の出力端視に接続されたデータラッチ回路２０７と、ＥＥＰＲＯＭ２０６の出力値とデータラッチ回路２０７からの出力値とを比較する比較回路２０８（電流値比較手段、駆動回路判定手段）と、を備えている。なお、比較回路２０８の出力端子は、比較回路２０８における比較結果を、集積回路１０が備える制御回路に接続している。なお、スイッチ２０３および２０５の切替は、集積回路１０が備える制御回路によって制御される。 29, the operation determination circuit 200 includes a resistor 202 (detection means) and a switch 203 between the integrated circuit 10 and the VA 201 that supplies power to the integrated circuit 10. The resistor 202 and the switch 203 are connected so as to be parallel to each other. Further, the operation determination circuit 200 includes an A / D converter 204 (detection means) connected to one end of the resistor 202 and the switch 203 on the integrated circuit 10 side, and a switch for inputting an output signal from the A / D converter 204. 205, an EEPROM 206 (normal current value storage means) which is a nonvolatile memory connected to one output terminal of the switch 205, a data latch circuit 207 connected to the other output terminal of the switch 205, and an EEPROM 206 A comparison circuit 208 (current value comparison means, drive circuit determination means) that compares the output value with the output value from the data latch circuit 207 is provided. Note that the output terminal of the comparison circuit 208 connects the comparison result in the comparison circuit 208 to a control circuit included in the integrated circuit 10. Note that switching of the switches 203 and 205 is controlled by a control circuit included in the integrated circuit 10.
　（動作判定回路２００の概略動作）
　動作判定回路２００は、予め、集積回路１０の正常動作時における電源電流値に応じた値を、基準データとしてＥＥＰＲＯＭ２０６に記憶しておく。ここで、動作判定回路２００は、集積回路１０に動作不良が発生しているかどうかを判定する場合、集積回路１０に供給される電源電流値に応じた値を検出し、この検出した値と予めＥＥＰＲＯＭ２０６が記憶する基準データの値とを比較し、検出した値が一定の値以上の場合に、集積回路１０に動作不良が発生していると判定する。さらに、動作判定回路２００は、集積回路１０に動作不良が発生していることを示す信号を、集積回路１０が備える制御回路に対して出力することにより、制御回路は、集積回路１０の自己検出処理および自己修復処理を開始する。 (Schematic operation of the operation determination circuit 200)
The operation determination circuit 200 previously stores a value corresponding to the power supply current value during normal operation of the integrated circuit 10 in the EEPROM 206 as reference data. Here, when determining whether or not an operation failure has occurred in the integrated circuit 10, the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit 10, The value of the reference data stored in the EEPROM 206 is compared, and if the detected value is equal to or greater than a certain value, it is determined that an operation failure has occurred in the integrated circuit 10. Further, the operation determination circuit 200 outputs a signal indicating that an operation failure has occurred in the integrated circuit 10 to the control circuit included in the integrated circuit 10, so that the control circuit detects the self-detection of the integrated circuit 10. Start processing and self-healing process.
　（基準データの生成および記憶処理）
　上述したように、動作判定回路２００は、予め、基準データを、自身が備えるＥＥＰＲＯＭ２０６に記憶しておく必要がある。そこで、以下に、動作判定回路２００がＥＥＰＲＯＭ２０６に基準データを記憶するための処理を、図３０を参照して説明する。図３０は、動作判定回路２００が、基準データをＥＥＰＲＯＭ２０６に記憶する動作処理を示すフローチャート図である。 (Generation and storage of reference data)
As described above, the operation determination circuit 200 needs to store the reference data in the EEPROM 206 provided therein in advance. Therefore, hereinafter, a process for the operation determination circuit 200 to store the reference data in the EEPROM 206 will be described with reference to FIG. FIG. 30 is a flowchart showing an operation process in which the operation determination circuit 200 stores reference data in the EEPROM 206.
　図３０に示すように、基準データの生成にあたり、制御回路が、スイッチ２０３を開放し、抵抗２０２にＶＡ２０１からの電源電流が流れるようにする（Ｓ３０１）。ここで、抵抗２０２の抵抗値は、集積回路１０の正常動作時における抵抗２０２の電圧降下が約０．１Ｖとなるような抵抗値である。なお、抵抗２０２の抵抗値は、集積回路の消費電流を考慮して決定されることが好ましい。 As shown in FIG. 30, in generating the reference data, the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S301). Here, the resistance value of the resistor 202 is a resistance value such that the voltage drop of the resistor 202 during the normal operation of the integrated circuit 10 is about 0.1V. Note that the resistance value of the resistor 202 is preferably determined in consideration of current consumption of the integrated circuit.
　次に、抵抗２０２の集積回路１０側の一端の電圧値を、Ａ／Ｄコンバータ２０４がデジタル値に変換する（Ｓ３０２）。Ａ／Ｄコンバータ２０４は、変換したデジタル値を、スイッチ２０５を介して、ＥＥＰＲＯＭ２０６に入力する。ＥＥＰＲＯＭ２０６は、入力されたＡ／Ｄコンバータからのデジタル値を、基礎データとして記憶する（Ｓ３０３）。なお、Ｓ３０３におけるスイッチ２０５は、制御回路によって、Ａ／Ｄコンバータ２０４とＥＥＰＲＯＭ２０６とを接続するように、切替られているものとする。 Next, the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S302). The A / D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205. The EEPROM 206 stores the input digital value from the A / D converter as basic data (S303). Note that the switch 205 in S303 is switched by the control circuit so as to connect the A / D converter 204 and the EEPROM 206.
　次に、ＥＥＰＲＯＭ２０６が基礎データを記憶した後、制御回路が、スイッチ２０３を短絡し、集積回路１０を通常動作状態に戻す（Ｓ３０４）。なお、Ｓ３０１～Ｓ３０４までの、基準データの生成および記憶処理は、集積回路１０を備える表示装置の製品出荷段階、言い換えれば、集積回路１０が様々な出荷検査によって正常と判定された段階において、行われる。 Next, after the EEPROM 206 stores the basic data, the control circuit short-circuits the switch 203 and returns the integrated circuit 10 to the normal operation state (S304). The generation and storage processing of the reference data from S301 to S304 is performed at the product shipment stage of the display device including the integrated circuit 10, in other words, at the stage where the integrated circuit 10 is determined to be normal by various shipment inspections. Is called.
　（動作判定回路２００による動作不良検出処理）
　次に、動作判定回路２００における、集積回路１０の動作不良を検出する処理を、図３１を参照して、以下に説明する。図３１は、動作判定回路２００における、集積回路１０の動作不良を検出する処理を示すフローチャート図である。 (Operation failure detection processing by the operation determination circuit 200)
Next, processing for detecting an operation failure of the integrated circuit 10 in the operation determination circuit 200 will be described below with reference to FIG. FIG. 31 is a flowchart showing processing for detecting an operation failure of the integrated circuit 10 in the operation determination circuit 200.
　図３１に示すように、まず、制御回路がスイッチ２０３を開放し、抵抗２０２にＶＡ２０１からの電源電流が流れるようにする（Ｓ３０５）。 As shown in FIG. 31, first, the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S305).
　次に、抵抗２０２の集積回路１０側の一端の電圧値を、Ａ／Ｄコンバータ２０４がデジタル値に変換する（Ｓ３０６）。Ａ／Ｄコンバータ２０４は、変換したデジタル値を、スイッチ２０５を介して、データラッチ回路２０７に入力する。データラッチ回路２０７は、入力されたＡ／Ｄコンバータからのデジタル値を、検出データとして記憶する（Ｓ３０７）。なお、Ｓ３０６におけるスイッチ２０５は、制御回路によって、Ａ／Ｄコンバータ２０４とデータラッチ回路２０７とを接続するように、切替られているものとする。 Next, the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S306). The A / D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205. The data latch circuit 207 stores the input digital value from the A / D converter as detection data (S307). Note that the switch 205 in S306 is switched by the control circuit so as to connect the A / D converter 204 and the data latch circuit 207.
　次に、比較回路２０８は、ＥＥＰＲＯＭ２０６が記憶する基準データと、データラッチ回路２０７が記憶する検出データとを読み出し、読み出した基準データの値と、検出データの値とを比較する（Ｓ３０８）。さらに比較回路２０８は、基準データの値と、検出データの値との差が、所定の値以上（例えば、デジタル値で３以上）であるかどうかを検出する（Ｓ３０９）。ここで、基準データの値と、検出データの値との差が所定の値以上（例えば、デジタル値で３以上）であった場合に、集積回路１０に動作不良が発生していることを示す信号を、集積回路１０が備える制御回路に出力する。 Next, the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data stored in the data latch circuit 207, and compares the value of the read reference data with the value of the detection data (S308). Further, the comparison circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is equal to or greater than a predetermined value (for example, 3 or more as a digital value) (S309). Here, when the difference between the value of the reference data and the value of the detection data is equal to or greater than a predetermined value (for example, 3 or more as a digital value), it indicates that an operation failure has occurred in the integrated circuit 10. The signal is output to a control circuit included in the integrated circuit 10.
　ここで、制御回路は、比較回路２０８より、集積回路１０に動作不良が発生していることを示す信号を入力されると、集積回路１０の自己検出を開始する（Ｓ３１１）。さらに、集積回路１０の自己検出において、集積回路１０が自身の出力回路ブロックに不具合を検出した場合、集積回路１０は、不具合の出力回路ブロックの出力と、予備の出力回路ブロックの出力を切替え、自己修復を行う。なお、Ｓ３１１の集積回路１０の自己検出において、出力回路ブロックの不具合を検出できない場合は、他の要因による電源電流値の変動と考えれる。したがって、この場合は、電源電流値に変動が生じているため、動作判定回路２００は、Ｓ３０１～Ｓ３０４に示した基準データを生成および記憶処理を行い、変動が生じている電源電流値を、新たな基準データとしてＥＥＰＲＯＭ２０６に記憶する（Ｓ３１２）。さらに、Ｓ３１２の後、制御回路が、スイッチ２０３を短絡し、動作判定回路２００および集積回路１０を通常動作状態にする（Ｓ３１０）。 Here, when the control circuit 208 receives a signal indicating that a malfunction has occurred in the integrated circuit 10 from the comparison circuit 208, the control circuit starts self-detection of the integrated circuit 10 (S311). Further, in the self-detection of the integrated circuit 10, when the integrated circuit 10 detects a failure in its own output circuit block, the integrated circuit 10 switches between the output of the defective output circuit block and the output of the spare output circuit block, Perform self-healing. Note that if the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 10 in S311, it is considered that the power supply current value varies due to other factors. Therefore, in this case, since the power supply current value fluctuates, the operation determination circuit 200 generates and stores the reference data shown in S301 to S304, and the power supply current value that has fluctuated is newly set. The reference data is stored in the EEPROM 206 (S312). Further, after S312, the control circuit short-circuits the switch 203 to place the operation determination circuit 200 and the integrated circuit 10 in a normal operation state (S310).
　一方、Ｓ３０９において、比較回路２０８が、基準データの値と、検出データの値との差が所定の値未満（例えば、デジタル値で３未満）であることを検出した場合は、Ｓ３１０に処理が移行する。 On the other hand, if the comparison circuit 208 detects in S309 that the difference between the reference data value and the detected data value is less than a predetermined value (for example, less than 3 as a digital value), the process proceeds to S310. Transition.
　〔実施例２〕
　（定期的な集積回路１０の自己検出）
　また、集積回路１０の自己検出（動作確認テスト）および自己修復を、定期的に行ってもよい。具体的には、上述の実施例１において説明した、表示装置の垂直帰線期間毎に、集積回路１０の自己検出（動作確認テスト）および自己修復を行ってもよい。この場合、垂直同期信号をカウントし、一定回数の表示毎に行う。この場合、不揮発性のメモリーにてカウンタを構成し、カウンタが垂直同期信号の回数をカウントすることにより実現できる。さらに、集積回路１０が時間を測定するタイマを備え、このタイマにより、動作時間をカウントし、予め設定した累計動作時間毎に、集積回路１０の自己検出および自己修復を行う構成としてもよい。 [Example 2]
(Periodic self-detection of the integrated circuit 10)
Further, self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed periodically. Specifically, the self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed for each vertical blanking period of the display device described in the first embodiment. In this case, the vertical synchronization signal is counted and is displayed every certain number of times. In this case, the counter can be configured by a non-volatile memory and the counter can count the number of vertical synchronization signals. Further, the integrated circuit 10 may be provided with a timer for measuring time, the operation time is counted by this timer, and the integrated circuit 10 is self-detected and self-repaired every preset accumulated operation time.
　〔実施例３〕
　また、集積回路１０の自己検出（動作確認テスト）および自己修復の処理動作は、表示装置が映像の表示を行っている期間の一部で行っても良い。例えば、表示装置の各画素は、表示電極の電圧を記憶するため、表示電極の電圧の充電が終了した後は、集積回路１０の出力端子ＯＵＴ１～ＯＵＴｎを、ハイインピーダンスにしても、表示装置における映像の表示に問題はない。 Example 3
Further, the self-detection (operation check test) and self-repair processing operation of the integrated circuit 10 may be performed during a part of a period during which the display device displays an image. For example, since each pixel of the display device stores the voltage of the display electrode, after charging of the voltage of the display electrode is finished, the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, There is no problem with the video display.
　したがって、表示装置が映像の表示を行っている表示期間の一部において、集積回路１０の出力端子ＯＵＴ１～ＯＵＴｎをハイインピーダンスにして、自己検出（動作確認テスト）および自己修復の処理動作を行う。出力端子ＯＵＴ１～ＯＵＴｎをハイインピーダンスにする方法の一例として、出力端子ＯＵＴ１～ＯＵＴｎと、表示装置とを接続する信号伝送路毎に対して、直列にスイッチを設け、このスイッチを開放することにより、出力端子ＯＵＴ１～ＯＵＴｎと、表示装置とをハイインピーダンスとする、言い換えれば、電気的に切り離すことができる。 Therefore, in a part of the display period in which the display device displays an image, the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, and self-detection (operation check test) and self-repair processing operations are performed. As an example of a method for setting the output terminals OUT1 to OUTn to high impedance, by providing a switch in series for each signal transmission path connecting the output terminals OUT1 to OUTn and the display device, and opening the switch, The output terminals OUT1 to OUTn and the display device have high impedance, in other words, can be electrically disconnected.
　また、自己検出（動作確認テスト）には、本実施形態１に説明したように、いくつかのパターンがある。そこで、自己検出（動作確認テスト）のパターンをすべて行う時間が無ければ、１ラインの表示期間の一部において、自己検出（動作確認テスト）の一部のパターン（例えば１パターンのみ）を行ってもよい。これにより、自己検出（動作確認テスト）の全てのパターンを、表示装置の１フレーム分の表示期間、または、数フレーム分の表示期間において行うことができる。また、自己検出（動作確認テスト）のパターンを、一度に行わず、各パターンを分割して行う上記手法を使用すれば、図２８に示す水平帰線期間において、自己検出（動作確認テスト）を行うことができる。 Further, as described in the first embodiment, there are several patterns for self-detection (operation check test). Therefore, if there is no time to perform all of the self-detection (operation check test) patterns, a part of the self-detection (operation check test) pattern (for example, only one pattern) is performed during a part of the display period of one line. Also good. Thereby, all the patterns of self-detection (operation check test) can be performed in the display period of one frame of the display device or in the display period of several frames. In addition, if the above-described method is used in which each pattern is divided without performing self-detection (operation confirmation test) patterns at once, self-detection (operation confirmation test) is performed in the horizontal blanking period shown in FIG. It can be carried out.
　なお、上記実施例１～３においては、実施形態１における集積回路１０を対象として説明したが、本発明はこれに限るものではなく、実施形態２および３における集積回路１０’、２０、および、実施形態４における表示部９０”に対しても適用できる。 In the first to third embodiments, the integrated circuit 10 in the first embodiment has been described. However, the present invention is not limited to this, and the integrated circuits 10 ′, 20 and in the second and third embodiments, and The present invention can also be applied to the display unit 90 ″ in the fourth embodiment.
　また、本実施形態１～４においては、液晶表示パネルによって映像を表示する液晶表示装置について説明したが、本発明はこれに限るものでなく、液晶表示装置以外の表示装置、例えばプラズマテレビ等にも適用できる。 Further, in the first to fourth embodiments, the liquid crystal display device that displays an image by the liquid crystal display panel has been described. However, the present invention is not limited to this, and the present invention is not limited to the liquid crystal display device, such as a plasma television. Is also applicable.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
　なお、本発明の表示装置駆動用の集積回路、および、表示装置を以下のように構成してもよい。 The display device driving integrated circuit and the display device of the present invention may be configured as follows.
　〔第１の構成〕
　表示パネルに接続された出力端子と、
　上記出力端子に接続可能であり上記表示パネルを駆動するための出力信号を出力する出力回路を含む出力回路ブロックと、
　上記出力端子に接続可能であり上記表示パネルに上記出力信号を出力可能な予備出力回路を含む予備出力回路ブロックとを備えた、上記表示パネルを駆動する駆動回路であって、
　不良になった当該駆動回路を自己修復する自己修復手段を備え、
　上記自己修復手段は、
　　上記出力回路からの出力信号と、上記予備出力回路からの出力信号とを比較する比較手段と、
　　上記比較手段の比較結果に基づき、上記出力回路が不良か否かを判定する判定手段と、
　　上記判定手段の判定結果が不良である場合、上記出力端子に、上記出力回路の代わりに上記予備出力回路を接続させる接続切替手段と、を備え、
　上記出力回路ブロックおよび上記予備出力回路ブロックは、さらに、オペアンプを使用した出力バッファを含み、上記比較手段として上記オペアンプを使用することを特徴とする駆動回路。 [First configuration]
An output terminal connected to the display panel;
An output circuit block including an output circuit that can be connected to the output terminal and outputs an output signal for driving the display panel;
A drive circuit for driving the display panel, comprising a spare output circuit block including a spare output circuit connectable to the output terminal and capable of outputting the output signal to the display panel;
Self-healing means to self-repair the drive circuit that has become defective,
The self-healing means is
Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit;
Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means;
If the determination result of the determination means is bad, the output terminal comprises a connection switching means for connecting the spare output circuit instead of the output circuit,
The output circuit block and the spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means.
　〔第２の構成〕
　上記出力回路ブロックおよび上記予備出力回路ブロックは、さらに、出力回路の入力に与える信号を記憶する回路を含むことを特徴とする第１の構成に記載の駆動回路。 [Second configuration]
The drive circuit according to the first configuration, wherein the output circuit block and the spare output circuit block further include a circuit for storing a signal applied to an input of the output circuit.
　〔第３の構成〕
　上記出力回路および予備出力回路に入力する入力信号を制御する制御手段を備え、
　上記制御手段は、
　　上記出力回路と予備出力回路とに、異なる大きさの入力信号を入力するとともに、
　　上記異なる大きさの入力信号に対応する、上記比較手段からの比較結果の期待値を出力し、
　上記判定手段は、上記比較結果と上記期待値とが異なる場合に、上記出力回路を不良と判定することを特徴とする、第１の構成または第２の構成に記載の駆動回路。 [Third configuration]
Control means for controlling input signals to be input to the output circuit and the standby output circuit,
The control means includes
While inputting input signals of different magnitudes to the output circuit and the standby output circuit,
Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
The drive circuit according to the first configuration or the second configuration, wherein the determination unit determines that the output circuit is defective when the comparison result and the expected value are different.
　〔第４の構成〕
　上記判定手段の判定結果を示すフラグを格納するフラグ格納手段をさらに備え、
　上記接続切替手段は、上記フラグの値が、上記出力回路が不良であることを示すとき、上記出力端子に、上記出力回路の代わりに上記予備出力回路を接続させることを特徴とする、第１の構成から第３の構成までのいずれかに記載の駆動回路。 [Fourth configuration]
Flag storage means for storing a flag indicating the determination result of the determination means;
The connection switching means connects the spare output circuit to the output terminal instead of the output circuit when the value of the flag indicates that the output circuit is defective. The drive circuit according to any one of the configuration from the third configuration to the third configuration.
　〔第５の構成〕
　上記表示パネルが表示する画像に影響を与えない期間に、
　　上記比較手段は、上記出力回路からの出力信号と上記予備出力回路からの出力信号とを比較し、
　　上記判定手段は、上記比較手段による比較結果に基づき、上記出力回路が不良か否かを判定し、
　　上記接続切替手段は、上記出力端子に対する接続を、上記判定手段によって不良と判定された出力回路の出力から、上記予備出力回路の出力に切り替え、
　　上記接続切替手段が、上記出力端子と上記予備出力回路の出力とを接続した後、上記予備出力回路が上記出力端子に出力信号を出力することを特徴とする、第１の構成から第４の構成のいずれかに記載の駆動回路。 [Fifth Configuration]
During a period that does not affect the image displayed on the display panel,
The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit,
After the connection switching means connects the output terminal and the output of the auxiliary output circuit, the auxiliary output circuit outputs an output signal to the output terminal. The drive circuit according to any one of the configurations.
　〔第６の構成〕
　上記駆動回路に供給される電源電流の値を検出する検出手段と、
　上記駆動回路の正常動作時における上記電源電流の値を、予め記憶する正常電流値記憶手段と、
　上記検出手段からの電源電流の値と、上記正常電流値記憶手段からの電源電流の値とを比較する電流値比較手段と、
　上記電流値比較手段の比較結果に基づき、上記駆動回路が不良か否かを判定する駆動回路判定手段と、をさらに備え、
　上記駆動回路判定手段の判定結果が不良である場合に、
　　上記比較手段は、上記出力回路からの出力信号と上記予備出力回路からの出力信号とを比較し、
　　上記判定手段は、上記比較手段による比較結果に基づき、上記出力回路が不良か否かを判定し、
　　上記接続切替手段は、上記出力端子に対する接続を、上記判定手段によって不良と判定された出力回路の出力から、上記予備出力回路の出力に切り替えることを特徴とする、第１の構成から第５の構成までのいずれか１つの構成に記載の駆動回路。 [Sixth configuration]
Detection means for detecting the value of the power supply current supplied to the drive circuit;
Normal current value storage means for storing in advance the value of the power supply current during normal operation of the drive circuit;
Current value comparison means for comparing the value of the power supply current from the detection means with the value of the power supply current from the normal current value storage means;
Drive circuit determination means for determining whether or not the drive circuit is defective based on a comparison result of the current value comparison means;
When the determination result of the drive circuit determination means is bad,
The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit. The drive circuit according to any one of the configurations up to the configuration.
　〔第７の構成〕
　上記表示パネルの電源投入直後に、
　　上記比較手段は、上記出力回路からの出力信号と上記予備出力回路からの出力信号とを比較し、
　　上記判定手段は、上記比較手段による比較結果に基づき、上記出力回路が不良か否かを判定し、
　　上記接続切替手段は、上記出力端子に対する接続を、上記判定手段によって不良と判定された出力回路の出力から、上記予備出力回路の出力に切り替えることを特徴とする、第１の構成から第６の構成までのいずれかに記載の駆動回路。 [Seventh configuration]
Immediately after the display panel is turned on,
The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit. The drive circuit according to any one of the configurations up to.
　〔第８の構成〕
　上記表示パネルの垂直帰線期間に、
　　上記比較手段は、上記出力回路からの出力信号と上記予備出力回路からの出力信号とを比較し、
　　上記判定手段は、上記比較手段による比較結果に基づき、上記出力回路が不良か否かを判定し、
　　上記接続切替手段は、上記出力端子に対する接続を、上記判定手段によって不良と判定された出力回路の出力から、上記予備出力回路の出力に切り替えることを特徴とする、第１の構成から第６の構成までのいずれかに記載の駆動回路。 [Eighth configuration]
During the vertical blanking period of the display panel,
The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit. The drive circuit according to any one of the configurations up to.
　〔第９の構成〕
　上記出力端子から上記表示パネルへの信号伝送路を遮断する遮断手段を、さらに備え、
　上記遮断手段が、上記出力端子から上記表示パネルへの信号伝送路を遮断した後に、
　　上記比較手段は、上記出力回路からの出力信号と上記予備出力回路からの出力信号とを比較し、
　　上記判定手段は、上記比較手段による比較結果に基づき、上記出力回路が不良か否かを判定し、
　　上記接続切替手段は、上記出力端子に対する接続を、上記判定手段によって不良と判定された出力回路の出力から、上記予備出力回路の出力に切り替えることを特徴とする、第１の構成から第８の構成までのいずれかに記載の駆動回路。 [Ninth Configuration]
A blocking means for blocking a signal transmission path from the output terminal to the display panel;
After the blocking means blocks the signal transmission path from the output terminal to the display panel,
The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit. The drive circuit according to any one of the configurations up to.
　〔第１０の構成〕
　表示パネルに接続されたＮ（Ｎ：正の偶数）個の出力端子と、
　上記各出力端子に接続可能であり上記表示パネルを駆動するための出力信号を出力する出力回路を含むＮ個の出力回路ブロックと、
　上記奇数番目の出力端子に接続可能であり上記表示パネルに上記出力信号を出力可能な第１予備出力回路を含む第１予備出力回路ブロックと、
　上記偶数番目の出力端子に接続可能であり上記表示パネルに上記出力信号を出力可能な第２予備出力回路を含む第２予備出力回路ブロックとを備えた、上記表示パネルを駆動する駆動回路であって、
　不良になった当該駆動回路を自己修復する自己修復手段を備え、
　上記自己修復手段は、
　　上記出力回路からの出力信号と、当該出力回路に隣接する出力回路からの出力信号とを比較する比較手段と、
　　上記比較手段の比較結果に基づき、上記出力回路および当該出力回路に隣接する出力回路が不良か否かを判定する判定手段と、
　　上記判定手段の判定結果が不良である場合、上記出力端子に、上記出力回路および当該出力回路に隣接する出力回路の代わりに上記第１予備出力回路および第２予備出力回路をそれぞれ接続させる接続切替手段と、を備え、
　上記出力回路ブロック、上記第１予備出力回路ブロック、および上記第２予備出力回路ブロックは、さらに、オペアンプを使用した出力バッファを含み、上記比較手段として上記オペアンプを使用することを特徴とする駆動回路。 [Tenth Configuration]
N (N: positive even number) output terminals connected to the display panel;
N output circuit blocks including an output circuit that is connectable to each of the output terminals and outputs an output signal for driving the display panel;
A first auxiliary output circuit block including a first auxiliary output circuit connectable to the odd numbered output terminal and capable of outputting the output signal to the display panel;
A drive circuit for driving the display panel, comprising: a second spare output circuit block including a second spare output circuit that can be connected to the even-numbered output terminals and can output the output signal to the display panel. And
Self-healing means to self-repair the drive circuit that has become defective,
The self-healing means is
Comparison means for comparing the output signal from the output circuit and the output signal from the output circuit adjacent to the output circuit;
Determination means for determining whether or not the output circuit and the output circuit adjacent to the output circuit are defective based on the comparison result of the comparison means;
Connection switching for connecting the first spare output circuit and the second spare output circuit to the output terminal instead of the output circuit and the output circuit adjacent to the output circuit, respectively, when the judgment result of the judging means is bad Means, and
The output circuit block, the first spare output circuit block, and the second spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means. .
　〔第１１の構成〕
　上記出力回路、上記第１予備出力回路、および上記第２予備出力回路に入力する入力信号を制御する制御手段を備え、
　上記制御手段は、
　　上記奇数番目の出力回路および上記第１予備出力回路と、上記偶数番目の出力回路および上記第２予備出力回路とに、異なる大きさの入力信号を入力するとともに、
　　上記異なる大きさの入力信号に対応する、上記比較手段からの比較結果の期待値を出力し、
　上記判定手段は、上記比較結果と上記期待値とが異なる場合に、上記出力回路および当該出力回路に隣接する出力回路を不良と判定することを特徴とする、第１０の構成に記載の駆動回路。 [Eleventh configuration]
Control means for controlling an input signal input to the output circuit, the first auxiliary output circuit, and the second auxiliary output circuit;
The control means includes
The odd-numbered output circuit and the first spare output circuit, and the even-numbered output circuit and the second spare output circuit are inputted with different magnitude input signals,
Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
The drive circuit according to the tenth configuration, wherein the determination unit determines that the output circuit and an output circuit adjacent to the output circuit are defective when the comparison result and the expected value are different. .
　〔第１２の構成〕
　第１の構成から第１１の構成までのいずれかに記載の駆動回路と、上記表示パネルとを、備えていることを特徴とする表示装置。 [Twelfth configuration]
A display device comprising: the drive circuit according to any one of the first configuration to the eleventh configuration; and the display panel.
　〔第１３の構成〕
　表示パネルと、
　上記表示パネルを駆動するための出力信号を、上記表示パネルに接続された出力端子から出力する出力回路を含む駆動回路と、を備えた表示装置であって、
　上記駆動回路は、
　　上記表示パネルに上記出力信号を出力可能な予備出力回路と、
　　上記出力回路からの出力信号と、上記予備出力回路からの出力信号とを比較する比較手段と、
　　上記比較手段の比較結果に基づき、上記出力回路が不良か否かを判定する判定手段とを備え、
　上記表示パネルは、
　　上記判定手段からの判定結果が不良であった場合、当該表示パネルを駆動する出力信号として、上記不良となった出力回路からの出力信号を、上記予備出力回路からの出力信号に切り替える切替手段を、備え、
　上記駆動回路では、上記比較手段として、上記出力回路および上記予備出力回路の出力バッファに使用されたオペアンプを使用することを特徴とする表示装置。 [13th Configuration]
A display panel;
A drive circuit including an output circuit for outputting an output signal for driving the display panel from an output terminal connected to the display panel, and a display device comprising:
The drive circuit is
A preliminary output circuit capable of outputting the output signal to the display panel;
Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit;
Determination means for determining whether or not the output circuit is defective based on the comparison result of the comparison means;
The display panel
Switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel when the determination result from the determination means is defective. , Prepared,
In the drive circuit, an operational amplifier used as an output buffer of the output circuit and the spare output circuit is used as the comparison means.
　〔第１４の構成〕
　表示パネルと、
　上記表示パネルを駆動するための出力信号を出力する出力回路と、
　上記表示パネルに上記出力信号を出力可能な予備出力回路と、
　上記出力回路からの出力信号と、上記予備出力回路からの出力信号とを比較する比較手段と、
　上記比較手段の比較結果に基づき、上記出力回路が不良か否かを判定する判定手段と、
　上記判定手段の判定結果が不良である場合、上記表示パネルを駆動する出力信号として、上記不良となった出力回路からの出力信号を、上記予備出力回路からの出力信号に切り替える切替手段と、を備え、
　上記比較手段として、上記出力回路および上記予備出力回路の出力バッファに使用されたオペアンプを使用することを特徴とする表示装置。 [Fourteenth Configuration]
A display panel;
An output circuit for outputting an output signal for driving the display panel;
A preliminary output circuit capable of outputting the output signal to the display panel;
Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit;
Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means;
When the determination result of the determination means is defective, a switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel, Prepared,
An operational amplifier used in the output buffer of the output circuit and the spare output circuit is used as the comparison means.
　〔第１５の構成〕
　第１２の構成から第１４の構成までのいずれか１項に記載の表示装置を備えていることを特徴とするテレビジョンシステム。 [Fifteenth configuration]
A television system comprising the display device according to any one of the twelfth configuration to the fourteenth configuration.
　（実施形態の総括）
　本実施形態に係る表示部９０は、表示パネル８０と、表示パネル８０を駆動する駆動回路であって、表示パネル８０との電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する液晶駆動用半導体集積回路１０とを備え、上記自己検出・自己修復手段は、上記表示パネルに表示すべき画像が不連続に切り替わるときに、上記駆動回路の不良を検出する処理を実行する。 (Summary of embodiment)
The display unit 90 according to the present embodiment is a display panel 80 and a drive circuit that drives the display panel 80, and detects a failure of the drive circuit in a state where the electrical connection with the display panel 80 is disconnected. A liquid crystal driving semiconductor integrated circuit 10 having a self-detection / self-repair means for repairing, and the self-detection / self-recovery means is configured to switch the drive circuit when the image to be displayed on the display panel is switched discontinuously. A process for detecting a defect is executed.
　上記の構成によれば、液晶駆動用半導体集積回路１０は、表示パネル８０を駆動する。そして、液晶駆動用半導体集積回路１０は、液晶駆動用半導体集積回路１０自身の不良を検出可能であり、検出した不良を修復する自己検出・自己修復手段とを有している。液晶駆動用半導体集積回路１０は、自身の不良を検出し修復する処理を、表示パネル８０との電気的な接続を切り離した状態で実行する。つまり、液晶駆動用半導体集積回路１０は、表示パネル８０との電気的接続を切り離して自身の不良を検出する（すなわち自己検出する）ことで、表示パネル８０に表示中の画像を表す階調データだけでなく、全ての階調データを用いて自己検出の処理を実行することができる。なお、画像は、静止画像であってもよいし、動画像すなわち映像であってもよい。 According to the above configuration, the liquid crystal driving semiconductor integrated circuit 10 drives the display panel 80. The liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect. The liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected. In other words, the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80. In addition, the self-detection process can be executed using all the gradation data. The image may be a still image or a moving image, that is, a video.
　そして、上記の構成によれば、自己検出・自己修復手段は、表示パネル８０に表示すべき画像が不連続に切り替わるときに、駆動回路の不良を検出する処理を実行する。例えば、自己検出・自己修復手段は、１チャンネルから２チャンネルへの切替によって、１チャンネルの画像信号に基づく表示が中断する場合に、表示パネル８０に表示すべき画像が不連続に切り替わるときに、液晶駆動用半導体集積回路１０の不良を検出する処理を実行する。また、例えば、自己検出・自己修復手段は、番組からＣＭへの移行によって、番組を表す画像信号に基づく表示が中断する場合に、表示パネル８０に表示すべき画像が不連続に切り替わるときに、液晶駆動用半導体集積回路１０の不良を検出する処理を実行する。 And according to the above configuration, the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit when the image to be displayed on the display panel 80 is switched discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed. Further, for example, when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM, the self-detecting / self-repairing means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed.
　これにより、本実施形態に係る表示部９０によれば、表示部９０の動作において、表示に影響のない期間に、自己検出の処理を実行することができる。つまり、本実施形態に係る表示部９０は、表示パネル８０との電気的な接続を切り離した状態で液晶駆動用半導体集積回路１０の不良を検出する処理を実行するが、表示部９０の画面において現在表示中の内容が一旦途切れるタイミングで、自己検出の処理を実行するため、ユーザに違和感を感じさせることがない。したがって、本実施形態に係る表示部９０によれば、ユーザの視聴を妨げずに適切なタイミングにおいて、自己検出および自己修復の処理を実行することが可能となり、ユーザにとっての利便性を向上させることができる。 Thereby, according to the display unit 90 according to the present embodiment, in the operation of the display unit 90, the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected. Since the self-detection process is executed at the timing when the currently displayed content is temporarily interrupted, the user does not feel uncomfortable. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
　本実施形態に係る表示部９０では、上記処理は、１つ以上の工程を含む複数の工程群に分割され、上記自己検出・自己修復手段は、表示パネル８０における上記表示が１回中断するごとに、上記工程群を１つずつ実行することが好ましい。 In the display unit 90 according to the present embodiment, the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair unit performs the display on the display panel 80 once. In addition, it is preferable to execute the above process group one by one.
　上記の構成によれば、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理には、複数の工程が含まれ、それらの工程は複数の工程群に分割される。そして、自己検出・自己修復手段は、表示パネル８０に供給中の画像信号に基づく表示が１回中断するごとに、上記工程群を１つずつ実行する。例えば、工程群の数がｎの場合、上記表示がｎ回中断したときに、自己検出処理に含まれる全ての工程を完了させることができる。 According to the above configuration, the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10, that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups. The self-detecting / self-repairing unit executes the above process group one by one every time the display based on the image signal being supplied to the display panel 80 is interrupted once. For example, when the number of process groups is n, all the processes included in the self-detection process can be completed when the display is interrupted n times.
　これにより、自己検出処理に含まれる工程の数が多く、全ての自己検出処理が完了するまでに長時間を要する場合であっても、表示パネル８０の表示が１回中断するごとに実行される工程群の処理時間はそれほど長くならないため、ユーザに違和感を感じさせずに、自己検出および自己修復の処理を実行することが可能となる。 As a result, even if the number of processes included in the self-detection process is large and it takes a long time to complete all the self-detection processes, the process is executed each time the display on the display panel 80 is interrupted. Since the processing time of the process group does not become so long, it is possible to execute self-detection and self-repair processing without making the user feel uncomfortable.
　本実施形態に係る表示部９０では、上記処理は、複数の工程を含んでおり、上記自己検出・自己修復手段は、上記表示パネルにおける上記表示が１回中断したときに、上記処理に含まれる全ての工程を実行することが好ましい。 In the display unit 90 according to the present embodiment, the process includes a plurality of steps, and the self-detection / self-repair means is included in the process when the display on the display panel is interrupted once. It is preferable to carry out all the steps.
　上記の構成によれば、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理には、複数の工程が含まれるが、自己検出・自己修復手段は、表示パネル８０に供給中の画像信号に基づく表示が１回中断したときに、自己検出処理に含まれる全ての工程を実行する。 According to the above configuration, the process for detecting a defect of the semiconductor integrated circuit 10 for driving the liquid crystal, that is, the self-detection process includes a plurality of steps, and the self-detection / self-repair means is supplied to the display panel 80. When the display based on the middle image signal is interrupted once, all the steps included in the self-detection process are executed.
　これにより、液晶駆動用半導体集積回路１０の自己検出および自己修復の処理を、短時間で完了させることが可能となる。 Thereby, the self-detection and self-repair processing of the liquid crystal driving semiconductor integrated circuit 10 can be completed in a short time.
　本実施形態に係る表示部９０では、ユーザによる選局操作を受け付けるリモコンＩ／Ｆ４０１と、リモコンＩ／Ｆ４０１が受け付けた選局操作に対応する放送を受信し、該放送の画像信号を上記表示パネルに供給するチューナーと、チューナーが受信する放送を切り替える際に、表示パネル８０に表示すべき画像が不連続に切り替わることを検知するコントローラ１００とをさらに備え、上記自己検出・自己修復手段は、コントローラ１００によって表示パネル８０に表示すべき画像の切替が検知されたときに、液晶駆動用半導体集積回路１０の不良を検出する処理を開始することが好ましい。 The display unit 90 according to the present embodiment receives a remote control I / F 401 that receives a channel selection operation by a user and a broadcast corresponding to the channel selection operation received by the remote control I / F 401, and displays the image signal of the broadcast on the display panel. And a controller 100 that detects that an image to be displayed on the display panel 80 switches discontinuously when switching between broadcasts received by the tuner, and the self-detection / self-repair means includes a controller When switching of an image to be displayed on the display panel 80 is detected by 100, it is preferable to start processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10.
　上記の構成によれば、リモコンＩ／Ｆ４０１はユーザによる放送番組の選局を受け付ける。また、チューナーは、リモコンＩ／Ｆ４０１が受け付けた選局に対応する放送を受信し、当該放送の画像信号を表示パネルに供給する。例えば、チューナーがユーザによって指定されたチャンネルの放送を受信して映像信号を表示パネル８０に供給する。 According to the above configuration, the remote control I / F 401 receives a broadcast program tuning by the user. Further, the tuner receives a broadcast corresponding to the channel selection accepted by the remote control I / F 401 and supplies an image signal of the broadcast to the display panel. For example, the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
　また、上記の構成によれば、コントローラ１００は、チューナーがユーザの選局に応じて放送を新たに受信することによって、表示パネル８０における上記表示が中断するときに、表示パネル８０に表示すべき画像が不連続に切り替わることを検知する。例えば、表示パネル８０において１チャンネルの放送を表示中にユーザが２チャンネルを選局した場合、チューナーが２チャンネルの放送を受信するために、１チャンネルの表示が中断するときに、表示パネル８０に表示すべき画像が不連続に切り替わることを検知する。 Further, according to the above configuration, the controller 100 should display the display panel 80 when the display is interrupted by the tuner receiving a new broadcast in response to the user's channel selection. Detect that the images switch discontinuously. For example, when the user selects channel 2 while displaying a one-channel broadcast on display panel 80, when display of one channel is interrupted because the tuner receives the two-channel broadcast, display panel 80 It detects that the image to be displayed switches discontinuously.
　そして、自己検出・自己修復手段は、チューナーが受信する放送を切り替える際に、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理を開始する。 Then, the self-detecting / self-repairing means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detecting process when switching the broadcast received by the tuner.
　これにより、ユーザによって新たな選局操作が行われた場合に表示部９０の画面における表示が途切れるタイミングにおいて、自己検出の処理を実行することが可能となる。したがって、自己検出処理によって一瞬画面表示されない期間が生じても、ユーザに違和感を感じさせることがない。 This makes it possible to execute the self-detection process at a timing when the display on the display unit 90 is interrupted when a new channel selection operation is performed by the user. Therefore, even if there is a period when the screen is not displayed for a moment due to the self-detection process, the user does not feel uncomfortable.
　本実施形態に係る表示部９０では、放送を受信し、該放送の画像信号を表示パネル８０に供給するチューナーと、チューナーが受信する放送の内容が番組からＣＭ（Commercial Message）に切り替わる際に、表示パネル８０に表示すべき画像が不連続に切り替わることを検知するコントローラ１００とをさらに備え、上記自己検出・自己修復手段は、コントローラ１００によって表示パネル８０に表示すべき画像の切替が検知されたときに、液晶駆動用半導体集積回路１０の不良を検出する処理を実行することが好ましい。 In the display unit 90 according to the present embodiment, a tuner that receives a broadcast and supplies an image signal of the broadcast to the display panel 80, and when the content of the broadcast received by the tuner is switched from a program to a CM (Commercial Message), And a controller 100 for detecting that the image to be displayed on the display panel 80 switches discontinuously, and the self-detection / self-repair means detects the switching of the image to be displayed on the display panel 80 by the controller 100. Sometimes, it is preferable to execute a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10.
　上記の構成によれば、チューナーは、放送を受信し、当該放送の画像信号を表示パネル８０に供給する。例えば、チューナーがユーザによって指定されたチャンネルの放送を受信して映像信号を表示パネル８０に供給する。 According to the above configuration, the tuner receives a broadcast and supplies an image signal of the broadcast to the display panel 80. For example, the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
　また、上記の構成によれば、コントローラ１００は、表示パネル８０に供給される画像信号が、放送に含まれる番組を表す画像信号から、放送に含まれるＣＭを表す画像信号に切り替わるために、上記番組を表す画像信号に基づく表示が中断するときに、表示パネル８０に表示すべき画像が不連続に切り替わることを検知する。つまり、コントローラ１００は、放送中の番組がＣＭに移行することによって、番組を表す画像信号に基づく表示が中断するときに、表示パネル８０に表示すべき画像が不連続に切り替わること検知する。 Further, according to the above configuration, the controller 100 switches the image signal supplied to the display panel 80 from the image signal representing the program included in the broadcast to the image signal representing the CM included in the broadcast. When the display based on the image signal representing the program is interrupted, it is detected that the image to be displayed on the display panel 80 switches discontinuously. That is, the controller 100 detects that the image to be displayed on the display panel 80 is switched discontinuously when the display based on the image signal representing the program is interrupted by the program being broadcast being shifted to the CM.
　そして、自己検出・自己修復手段は、コントローラ１００によって表示パネル８０における上記表示の中断を検知したときに、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理を開始する。 Then, the self-detection / self-repair means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detection process when the controller 100 detects the interruption of the display on the display panel 80.
　これにより、放送中の番組がＣＭへ移行する場合に表示部９０の画面における番組の表示が途切れるタイミングにおいて、自己検出の処理を実行することが可能となる。したがって、自己検出処理によって一瞬画面表示されない期間が生じても、ユーザに違和感を感じさせることがない。 This makes it possible to execute the self-detection process at the timing when the display of the program on the screen of the display unit 90 is interrupted when the program being broadcast shifts to CM. Therefore, even if there is a period when the screen is not displayed for a moment due to the self-detection process, the user does not feel uncomfortable.
　本実施形態に係る表示部９０は、表示パネル８０と、表示パネル８０に画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切り替えながら表示パネル８０を駆動する駆動回路であって、表示パネル８０との電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する液晶駆動用半導体集積回路１０とを備え、上記自己検出・自己修復手段は、上記供給停止期間に、液晶駆動用半導体集積回路１０の不良を検出する処理を実行する。 The display unit 90 according to the present embodiment includes the display panel 80, a supply period in which an image signal is supplied, and a supply in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel 80. Self-detection / self-repair means for detecting and repairing a defect in the drive circuit that drives the display panel 80 while switching the stop period and is disconnected from the display panel 80. The self-detecting / self-repairing means executes processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period.
　上記の構成によれば、液晶駆動用半導体集積回路１０は、表示パネル８０に画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切替ながら、表示パネル８０を駆動する。そして、液晶駆動用半導体集積回路１０は、液晶駆動用半導体集積回路１０自身の不良を検出可能であり、検出した不良を修復する自己検出・自己修復手段とを有している。液晶駆動用半導体集積回路１０は、自身の不良を検出し修復する処理を、表示パネル８０との電気的な接続を切り離した状態で実行する。つまり、液晶駆動用半導体集積回路１０は、表示パネル８０との電気的接続を切り離して自身の不良を検出する（すなわち自己検出する）ことで、表示パネル８０に表示中の画像を表す階調データだけでなく、全ての階調データを用いて自己検出の処理を実行することができる。なお、画像は、静止画像であってもよいし、動画像すなわち映像であってもよい。 According to the above configuration, the liquid crystal driving semiconductor integrated circuit 10 stops the supply period in which the image signal is supplied and the supply of the image signal in the period in which the image is displayed on the display panel 80. The display panel 80 is driven while switching the supply stop period. The liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect. The liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected. In other words, the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80. In addition, the self-detection process can be executed using all the gradation data. The image may be a still image or a moving image, that is, a video.
　そして、上記の構成によれば、自己検出・自己修復手段は、供給停止期間に、液晶駆動用半導体集積回路１０の不良を検出する処理を実行する。例えば、自己検出・自己修復手段は、水平走査期間や垂直走査期間において、液晶駆動用半導体集積回路１０の不良を検出する処理を実行する。 Then, according to the above configuration, the self-detecting / self-repairing means executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period. For example, the self-detecting / self-repairing unit executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in the horizontal scanning period and the vertical scanning period.
　これにより、本実施形態に係る表示部９０によれば、表示部９０の駆動において、表示に影響のない期間に、自己検出の処理を実行することができる。つまり、本実施形態に係る表示部９０は、表示パネル８０との電気的な接続を切り離した状態で液晶駆動用半導体集積回路１０の不良を検出する処理を実行するが、画像を表示中の表示パネル８０に画像信号の供給が行われないタイミングで、自己検出の処理を実行するため、表示パネル８０の駆動を妨げない。したがって、本実施形態に係る表示部９０によれば、ユーザの視聴を妨げずに適切なタイミングにおいて、自己検出および自己修復の処理を実行することが可能となり、ユーザにとっての利便性を向上させることができる。 Thereby, according to the display unit 90 according to the present embodiment, in the driving of the display unit 90, the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected, but the display while displaying an image. Since the self-detection process is executed at the timing when the image signal is not supplied to the panel 80, the display panel 80 is not hindered. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
　本実施形態に係る表示部９０では、上記処理は、１つ以上の工程を含む複数の工程群に分割され、上記自己検出・自己修復手段は、１回の上記供給停止期間ごとに上記工程群を１つずつ実行することが好ましい。 In the display unit 90 according to the present embodiment, the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair means performs the process group for each supply stop period. Are preferably performed one by one.
　上記の構成によれば、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理には、複数の工程が含まれ、それらの工程は複数の工程群に分割される。そして、自己検出・自己修復手段は、１回の供給停止期間ごとに、上記工程群を１つずつ実行する。例えば、工程群の数がｎの場合、ｎ回の供給停止期間で、自己検出処理に含まれる全ての工程を完了させることができる。 According to the above configuration, the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10, that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups. The self-detecting / self-repairing means executes the above process group one by one for each supply stop period. For example, when the number of process groups is n, all processes included in the self-detection process can be completed in n supply stop periods.
　これにより、自己検出処理に含まれる工程の数が多く、全ての自己検出処理が完了するまでに長時間を要する場合であっても、１回の供給停止期間内に各工程群の処理を収めることができるため、ユーザの視聴を妨げることなく、適切なタイミングにおいて自己検出および自己修復の処理を実行することが可能となる。 As a result, even if the number of processes included in the self-detection process is large and it takes a long time to complete all the self-detection processes, the processes of each process group are accommodated within one supply stop period. Therefore, it is possible to execute the self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing.
　本実施形態に係る表示部９０では、上記処理は、複数の工程を含んでおり、上記自己検出・自己修復手段は、１回の上記供給停止期間で上記処理に含まれる全ての工程を実行することが好ましい。 In the display unit 90 according to the present embodiment, the process includes a plurality of processes, and the self-detecting / self-repairing unit executes all processes included in the process in one supply stop period. It is preferable.
　上記の構成によれば、液晶駆動用半導体集積回路１０の不良を検出する処理、すなわち、自己検出処理には、複数の工程が含まれるが、自己検出・自己修復手段は、１回の供給停止期間において、自己検出処理に含まれる全ての工程を実行する。 According to the above configuration, the process for detecting a defect in the semiconductor integrated circuit 10 for driving the liquid crystal, that is, the self-detection process includes a plurality of steps. In the period, all the steps included in the self-detection process are executed.
　これにより、液晶駆動用半導体集積回路１０の自己検出および自己修復の処理を、短時間で完了させることが可能となる。 Thereby, the self-detection and self-repair processing of the liquid crystal driving semiconductor integrated circuit 10 can be completed in a short time.
　本実施形態に係る表示部９０では、表示パネル８０に画像を表示している期間において、上記供給期間から、上記供給停止期間としての水平ブランキング期間への切替を検知するコントローラ１００をさらに備え、上記自己検出・自己修復手段は、コントローラ１００によって上記切替が検知されたとき、上記処理を開始することが好ましい。 The display unit 90 according to the present embodiment further includes a controller 100 that detects switching from the supply period to the horizontal blanking period as the supply stop period in a period during which an image is displayed on the display panel 80, The self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
　上記の構成によれば、コントローラ１００は、表示パネル８０に画像を表示している期間において、水平ブランキング期間を検知する。そして、自己検出・自己修復手段は、水平ブランキング期間において、自己検出処理を実行する。水平ブランキング期間においては、画像は表示されているが、画像信号は表示パネル８０に供給されておらず、表示パネル８０は駆動されない。 According to the above configuration, the controller 100 detects the horizontal blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the horizontal blanking period. In the horizontal blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
　これにより、画像信号を表示パネル８０に供給していない水平ブランキング期間において、自己検出の処理を実行することが可能となる、したがって、自己検出の処理によって画面表示に影響を与えることがなく、ユーザに違和感を感じさせることがない。 Thereby, it is possible to execute the self-detection process in the horizontal blanking period in which the image signal is not supplied to the display panel 80. Therefore, the self-detection process does not affect the screen display. The user does not feel uncomfortable.
　本実施形態に係る表示部９０では、表示パネル８０に画像を表示している期間において、上記供給期間から、上記供給停止期間としての垂直ブランキング期間への切替を検知するコントローラ１００をさらに備え、上記自己検出・自己修復手段は、コントローラ１００によって上記切替が検知されたとき、上記処理を開始することが好ましい。 The display unit 90 according to the present embodiment further includes a controller 100 that detects switching from the supply period to the vertical blanking period as the supply stop period in a period during which an image is displayed on the display panel 80, The self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
　上記の構成によれば、コントローラ１００は、表示パネル８０に画像を表示している期間において、垂直ブランキング期間を検知する。そして、自己検出・自己修復手段は、垂直ブランキング期間において、自己検出処理を実行する。垂直ブランキング期間においては、画像は表示されているが、画像信号は表示パネル８０に供給されておらず、表示パネル８０は駆動されない。 According to the above configuration, the controller 100 detects the vertical blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the vertical blanking period. In the vertical blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
　これにより、画像信号を表示パネル８０に供給していない垂直ブランキング期間において、自己検出の処理を実行することが可能となる、したがって、自己検出の処理によって画面表示に影響を与えることがなく、ユーザに違和感を感じさせることがない。 Accordingly, it is possible to execute the self-detection process in the vertical blanking period in which the image signal is not supplied to the display panel 80. Therefore, the self-detection process does not affect the screen display. The user does not feel uncomfortable.
　本実施形態に係る表示部９０では、液晶駆動用半導体集積回路１０は、表示パネル８０を駆動するための出力信号を出力する出力回路ブロック３０を備え、上記自己検出・自己修復手段は、出力回路ブロック３０が不良か否かを判定する比較判定回路５０を備え、比較判定回路５０の判定結果が不良であった場合に、表示パネル８０に正常な出力信号を出力するように、液晶駆動用半導体集積回路１０を自己修復することが好ましい。 In the display unit 90 according to the present embodiment, the liquid crystal driving semiconductor integrated circuit 10 includes an output circuit block 30 that outputs an output signal for driving the display panel 80, and the self-detection / self-repair means includes an output circuit. A comparison / determination circuit 50 for determining whether or not the block 30 is defective is provided. When the determination result of the comparison / determination circuit 50 is defective, a liquid crystal driving semiconductor is output so as to output a normal output signal to the display panel 80. The integrated circuit 10 is preferably self-healing.
　上記の構成によれば、液晶駆動用半導体集積回路１０は、表示パネル８０を駆動するための出力信号を出力する出力回路ブロック３０を備えている。出力回路ブロック３０は、例えば映像データを階調電圧に変換して表示パネル８０を駆動する出力信号として出力する。 According to the above configuration, the liquid crystal driving semiconductor integrated circuit 10 includes the output circuit block 30 that outputs an output signal for driving the display panel 80. The output circuit block 30 converts, for example, video data into a gradation voltage and outputs it as an output signal for driving the display panel 80.
　また、上記の構成によれば、自己検出・自己修復手段は、出力回路ブロック３０が不良であるか否かを判定する比較判定回路５０を備えており、比較判定回路５０における判定結果が不良であった場合、表示パネル８０に正常な出力信号を出力するように、液晶駆動用半導体集積回路１０を自己修復する。 Further, according to the above configuration, the self-detection / self-repair means includes the comparison determination circuit 50 that determines whether or not the output circuit block 30 is defective, and the determination result in the comparison determination circuit 50 is defective. If so, the liquid crystal driving semiconductor integrated circuit 10 is self-repaired so as to output a normal output signal to the display panel 80.
　これにより、本実施形態に係る表示部９０では、液晶駆動用半導体集積回路１０の出力回路ブロック３０における欠陥を検出することができ、出力回路ブロック３０に欠陥があった場合に自己修復できる。 Thereby, in the display unit 90 according to the present embodiment, a defect in the output circuit block 30 of the liquid crystal driving semiconductor integrated circuit 10 can be detected, and self-repair can be performed when the output circuit block 30 is defective.
　本実施形態に係る表示部９０では、液晶駆動用半導体集積回路１０は、表示パネル８０に上記出力信号を出力可能な予備出力回路ブロック４０を備え、上記自己検出・自己修復手段は、比較判定回路５０の判定結果が不良である場合、表示パネル８０への出力信号として、上記不良となった出力回路ブロック３０からの出力信号を、予備出力回路ブロック４０からの出力信号に切り替える切替回路６０を、備えていることが好ましい。 In the display unit 90 according to the present embodiment, the liquid crystal driving semiconductor integrated circuit 10 includes a spare output circuit block 40 that can output the output signal to the display panel 80, and the self-detection / self-repair means is a comparison / determination circuit. When the determination result of 50 is defective, a switching circuit 60 that switches the output signal from the defective output circuit block 30 to the output signal from the standby output circuit block 40 as an output signal to the display panel 80, It is preferable to provide.
　上記の構成によれば、上記駆動回路は、表示パネル８０に出力信号を出力可能な予備出力回路ブロック４０を備えている。予備出力回路ブロック４０は、出力回路ブロック３０と同様、例えば映像データを階調電圧に変換して表示パネル８０を駆動する出力信号として出力することができる。 According to the above configuration, the drive circuit includes the spare output circuit block 40 that can output an output signal to the display panel 80. Similar to the output circuit block 30, the preliminary output circuit block 40 can convert, for example, video data into a gradation voltage and output it as an output signal for driving the display panel 80.
　また、上記の構成によれば、自己検出・自己修復手段は、比較判定回路５０において不良と判定された出力回路ブロック３０を、予備出力回路ブロック４０に切り替える切替回路６０を備えている。 Further, according to the above configuration, the self-detection / self-repair means includes the switching circuit 60 that switches the output circuit block 30 determined to be defective in the comparison determination circuit 50 to the spare output circuit block 40.
　これにより、本実施形態に係る表示部９０では、出力回路ブロック３０に欠陥があった場合、欠陥のある出力回路ブロック３０を予備出力回路ブロック４０に切り替えることにより、液晶駆動用半導体集積回路１０の自己修復を容易に行うことができる。 Thereby, in the display unit 90 according to the present embodiment, when the output circuit block 30 is defective, the defective output circuit block 30 is switched to the spare output circuit block 40, whereby the liquid crystal driving semiconductor integrated circuit 10 is replaced. Self-healing can be easily performed.
　本実施形態に係る表示部９０では、比較判定回路５０は、出力回路ブロック３０からの出力信号と、予備出力回路ブロック４０からの出力信号とを比較するオペアンプ１－１，１－２，１－nを備え、オペアンプ１－１，１－２，１－nの比較結果に基づき、出力回路ブロック３０が不良か否かを判定することが好ましい。 In the display unit 90 according to the present embodiment, the comparison determination circuit 50 compares the output signal from the output circuit block 30 with the output signal from the auxiliary output circuit block 40, as operational amplifiers 1-1, 1-2, 1-. It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
　上記の構成によれば、比較判定回路５０は、オペアンプ１－１，１－２，１－nを備えている。また、オペアンプ１－１，１－２，１－nは、出力回路ブロック３０からの出力信号と、予備出力回路ブロック４０からの出力信号とを比較する。そして、比較判定回路５０は、オペアンプ１－１，１－２，１－nの比較結果に基づいて、出力回路ブロック３０が不良か否かを判定する。 According to the above configuration, the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n. The operational amplifiers 1-1, 1-2, and 1-n compare the output signal from the output circuit block 30 with the output signal from the spare output circuit block 40. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
　これにより、本実施形態に係る表示部９０では、出力回路ブロック３０の出力と予備出力回路ブロック４０の出力とを比較することで出力回路ブロック３０の不良を判定できるため、簡素な構成にて、容易に出力回路ブロック３０の不良を検出することができる。 Thereby, in the display unit 90 according to the present embodiment, a defect in the output circuit block 30 can be determined by comparing the output of the output circuit block 30 and the output of the standby output circuit block 40. A defect in the output circuit block 30 can be easily detected.
　本実施形態に係る表示部９０では、出力回路ブロック３０および予備出力回路ブロック４０に入力する入力信号を制御する制御手段をさらに備え、上記制御手段は、出力回路ブロック３０と予備出力回路ブロック４０とに、異なる大きさの入力信号を入力するとともに、上記異なる大きさの入力信号に対応する、オペアンプ１－１，１－２，１－nからの比較結果の期待値を出力し、比較判定回路５０は、上記比較結果と上記期待値とが異なる場合に、出力回路ブロック３０を不良と判定することが好ましい。 The display unit 90 according to the present embodiment further includes control means for controlling input signals input to the output circuit block 30 and the spare output circuit block 40, and the control means includes the output circuit block 30, the spare output circuit block 40, and the like. In addition, an input signal of a different magnitude is input, and an expected value of a comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signal of the different magnitude is output, and a comparison determination circuit 50, it is preferable to determine that the output circuit block 30 is defective when the comparison result is different from the expected value.
　上記の構成によれば、制御手段は、出力回路ブロック３０と予備出力回路ブロック４０に入力する入力信号を制御し、異なる大きさの入力信号を入力する。また、制御手段は、異なる大きさの入力信号に対応する、オペアンプ１－１，１－２，１－nからの比較結果の期待値を出力する。そして、比較判定回路５０は、オペアンプ１－１，１－２，１－nからの実際の比較結果と制御手段からの期待値とが異なる場合、出力回路ブロック３０を不良と判定する。 According to the above configuration, the control means controls the input signals input to the output circuit block 30 and the spare output circuit block 40 and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes. The comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
　具体的には、例えば、出力回路ブロック３０に階調ｍの入力信号を入力し、予備出力回路ブロック４０に階調ｍ＋１の入力信号を入力する。なお、階調ｍの階調電圧は、階調ｍ＋１の階調電圧よりも低い電圧である。ここで、出力回路ブロック３０が正常であれば、オペアンプ１－１，１－２，１－nは、予備出力回路ブロック４０から入力した階調電圧の方が高いことを示す信号を出力する。一方、出力回路ブロック３０に欠陥があり、階調ｍの信号を入力しても、出力回路ブロック３０は高い階調電圧しか出力できない場合、オペアンプ１－１，１－２，１－nは、出力回路ブロック３０より入力した階調電圧の方が高いことを示す信号を出力する。 Specifically, for example, an input signal of gradation m is input to the output circuit block 30, and an input signal of gradation m + 1 is input to the standby output circuit block 40. Note that the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1. Here, if the output circuit block 30 is normal, the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the spare output circuit block 40 is higher. On the other hand, when the output circuit block 30 is defective and the output circuit block 30 can output only a high gradation voltage even if a signal of gradation m is input, the operational amplifiers 1-1, 1-2, and 1-n A signal indicating that the input gradation voltage is higher than that of the output circuit block 30 is output.
　このように、本実施形態の液晶駆動用半導体集積回路１０では、オペアンプ１－１，１－２，１－nは、出力回路ブロック３０および予備出力回路ブロック４０より出力される階調電圧を比較し、出力回路ブロック３０に欠陥がある場合とない場合とにおいて、異なる値の信号を出力する。 Thus, in the liquid crystal driving semiconductor integrated circuit 10 of the present embodiment, the operational amplifiers 1-1, 1-2, and 1-n compare the grayscale voltages output from the output circuit block 30 and the spare output circuit block 40. Then, different values of signals are output depending on whether the output circuit block 30 is defective or not.
　次に、比較判定回路５０は、オペアンプ１－１，１－２，１－nより出力された信号より、出力回路ブロック３０が不良か否かを判定する。具体的には、上述したような、出力回路ブロック３０に階調ｍの入力信号を入力し、予備出力回路ブロック４０に階調ｍ＋１の入力信号を入力した場合に、出力回路ブロック３０からの階調電圧が高いことを示す信号を、オペアンプ１－１，１－２，１－nより入力したときは、出力回路ブロック３０は不良であると判定する。一方、予備出力回路ブロック４０からの階調電圧が高いことを示す信号を、オペアンプ１－１，１－２，１－nより入力した場合は、比較判定回路５０は、出力回路ブロック３０は不良でないと判定する。 Next, the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when the input signal of gradation m is input to the output circuit block 30 and the input signal of gradation m + 1 is input to the standby output circuit block 40 as described above, the level from the output circuit block 30 is increased. When a signal indicating that the regulated voltage is high is input from the operational amplifiers 1-1, 1-2, and 1-n, the output circuit block 30 is determined to be defective. On the other hand, when a signal indicating that the grayscale voltage from the standby output circuit block 40 is high is input from the operational amplifiers 1-1, 1-2, and 1-n, the comparison / determination circuit 50 determines that the output circuit block 30 is defective. It is determined that it is not.
　これにより、本実施形態に係る表示部９０では、容易に出力回路ブロック３０の欠陥を検出する具体的な手段を備え、出力回路ブロック３０に欠陥があった場合に自己修復できる。 Thereby, the display unit 90 according to the present embodiment includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
　本実施形態に係る表示部９０では、比較判定回路５０は、出力回路ブロック３０のうち、少なくとも２つの出力回路からの出力信号を比較するオペアンプ１－１，１－２，１－nを備え、オペアンプ１－１，１－２，１－nの比較結果に基づき、出力回路ブロック３０が不良か否かを判定することが好ましい。 In the display unit 90 according to the present embodiment, the comparison determination circuit 50 includes operational amplifiers 1-1, 1-2, and 1-n that compare output signals from at least two output circuits in the output circuit block 30; It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison results of the operational amplifiers 1-1, 1-2, and 1-n.
　上記の構成によれば、比較判定回路５０は、オペアンプ１－１，１－２，１－nを備えている。また、オペアンプ１－１，１－２，１－nは、出力回路ブロック３０のうち、少なくとも２つの出力回路からの出力信号を比較する。そして、比較判定回路５０は、オペアンプ１－１，１－２，１－nの比較結果に基づいて、出力回路ブロック３０が不良か否かを判定する。 According to the above configuration, the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n. The operational amplifiers 1-1, 1-2, and 1-n compare output signals from at least two output circuits in the output circuit block 30. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
　これにより、本実施形態に係る表示部９０では、出力回路ブロック３０の出力を比較することで出力回路ブロック３０の不良を判定できるため、簡素な構成にて、容易に出力回路ブロック３０の不良を検出することができる。 As a result, the display unit 90 according to the present embodiment can determine the failure of the output circuit block 30 by comparing the output of the output circuit block 30. Therefore, the failure of the output circuit block 30 can be easily detected with a simple configuration. Can be detected.
　本実施形態に係る表示部９０では、出力回路ブロック３０のうち、少なくとも２つの出力回路に入力する入力信号を制御する制御手段をさらに備え、上記制御手段は、上記少なくとも２つの出力回路に、異なる大きさの入力信号を入力するとともに、上記異なる大きさの入力信号に対応する、オペアンプ１－１，１－２，１－nからの比較結果の期待値を出力し、比較判定回路５０は、上記比較結果と上記期待値とが異なる場合に、上記少なくとも２つの出力回路のいずれかが不良であると判定することが好ましい。 The display unit 90 according to the present embodiment further includes control means for controlling input signals to be input to at least two output circuits in the output circuit block 30, and the control means is different from the at least two output circuits. The input signal of the magnitude is input, and the expected value of the comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signals of the different magnitudes is output. When the comparison result and the expected value are different, it is preferable to determine that one of the at least two output circuits is defective.
　上記の構成によれば、制御手段は、出力回路ブロック３０のうち、少なくとも２つの出力回路に入力する入力信号を制御し、異なる大きさの入力信号を入力する。また、制御手段は、異なる大きさの入力信号に対応する、オペアンプ１－１，１－２，１－nからの比較結果の期待値を出力する。そして、比較判定回路５０は、オペアンプ１－１，１－２，１－nからの実際の比較結果と制御手段からの期待値とが異なる場合、出力回路ブロック３０を不良と判定する。 According to the above configuration, the control means controls the input signals input to at least two output circuits in the output circuit block 30, and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes. The comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
　具体的には、例えば、第１の出力回路と第２の出力回路との２つの出力回路に異なる入力信号を入力する場合、第１の出力回路に階調ｍの入力信号を入力し、第２の出力回路に階調ｍ＋１の入力信号を入力する。なお、階調ｍの階調電圧は、階調ｍ＋１の階調電圧よりも低い電圧である。ここで、第１の出力回路が正常であれば、オペアンプ１－１，１－２，１－nは、第２の出力回路から入力した階調電圧の方が高いことを示す信号を出力する。一方、第１の出力回路に欠陥があり、階調ｍの信号を入力しても、第１の出力回路は高い階調電圧しか出力できない場合、オペアンプ１－１，１－２，１－nは、第１の出力回路より入力した階調電圧の方が高いことを示す信号を出力する。 Specifically, for example, when different input signals are input to the two output circuits of the first output circuit and the second output circuit, the input signal of gradation m is input to the first output circuit, The input signal of gradation m + 1 is input to the output circuit 2. Note that the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1. Here, if the first output circuit is normal, the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the second output circuit is higher. . On the other hand, when the first output circuit is defective and the first output circuit can output only a high gradation voltage even when a signal of gradation m is input, the operational amplifiers 1-1, 1-2, 1-n Outputs a signal indicating that the gradation voltage input from the first output circuit is higher.
　このように、本実施形態の液晶駆動用半導体集積回路１０では、オペアンプ１－１，１－２，１－nは、出力回路ブロック３０のうち、少なくとも２つの出力回路より出力される階調電圧を比較し、出力回路ブロック３０に欠陥がある場合とない場合とにおいて、異なる値の信号を出力する。 As described above, in the liquid crystal driving semiconductor integrated circuit 10 of the present embodiment, the operational amplifiers 1-1, 1-2, and 1-n have the grayscale voltages output from at least two output circuits in the output circuit block 30. And output signals having different values depending on whether the output circuit block 30 is defective or not.
　次に、比較判定回路５０は、オペアンプ１－１，１－２，１－nより出力された信号より、出力回路ブロック３０が不良か否かを判定する。具体的には、上述したような、第１の出力回路と第２の出力回路との２つの出力回路に異なる入力信号を入力する場合、第１の出力回路に階調ｍの入力信号を入力し、第２の出力回路に階調ｍ＋１の入力信号を入力した場合に、第１の出力回路からの階調電圧が高いことを示す信号を、オペアンプ１－１，１－２，１－nより入力したときは、比較判定回路５０は、第１の出力回路と第２の出力回路との少なくともいずれかの出力回路は不良であると判定する。このとき、第１の出力回路と第２の出力回路は、予備の出力回路に切り替えられる。一方、第２の出力回路からの階調電圧が高いことを示す信号を、オペアンプ１－１，１－２，１－nより入力した場合は、比較判定回路５０は、出力回路ブロック３０は不良でないと判定する。 Next, the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when different input signals are input to the two output circuits of the first output circuit and the second output circuit as described above, the input signal of the gradation m is input to the first output circuit. When an input signal of gradation m + 1 is input to the second output circuit, a signal indicating that the gradation voltage from the first output circuit is high is supplied to the operational amplifiers 1-1, 1-2, 1-n. When more inputs are made, the comparison / determination circuit 50 determines that at least one of the first output circuit and the second output circuit is defective. At this time, the first output circuit and the second output circuit are switched to a spare output circuit. On the other hand, when a signal indicating that the grayscale voltage from the second output circuit is high is input from the operational amplifiers 1-1, 1-2, and 1-n, the comparison determination circuit 50 causes the output circuit block 30 to be defective. It is determined that it is not.
　これにより、本実施形態に係る表示部９０では、容易に出力回路ブロック３０の欠陥を検出する具体的な手段を備え、出力回路ブロック３０に欠陥があった場合に自己修復できる。 Thereby, the display unit 90 according to the present embodiment includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
　本実施形態に係る表示部９０では、出力回路ブロック３０は、出力バッファーとしてオペアンプ２１を備え、オペアンプ１－１，１－２，１－nは、オペアンプ２１を含んで構成されるコンパレーターであることが好ましい。 In the display unit 90 according to the present embodiment, the output circuit block 30 includes an operational amplifier 21 as an output buffer, and the operational amplifiers 1-1, 1-2, and 1-n are comparators including the operational amplifier 21. It is preferable.
　上記の構成によれば、出力回路ブロック３０は、出力バッファーとしてオペアンプ２１を備えている。また、オペアンプ１－１，１－２，１－nは、オペアンプ２１によって構成されるコンパレーターである。 According to the above configuration, the output circuit block 30 includes the operational amplifier 21 as an output buffer. The operational amplifiers 1-1, 1-2, and 1-n are comparators configured by the operational amplifier 21.
　一般的に、表示パネル８０を駆動する出力回路ブロック３０からの出力信号は、バッファリングされて出力端子に出力される。ここで、オペアンプ２１は、自身の出力を、自身の負極性入力端子に負帰還させることにより、ボルテージフォロワ回路となり、バッファ回路としての機能を有することになる。 Generally, an output signal from the output circuit block 30 that drives the display panel 80 is buffered and output to an output terminal. Here, the operational amplifier 21 provides a voltage follower circuit by negatively feeding back its output to its negative input terminal, and has a function as a buffer circuit.
　したがって、上記のように、オペアンプ１－１，１－２，１－nをオペアンプ２１を含んで構成されるコンパレーターとすることにより、オペアンプ２１が、出力回路ブロック３０からの出力信号をバッファリングするバッファ回路とオペアンプ１－１，１－２，１－nとの両方の役割を兼ね備えることになる。よって、本実施形態の液晶駆動用半導体集積回路１０は、出力回路ブロック３０からの出力信号をバッファリングするためのバッファ回路を別途備える必要がなく、コストを低減する効果を奏する。 Therefore, as described above, by using the operational amplifiers 1-1, 1-2, and 1-n as the comparators including the operational amplifier 21, the operational amplifier 21 buffers the output signal from the output circuit block 30. Thus, both the buffer circuit and the operational amplifiers 1-1, 1-2, and 1-n are combined. Therefore, the liquid crystal driving semiconductor integrated circuit 10 according to the present embodiment does not require a separate buffer circuit for buffering the output signal from the output circuit block 30, and has the effect of reducing costs.
　本実施形態に係る表示部９０では、オペアンプ２１は、表示パネル８０を駆動する場合、ボルテージフォロワとして動作することが好ましい。 In the display unit 90 according to the present embodiment, the operational amplifier 21 preferably operates as a voltage follower when the display panel 80 is driven.
　さらに、本実施形態に係るテレビジョンシステム３００は、表示部９０を備えている構成であってもよい。 Furthermore, the television system 300 according to the present embodiment may be configured to include the display unit 90.
　本発明は、出力回路の欠陥の検出および自己修復の具体的な手段を備え、より容易に出力回路の不具合に対処可能な表示駆動用集積回路を備えた表示装置を提供するものであり、特に、適切なタイミングにて自己検出および自己修復を行うことができる液晶表示装置に好適である。 The present invention provides a display device including a display drive integrated circuit that includes specific means for detecting a defect in the output circuit and self-repairing, and that can more easily cope with the malfunction of the output circuit. It is suitable for a liquid crystal display device that can perform self-detection and self-repair at an appropriate timing.
　１－１　オペアンプ（比較手段）
　１－２　オペアンプ（比較手段）
　１－ｎ　オペアンプ（比較手段）
　２ｃ　　スイッチ（接続切替手段）
　２ｄ　　スイッチ（接続切替手段）
　３－１　判定回路（判定手段）
　３－２　判定回路（判定手段）
　３－ｎ　判定回路（判定手段）
　４－１　判定フラグ（フラグ格納手段）
　４－２　判定フラグ（フラグ格納手段）
　４－ｎ　判定フラグ（フラグ格納手段）
　８－１　ＤＡＣ回路（出力回路）
　８－２　ＤＡＣ回路（出力回路）
　８－ｎ　ＤＡＣ回路（出力回路）
　１０　　液晶駆動用半導体集積回路（駆動回路）
　１０’　液晶駆動用半導体集積回路（駆動回路）
　１０ａ　液晶駆動用半導体集積回路（駆動回路、ソースドライバ）
　１０ｂ　液晶駆動用半導体集積回路（駆動回路、ソースドライバ）
　２０　　液晶駆動用半導体集積回路（駆動回路）
　２１　　オペアンプ（比較手段）
　２１Ａ　オペアンプ（比較手段）
　２１Ｂ　オペアンプ（比較手段）
　２８　　ＤＡＣ回路（予備出力回路）
　２８Ａ　ＤＡＣ回路（予備出力回路）
　２８Ｂ　ＤＡＣ回路（予備出力回路）
　５０　　比較判定回路（自己検出・自己修復手段、判定手段）
　６０　　切替回路（自己検出・自己修復手段、切替手段）
　６１　　切替回路（自己検出・自己修復手段）
　８０　　表示パネル
　８０’　表示パネル
　８１　　メモリ（記憶装置）
　８２　　動作切換入力端子
　８３　　フィルム基材
　８４　　入力端子
　８５　　ソルダーレジスト
　８６　　出力側配線
　８７　　デバイスホール
　８８　　入力側配線
　８９　　テープキャリア
　９０　　表示部（表示装置）
　９２　　画素
　９３　　ＴＦＴ
　９４　　ゲート線
　９５　　ソース線
　９６　　ガラス基板
　９７　　プリント基板（ＰＷＤ）
　９８　　フィルムケーブル（ＦＰＣ）
　９９　　ゲートドライバ
　１００　コントローラ（画像切替手段、期間切替検知手段）
　２０２　抵抗（検出手段）
　２０４　Ａ／Ｄコンバータ（検出手段）
　２０６　ＥＥＰＲＯＭ（正常電流値記憶手段）
　２０８　比較回路（電流値比較手段、駆動回路判定手段）
　３００　テレビジョンシステム
　４００　液晶テレビジョン
　４０１　リモコンＩ／Ｆ（選局受付手段）
　４０２　リモコン 1-1 Operational amplifier (comparison means)
1-2 Operational amplifier (comparison means)
1-n operational amplifier (comparison means)
2c switch (connection switching means)
2d switch (connection switching means)
3-1 Determination circuit (determination means)
3-2 Determination circuit (determination means)
3-n determination circuit (determination means)
4-1 Determination flag (flag storage means)
4-2 Judgment flag (flag storage means)
4-n determination flag (flag storage means)
8-1 DAC circuit (output circuit)
8-2 DAC circuit (output circuit)
8-n DAC circuit (output circuit)
10 Liquid crystal drive semiconductor integrated circuit (drive circuit)
10 'Liquid crystal driving semiconductor integrated circuit (driving circuit)
10a Semiconductor integrated circuit for driving liquid crystal (drive circuit, source driver)
10b Semiconductor integrated circuit for driving liquid crystal (drive circuit, source driver)
20 Semiconductor integrated circuit for driving liquid crystal (drive circuit)
21 Operational amplifier (comparison means)
21A operational amplifier (comparison means)
21B operational amplifier (comparison means)
28 DAC circuit (spare output circuit)
28A DAC circuit (spare output circuit)
28B DAC circuit (spare output circuit)
50 Comparison judgment circuit (self-detection / self-repair means, judgment means)
60 switching circuit (self-detection / self-repair means, switching means)
61 Switching circuit (self-detection / self-repair means)
80 display panel 80 'display panel 81 memory (storage device)
82 Operation switching input terminal 83 Film substrate 84 Input terminal 85 Solder resist 86 Output side wiring 87 Device hole 88 Input side wiring 89 Tape carrier 90 Display unit (display device)
92 pixels 93 TFT
94 Gate line 95 Source line 96 Glass substrate 97 Printed circuit board (PWD)
98 Film cable (FPC)
99 Gate driver 100 Controller (image switching means, period switching detection means)
202 Resistance (detection means)
204 A / D converter (detection means)
206 EEPROM (normal current value storage means)
208 comparison circuit (current value comparison means, drive circuit determination means)
300 Television system 400 Liquid crystal television 401 Remote control I / F (channel selection reception means)
402 remote control

Claims (19)

  1. 　表示パネルと、
    　上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、
    　上記自己検出・自己修復手段は、上記表示パネルに表示すべき画像が不連続に切り替わるときに、上記駆動回路の不良を検出する処理を実行することを特徴とする表示装置。     A display panel;
    A drive circuit for driving the display panel, comprising a drive circuit having self-detection / self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected. ,
    The display device according to claim 1, wherein the self-detection / self-repair means executes a process of detecting a defect in the drive circuit when an image to be displayed on the display panel is switched discontinuously.
  2. 　上記処理は、１つ以上の工程を含む複数の工程群に分割され、
    　上記自己検出・自己修復手段は、上記表示パネルにおける上記表示が１回中断するごとに、上記工程群を１つずつ実行することを特徴とする請求項１に記載の表示装置。     The process is divided into a plurality of process groups including one or more processes,
    The display device according to claim 1, wherein the self-detecting / self-repairing unit executes the process group one by one every time the display on the display panel is interrupted once.
  3. 　上記処理は、複数の工程を含んでおり、
    　上記自己検出・自己修復手段は、上記表示パネルにおける上記表示が１回中断したときに、上記処理に含まれる全ての工程を実行することを特徴とする請求項１に記載の表示装置。     The above process includes a plurality of steps,
    The display device according to claim 1, wherein the self-detecting / self-repairing unit executes all the steps included in the processing when the display on the display panel is interrupted once.
  4. 　ユーザによる選局操作を受け付ける選局受付手段と、
    　選局受付手段が受け付けた選局操作に対応する放送を受信し、該放送の画像信号を上記表示パネルに供給する放送受信手段と、
    　上記放送受信手段が受信する放送を切り替える際に、上記表示パネルに表示すべき画像が不連続に切り替わることを検知する画像切替手段とをさらに備え、
    　上記自己検出・自己修復手段は、画像切替手段によって上記表示パネルに表示すべき画像の切替が検知されたときに、上記駆動回路の不良を検出する処理を開始することを特徴とする請求項１に記載の表示装置。     Channel selection receiving means for receiving a channel selection operation by a user;
    Broadcast receiving means for receiving a broadcast corresponding to the channel selection operation received by the channel selection receiving means, and supplying an image signal of the broadcast to the display panel;
    An image switching means for detecting that the image to be displayed on the display panel is discontinuously switched when switching the broadcast received by the broadcast receiving means;
    2. The self-detecting / self-repairing unit starts processing for detecting a defect in the driving circuit when switching of an image to be displayed on the display panel is detected by the image switching unit. The display device described in 1.
  5. 　放送を受信し、該放送の画像信号を上記表示パネルに供給する放送受信手段と、
    　上記放送受信手段が受信する放送の内容が番組からＣＭ（Commercial Message）に切り替わる際に、上記表示パネルに表示すべき画像が不連続に切り替わることを検知する画像切替手段とをさらに備え、
    　上記自己検出・自己修復手段は、画像切替手段によって上記表示パネルに表示すべき画像の切替が検知されたときに、上記駆動回路の不良を検出する処理を実行することを特徴とする請求項１に記載の表示装置。     Broadcast receiving means for receiving a broadcast and supplying an image signal of the broadcast to the display panel;
    An image switching means for detecting that the image to be displayed on the display panel is switched discontinuously when the broadcast content received by the broadcast receiving means is switched from a program to a CM (Commercial Message);
    2. The self-detecting / self-repairing unit executes a process of detecting a defect of the driving circuit when switching of an image to be displayed on the display panel is detected by the image switching unit. The display device described in 1.
  6. 　表示パネルと、
    　上記表示パネルに画像を表示している期間のうち、画像信号を供給している供給期間と、画像信号の供給を停止している供給停止期間とを切り替えながら上記表示パネルを駆動する駆動回路であって、上記表示パネルとの電気的な接続を切り離した状態で当該駆動回路の不良を検出し、修復する自己検出・自己修復手段を有する駆動回路とを備え、
    　上記自己検出・自己修復手段は、上記供給停止期間に、上記駆動回路の不良を検出する処理を実行することを特徴とする表示装置。     A display panel;
    A drive circuit that drives the display panel while switching between a supply period in which an image signal is supplied and a supply stop period in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel. A drive circuit having self-detection and self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected,
    The display device according to claim 1, wherein the self-detection / self-repair means performs a process of detecting a defect of the drive circuit during the supply stop period.
  7. 　上記処理は、１つ以上の工程を含む複数の工程群に分割され、
    　上記自己検出・自己修復手段は、１回の上記供給停止期間ごとに上記工程群を１つずつ実行することを特徴とする請求項６に記載の表示装置。     The process is divided into a plurality of process groups including one or more processes,
    The display device according to claim 6, wherein the self-detecting / self-repairing unit executes the process group one by one for each supply stop period.
  8. 　上記処理は、複数の工程を含んでおり、
    　上記自己検出・自己修復手段は、１回の上記供給停止期間で上記処理に含まれる全ての工程を実行することを特徴とする請求項６に記載の表示装置。     The above process includes a plurality of steps,
    The display device according to claim 6, wherein the self-detecting / self-repairing unit executes all the steps included in the processing in one supply stop period.
  9. 　上記表示パネルに画像を表示している期間において、上記供給期間から、上記供給停止期間としての水平ブランキング期間への切替を検知する期間切替検知手段をさらに備え、
    　上記自己検出・自己修復手段は、上記期間切替検知手段によって上記切替が検知されたとき、上記処理を開始すること特徴とする請求項６に記載の表示装置。     In the period during which an image is displayed on the display panel, it further comprises period switching detection means for detecting switching from the supply period to a horizontal blanking period as the supply stop period,
    The display device according to claim 6, wherein the self-detection / self-repair unit starts the process when the switching is detected by the period switching detection unit.
  10. 　上記表示パネルに画像を表示している期間において、上記供給期間から、上記供給停止期間としての垂直ブランキング期間への切替を検知する期間切替検知手段をさらに備え、
    　上記自己検出・自己修復手段は、上記期間切替検知手段によって上記切替が検知されたとき、上記処理を開始すること特徴とする請求項８に記載の表示装置。     In the period during which an image is displayed on the display panel, it further comprises period switching detection means for detecting switching from the supply period to the vertical blanking period as the supply stop period,
    9. The display device according to claim 8, wherein the self-detecting / self-repairing unit starts the processing when the switching is detected by the period switching detecting unit.
  11. 　上記駆動回路は、
    　上記表示パネルを駆動するための出力信号を出力する複数の出力回路を備え、
    　上記自己検出・自己修復手段は、
    　上記出力回路が不良か否かを判定する判定手段を備え、上記判定手段の判定結果が不良であった場合に、上記表示パネルに正常な出力信号を出力するように、当該駆動回路を自己修復することを特徴とする請求項１に記載の表示装置。     The drive circuit is
    A plurality of output circuits for outputting an output signal for driving the display panel;
    The self-detection / self-repair means is
    A determination unit configured to determine whether or not the output circuit is defective; and when the determination result of the determination unit is defective, the drive circuit is self-repaired so that a normal output signal is output to the display panel. The display device according to claim 1.
  12. 　上記駆動回路は、
    　上記表示パネルに上記出力信号を出力可能な予備出力回路を備え、
    　上記自己検出・自己修復手段は、
    　上記判定手段の判定結果が不良である場合、上記表示パネルへの出力信号として、上記不良となった出力回路からの出力信号を、上記予備出力回路からの出力信号に切り替える切替手段を、備えていることを特徴とする請求項１１に記載の表示装置。     The drive circuit is
    A preliminary output circuit capable of outputting the output signal to the display panel;
    The self-detection / self-repair means is
    When the determination result of the determination means is defective, a switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal to the display panel is provided. The display device according to claim 11, wherein the display device is a display device.
  13. 　上記判定手段は、
    　上記出力回路からの出力信号と、上記予備出力回路からの出力信号とを比較する比較手段を備え、上記比較手段の比較結果に基づき、上記出力回路が不良か否かを判定することを特徴とする請求項１２に記載の表示装置。     The determination means is
    Comparing means for comparing an output signal from the output circuit and an output signal from the auxiliary output circuit, and determining whether or not the output circuit is defective based on a comparison result of the comparing means The display device according to claim 12.
  14. 　上記出力回路および上記予備出力回路に入力する入力信号を制御する制御手段をさらに備え、
    　上記制御手段は、上記出力回路と上記予備出力回路とに、異なる大きさの入力信号を入力するとともに、上記異なる大きさの入力信号に対応する、上記比較手段からの比較結果の期待値を出力し、
    　上記判定手段は、上記比較結果と上記期待値とが異なる場合に、上記出力回路を不良と判定することを特徴とする、請求項１３に記載の駆動回路。     Control means for controlling input signals to be input to the output circuit and the spare output circuit,
    The control means inputs an input signal having a different magnitude to the output circuit and the standby output circuit, and outputs an expected value of the comparison result from the comparison means corresponding to the input signal having a different magnitude. And
    The drive circuit according to claim 13, wherein the determination means determines that the output circuit is defective when the comparison result and the expected value are different.
  15. 　上記判定手段は、上記複数の出力回路のうち、少なくとも２つの出力回路からの出力信号を比較する比較手段を備え、上記比較手段の比較結果に基づき、上記出力回路が不良か否かを判定することを特徴とする請求項１２に記載の表示装置。 The determination means includes comparison means for comparing output signals from at least two output circuits among the plurality of output circuits, and determines whether or not the output circuit is defective based on a comparison result of the comparison means. The display device according to claim 12.
  16. 　上記複数の出力回路のうち、少なくとも２つの出力回路に入力する入力信号を制御する制御手段をさらに備え、
    　上記制御手段は、上記少なくとも２つの出力回路に、異なる大きさの入力信号を入力するとともに、上記異なる大きさの入力信号に対応する、上記比較手段からの比較結果の期待値を出力し、
    　上記判定手段は、上記比較結果と上記期待値とが異なる場合に、上記少なくとも２つの出力回路のいずれかが不良であると判定することを特徴とする、請求項１５に記載の駆動回路。     Control means for controlling an input signal input to at least two output circuits among the plurality of output circuits,
    The control means inputs an input signal of a different magnitude to the at least two output circuits, and outputs an expected value of the comparison result from the comparison means corresponding to the input signal of the different magnitude,
    The drive circuit according to claim 15, wherein the determination means determines that one of the at least two output circuits is defective when the comparison result and the expected value are different.
  17. 　上記出力回路は、出力バッファーとしてオペアンプを備え、
    　上記比較手段は、上記オペアンプを含んで構成されるコンパレーターであることを特徴とする請求項１３に記載の表示装置。     The output circuit includes an operational amplifier as an output buffer,
    The display device according to claim 13, wherein the comparison unit is a comparator configured to include the operational amplifier.
  18. 　上記オペアンプは、表示パネルを駆動する場合、ボルテージフォロワとして動作することを特徴とする請求項１７に記載の表示装置。 18. The display device according to claim 17, wherein the operational amplifier operates as a voltage follower when driving the display panel.
  19. 　請求項１に記載の表示装置を備えていることを特徴とするテレビジョンシステム。 A television system comprising the display device according to claim 1.
PCT/JP2009/069697 2008-11-20 2009-11-20 Display device and television system WO2010058836A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-296965 2008-11-20
JP2008296965A JP2010122513A (en) 2008-11-20 2008-11-20 Display device and television system

Publications (1)

Publication Number Publication Date
WO2010058836A1 true WO2010058836A1 (en) 2010-05-27

Family

ID=42198275

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/069697 WO2010058836A1 (en) 2008-11-20 2009-11-20 Display device and television system

Country Status (3)

Country Link
JP (1) JP2010122513A (en)
TW (1) TW201037680A (en)
WO (1) WO2010058836A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600378B2 (en) 2016-03-01 2020-03-24 Rohm Co., Ltd. Liquid crystal driving device
JP6706954B2 (en) 2016-04-01 2020-06-10 三菱電機株式会社 Driver IC and liquid crystal display device
JP6804066B2 (en) * 2016-10-26 2020-12-23 シャープＮｅｃディスプレイソリューションズ株式会社 Video signal output device, display system and video signal output method
JP7132010B2 (en) * 2018-07-23 2022-09-06 ローム株式会社 Abnormality detection circuit
JP7040368B2 (en) * 2018-09-06 2022-03-23 株式会社デンソー Anomaly detection device for liquid crystal display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10339861A (en) * 1997-03-15 1998-12-22 Sharp Corp Fault tolerant architecture
JP2002043943A (en) * 2000-07-21 2002-02-08 Toshiba Corp Analog output device
JP2008139861A (en) * 2006-11-10 2008-06-19 Toshiba Matsushita Display Technology Co Ltd Active matrix display device using organic light-emitting element and method of driving same using organic light-emitting element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10339861A (en) * 1997-03-15 1998-12-22 Sharp Corp Fault tolerant architecture
JP2002043943A (en) * 2000-07-21 2002-02-08 Toshiba Corp Analog output device
JP2008139861A (en) * 2006-11-10 2008-06-19 Toshiba Matsushita Display Technology Co Ltd Active matrix display device using organic light-emitting element and method of driving same using organic light-emitting element

Also Published As

Publication number Publication date
JP2010122513A (en) 2010-06-03
TW201037680A (en) 2010-10-16

Similar Documents

Publication Publication Date Title
JP4277055B2 (en) Drive circuit, display device, and television system
WO2010035797A1 (en) Display apparatus and television system
JP6653593B2 (en) Display device and display device inspection method
WO2010061839A1 (en) Drive circuit, display device and method for self-detecting and self-repairing drive circuit
WO2010058836A1 (en) Display device and television system
CN105761704A (en) Display panel and driving circuit and driving method thereof
JP2002032053A (en) Data driver and display device using the same
WO2010035792A1 (en) Display device and television system
WO2010035785A1 (en) Display apparatus and television system
WO2008047495A1 (en) Display device
JPH1130772A (en) Liquid crystal display device
JP2006153927A (en) Display apparatus
WO2010035801A1 (en) Display apparatus and television system
US20090243981A1 (en) Driving module of display device and method for extending lifetime of the driving module
US9953599B2 (en) Display device and driving board
JP5015038B2 (en) DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE DRIVE CIRCUIT
JP5015037B2 (en) DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE DRIVE CIRCUIT
JPH07199872A (en) Liquid crystal display device
JP5015041B2 (en) DRIVE CIRCUIT AND DISPLAY DEVICE PROVIDED WITH DRIVE CIRCUIT
JPH06281944A (en) Redundancy driving matrix display device that can be recovered
JP2002196743A (en) Display device, abnormal operation preventing circuit and method therefor
JPH07199876A (en) Shift register, active matrix system tft-lcd and method of driving drive circuit
JP3230393B2 (en) Inspection method of liquid crystal panel
JPH06214210A (en) Matrix display device
JP2002287714A (en) Liquid crystal display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09827617

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09827617

Country of ref document: EP

Kind code of ref document: A1