201023700 九、發明說明： 【發明所屬之技術領域】 本發明係㈣包埋式電容n之製作 容器包埋在電路板内的製作方法。 兀，、疋將電 【先前技術】 。所謂“埋入式被動元件”，係利用多層板之内層板製 私’採仃_或_方式，將電容料電㈣直接製作在 内層板上，再經壓合成多層板後可取代掉板面上組裝時所 2接的零散祕元件，以節省板面給—元件及其佈線 者。 埋入式、植入式或藏入式技術最早是〇hmega物公 =是於内層板面原有銅箱毛面上形成—磷鎳合金薄膜層 當成電組成份而壓合成為薄膜核心（Thin c〇re)，然後再 利用兩次光阻與三次蝕刻的技術於特定位置上形成電阻 器。由於是埋人在内層中，故稱之為埋人式電阻(BuHed ❹201023700 IX. Description of the Invention: [Technical Field of the Invention] The present invention is a method for fabricating a buried capacitor in a circuit board.兀, 疋 will be electricity [prior art]. The so-called "buried passive components" are made by using the inner layer of the multi-layer board to make a private ' picking _ or _ way, the capacitor material (4) is directly made on the inner layer board, and then the laminated board can be replaced by pressing the laminated board. The loose components that are connected to the upper assembly to save the board surface to the components and their routers. Buried, implantable or hidden technology is the first 〇hmega object = formed on the original copper surface of the inner layer of the plate - the phosphorous-nickel alloy film layer is formed into an electrical component and pressed into a film core (Thin C〇re), and then use two photoresist and three etching techniques to form resistors at specific locations. Because it is buried in the inner layer, it is called buried electric resistance (BuHed ❹
Resister ， BR)。 • 一般電容結構中，電源極、介電層以及接地極是依序 隹且的，並且為了提高電容量除了採用高介電質的介電 層、大面積的電源極以及接地極之外，就是讓電源極以及 接地極盡可能的接近。 參閱第一圖至第五圖’習用技術之埋入式電容器製作 方法的示意圖。首先’於具有薄銅層4的基板2上形成具 圖案化的光阻層6，以曝露出部分的薄銅層4，如第一圖 所示。然後’在曝露的薄銅層4上電锻出梳形極板i〇a， 201023700 如第一圖所示。梳形極板10a包含正極16與負極18，而 正極16具有正極端12以及複數個正極分支17，負極18 具有負極端14以及複數個負極分支19，如第三圖所示。 接著，去除掉光阻層6，並以電容膏15填充梳形極板他 内正極16與負極18之間的空隙，形成電容器1〇，如第四 圖所示。一般將該電容器1〇稱作平面梳型電容器。然後， 將電容器10與具有第一金屬層3〇的第 2 行壓合，使電容器1〇埋入第-介電膠膜2〇内，再膜去= ❹ 鋪4與基板2，軸埋人式平面獅電容n之結構，如 第五圖所示。 習用技術之埋人式電容器的缺點為，電容器的正極與 負極=有部分曝露出來，使得電容器的電氣特性易受外在 應用環境響，比如在高濕度下，會降低電容器的可承受電 壓值’甚至損壞電容器而失效。 因此，需要一種製造電容器的方法，以製造出具更小 間距且更不受外在應用環境影響且具隔絕功能的電ς 、 ❿ 器’以解決習用技術的所有缺點。 【發明内容】 本發明之主要目的在提供一種包埋式電容器之製造 方法，將具有電容器與第一介電膠膜的埋入式電容器^ 用第一介電膠膜以壓合方式包埋該電容器，並在第一介a 膠膜與第二介電夥膜上分別形成具電路圖案的第 •電 金屬層與第二導電金屬層，且在第—導電金屬層與第^ 電金屬層上分別形成第一絕緣膠層與第二絕緣膠/層，^ 6 201023700 電容器的正極端與負極端分別藉正極導通接線與負極導 „連_第二導電金屬層’因此形成包埋式電容 盗’藉以提高電容騎電驗性，並進—步縮小電容器的 面積’降低製造成本。 因此，本發明提供能製造出具更小間距且更不受外在 應用環境影響且具隔絕魏之電容器的方法，可解決 技術的所有缺點。 、 【實施方式】 ;以下配合圖式及元件符號對本發明之實施方式做更 詳細的說明’俾使熟習該項技藝者在研讀本制書後能據 以實施。 參閱第六至第九圖’本發明之包埋式電容器之製作 方法示意圖。首先’將具有第二金屬層31的第二介電勝 膜22壓合到具有第一金屬層3〇與電容器1〇的第一介電 膠膜2U ’吨埋住電容n 1G，如第六圖所示。 接著，以雷射鑽孔或機械鑽孔方式，貫穿第一金屬 層30、第-介電膠膜2〇、第二介電膠膜22與第二金屬 層31以形成貫穿孔32。同時貫穿第二介電膠膜22與第 二金屬層31，以形成接觸到正極端12的正極導通孔（圖 中未顯示,)以及接觸到負極端14的負極導通孔（圖中未顯 示）。接著’於貝穿孔32、正極導通孔以及負極導通孔内 填充導電金屬。因此，貫穿孔32電氣連接第—金屬層3〇 與第二金屬層3卜而正極導通孔以及負極導通孔分別形 成正極導通接線11以及負極導通接線13,並且正極導通 201023700 接線11電氣連接正極端12與第二金屬層31，負極導通 接線13電氣連接負極端14與第二金屬層31。然後，將 形成於第一介電膠膜2〇上的第一金屬層30圖案化形成 第一電路圖案以及將第二金屬層31圖案化形成第二電路 圖案，如第七圖所示。Resister, BR). • In a general capacitor structure, the power supply, dielectric, and grounding electrodes are sequentially connected, and in order to increase the capacitance, in addition to a high dielectric dielectric layer, a large-area power supply, and a grounding electrode, Keep the power and ground terminals as close as possible. Referring to the first to fifth figures, a schematic diagram of a method of fabricating a buried capacitor of the prior art. First, a patterned photoresist layer 6 is formed on the substrate 2 having the thin copper layer 4 to expose a portion of the thin copper layer 4 as shown in the first figure. Then, the comb-shaped plate i〇a is electrically forged on the exposed thin copper layer 4, 201023700 as shown in the first figure. The comb-shaped plate 10a includes a positive electrode 16 and a negative electrode 18, and the positive electrode 16 has a positive electrode terminal 12 and a plurality of positive electrode branches 17, and the negative electrode 18 has a negative electrode terminal 14 and a plurality of negative electrode branches 19, as shown in the third figure. Next, the photoresist layer 6 is removed, and the gap between the positive electrode 16 and the negative electrode 18 of the comb-shaped plate is filled with a capacitor paste 15 to form a capacitor 1 〇 as shown in the fourth figure. This capacitor 1 is generally referred to as a planar comb capacitor. Then, the capacitor 10 is pressed together with the second row having the first metal layer 3〇, so that the capacitor 1〇 is buried in the first dielectric film 2〇, and then the film is removed = ❹ 4 and the substrate 2, and the shaft is buried The structure of the flat lion capacitor n is shown in the fifth figure. The disadvantage of the buried capacitor of the conventional technology is that the positive and negative electrodes of the capacitor are partially exposed, so that the electrical characteristics of the capacitor are susceptible to external application environment, such as reducing the withstand voltage of the capacitor under high humidity. It even fails to damage the capacitor. Accordingly, there is a need for a method of fabricating a capacitor to produce an electrical enthalpy, a device having a smaller pitch and less quarantined by an external application environment to address all of the disadvantages of conventional techniques. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing an embedded capacitor, in which a buried capacitor having a capacitor and a first dielectric film is embedded in a press-fit manner by a first dielectric film. a capacitor, and forming a circuit pattern of the first and second conductive metal layers on the first dielectric film and the second dielectric film, respectively, and on the first conductive metal layer and the second metal layer Forming a first insulating adhesive layer and a second insulating adhesive/layer respectively, ^ 6 201023700 The positive and negative terminals of the capacitor are respectively connected by the positive conducting wiring and the negative conducting lead to the second conductive metal layer to form an embedded capacitive thief In order to improve the electrical riding performance of the capacitor and further reduce the area of the capacitor 'reducing the manufacturing cost. Therefore, the present invention provides a method for manufacturing a capacitor having a smaller pitch and being less affected by an external application environment and having a shield. Solving all the shortcomings of the technology. [Embodiment] The following is a more detailed description of the embodiments of the present invention with the drawings and the components and symbols, so that the skilled person is studying the book. After the book is made, it can be implemented according to the sixth to ninth drawings. The schematic diagram of the manufacturing method of the embedded capacitor of the present invention. First, the second dielectric film 22 having the second metal layer 31 is pressed to have the first A metal layer 3〇 and a first dielectric film 2U' of the capacitor 1 埋 bury the capacitor n 1G as shown in the sixth figure. Next, through the first metal layer by laser drilling or mechanical drilling 30. The first dielectric film 2, the second dielectric film 22 and the second metal layer 31 are formed to form the through hole 32. The second dielectric film 22 and the second metal layer 31 are penetrated to form a contact. The positive electrode via hole of the positive terminal 12 (not shown) and the negative electrode via hole (not shown) that contacts the negative electrode terminal 14. Then, the conductive metal is filled in the bead through hole 32, the positive electrode via hole, and the negative electrode via hole. Therefore, the through hole 32 electrically connects the first metal layer 3 and the second metal layer 3, and the positive and negative conductive vias respectively form the positive conductive connection 11 and the negative conductive connection 13, and the positive conduction 201023700 is electrically connected to the positive terminal. 12 and second metal layer 31, negative electrode The through wire 13 electrically connects the negative electrode terminal 14 and the second metal layer 31. Then, the first metal layer 30 formed on the first dielectric film 2 is patterned to form a first circuit pattern and the second metal layer 31 is patterned. The second circuit pattern is formed as shown in the seventh figure.
最後，在第一金屬層30上形成第一絕緣膠層4〇， 並在第二金屬層31底下形成第二絕緣膠層42，且第—絕 緣層40與第二絕緣層42分別具有複數個第一開口 41以 及複數個第二開口 43，如第八圖所示。在第一開口 41 以及第二開口 43内，分別形成第三金屬層5〇以及第四 金屬層52,如第九圖所示。第三金屬層5〇與第四金屬層 用以方便焊接其它的電子元件，比如電阻、電感、 電谷、一極體、電晶體、開關或積體電路。 要注意的是，在本發明之包埋式電容器的製作方法 中，電容H可為平面梳型電容器，如第三圖所示，在此 不再贅述。此外’本發财法的主要優點係可是採用一 般的印刷電路板製程崎行埋入式電容的製造，可有效 降低生產成本並提高產品的可靠度。 人以上所述者僅為用以解釋本發明之較佳實施例，並非 ^據以對本伽餘何形式上之_，是以，凡有在相 明ϊ神下所作有關本發明之任何修飾或變更，應包 在本發明意圖保護之範嘴。 【圖式簡單說明】 器製作方法的 第-圖至第五圖為習用技術之埋入式電容 8 201023700 示意圖。 第六圖至第九圖為本發明之包埋式電容器製作方法的示 意圖。 【主要元件符號說明】 2基板 4薄銅層 6光阻層 10電容器 ® IGa梳形極板 11正極導通接線 13負極導通接線 12正極端 14負極端 15電容膏 16正極 17正極分支 ❹ 18負極 19負極分支 20第一介電膠膜 22第二介電膠層 30第一導電金屬層 31第二導電金屬層 32貫穿孔 40第一絕緣膠層 9 201023700 41第一開口 42第二絕緣膠層 43第二開口 50第三導電金屬層 52第四導電金屬層Finally, a first insulating adhesive layer 4 is formed on the first metal layer 30, and a second insulating adhesive layer 42 is formed under the second metal layer 31, and the first insulating layer 40 and the second insulating layer 42 respectively have a plurality of The first opening 41 and the plurality of second openings 43 are as shown in the eighth figure. In the first opening 41 and the second opening 43, a third metal layer 5A and a fourth metal layer 52 are formed, respectively, as shown in the ninth. The third metal layer 5〇 and the fourth metal layer are used to facilitate soldering of other electronic components such as resistors, inductors, valleys, transistors, transistors, switches or integrated circuits. It should be noted that in the method of fabricating the embedded capacitor of the present invention, the capacitor H may be a planar comb capacitor as shown in the third figure, and will not be described herein. In addition, the main advantage of this method is that it uses a general printed circuit board process to manufacture embedded capacitors, which can effectively reduce production costs and improve product reliability. The above description is only for the purpose of explaining the preferred embodiments of the present invention, and is not intended to be in any form of the present invention. The changes should be included in the scope of the invention intended to be protected. [Simple diagram of the diagram] The first to fifth diagrams of the method of making the device are schematic diagrams of the buried capacitor 8 of the conventional technology. 6 to 9 are views showing a method of fabricating a buried capacitor of the present invention. [Main component symbol description] 2 substrate 4 thin copper layer 6 photoresist layer 10 capacitor® IGa comb plate 11 positive conduction wiring 13 negative conduction wiring 12 positive terminal 14 negative terminal 15 capacitance paste 16 positive electrode 17 positive branch ❹ 18 negative electrode 19 Negative electrode branch 20 first dielectric film 22 second dielectric layer 30 first conductive metal layer 31 second conductive metal layer 32 through hole 40 first insulating layer 9 201023700 41 first opening 42 second insulating layer 43 Second opening 50 third conductive metal layer 52 fourth conductive metal layer