200931456 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種嵌埋電容元件之封裝基板結構及其 製法，尤指一種易於製作、厚度薄之嵌埋電容元件之封裝 5 基板結構及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入具有 ® 多功能、高性能之發展趨勢。為滿足半導體封裝件高積集 1〇 度（integration)及微型化（miniaturization)的封裝需求，以供 更多主被動元件及線路載接，半導體封裝基板亦逐漸由雙 層演變成多層（multi-layer)，俾在有限的空間下運用層間連 接技術（interlayer connection)以擴大半導體封裝基板上可 供利用的線路佈局面積，藉此配合高線路密度之積體電路 15 (integrated circuit)需要，降低封裝基板的厚度，以在相同 基板單位體積中容納更多數量的線路及電子元件。然而， 〇 半導體裝置積集化之同時，封裝構造之接腳數目亦隨著增 加，常由於接腳數目與線路佈設之增多，導致雜訊亦隨之 增大。因此，通常於半導體封裝結構中增加被動元件，如 20 電阻元件、電容材料與電感元件，以消除雜訊或作電性補 償與穩定電路，藉此使得所封裝之半導體晶片能符合所需 之電性特性。 為符合半導體封裝件輕薄短小之發展趨勢，在習知方 法中，係利用表面黏著技術（Surface Mount Technology ; 200931456 SMT) ’將該多數被動元件整合至基板表面上，如此則限制 了電容與線路佈局空間的靈活性’亦不利於封裝體積的縮 小。 基於上述問題，近來有許多研究係利用壓合的方式， 5 將咼介電材料壓合於銅層間並製作線路以形成電容元件。 如圖1所不，係為一習知利用壓合方式形成電容元件的結構 剖視圖。其主要提供一内層電路板10，其係具有一内層線 路層11 ,其包括下電極板lu<) 一高介電材料層12係形成於 Ο 該内層線路層11上，接著再於該高介電材料層12表面形成 10 一外層線路層13，其包括上電極板131，因此藉由該上、下 電極板131，1U及夾於其中之部份該高介電材料層12而作為 一電容元件17。再經由一導電通孔14而導通該内層線路層 11及該外層線路層13。接著，再繼續進行後續的製程以形 成一防焊層15,該防焊層15係具有複數開孔151而顯露出部 15刀之該外層線路層13以作為一連接墊132。 六二而此種方法有數點缺失。一為該高介電材料於非 © '、區白屬材料之浪費，不利於降低成本；其二，此種全 面I·生而介電常數材料，由於非電容區域與線路相接觸，易 20於線路，或上下層線路產生寄生電容之漏電問題。其三， 化装ΐ间介電材料厚度往往小於30 μιη，且無玻璃纖維以強 办厂構’於該尚介電材料層兩表面分別形成線路層後， 2因其兩表面無銅箱支撐而碎裂；最後，由於該結構中 板與線路係佈局在同—層線路，對兩者皆造成佈局空 6 200931456 5 ❹ 10 15 ❹ 20 間的限制，不利於電容與線路佈局的靈活性。故前述問題 實為現今業界所急須解決的課題。【發明内容】 鑑於上述缺點，本發明提供一種嵌埋電容元件之封裝 基板，其包括一核心板、一電容元件、以及一增層結構。 上述核心板係具有一貫穿核心板之開口，以及具有一設於 核心板相對兩表面之第—線路層。上述電容元件係設於核 心板之開口中。該電容元件包含一高介電材料層，同時包 3 S 又於雨介電材料層之相對兩表面之外線路層。在該電 合2中，外線路層具有至少一對以高介電材料層間隔且互 相平行對應之外電極板。上述增層結構係設於核心板之至 少一表面及同側電容元件之表面。該增層結構具有至少一 "電層、至少一疊置於介電層表面之第二線路層、及設於 介電層中之複數導電盲孔。部份上述導電盲孔係電性連接第一線路層與第二線路層，並且至少一導電盲孔電性連接 外線路層與第二線路層。 上述之封裝基板更可包括至少一貫穿電容元件之導電 盲孔，且該導電盲孔係電性連接電容元件相對兩表面之外線路層。 或者，上述之封裝基板可包括至少一貫穿電容元件及 增層結構之導電通孔，該導電通孔係電性連接電容元件相 對兩表面之外線路層，並且電性連接外線路層與第二線路 層。 7 200931456 另外，上述之封裝基板亦可再包括一防焊層覆蓋該增 層結構，且該防焊層具有複數開孔而可以顯露部份第二線 路層作為複數電性連接塾。 在上述嵌埋電容元件之封裝基板中，電容元件可復包 5 Ο 10 15 ❾ 括至少一内線路層嵌埋於高介電材料層内，且每一内線路 層與外線路層係以高介電材料層間隔。在該電容元件中， 内線路層係具有至少一内電極板，該内電極板係平行對應 於成對之外電極板。另外，電容元件也可更包含至少一貫 穿高介電材料層之導電通孔，該導電通孔係電性連接外線 路層及内線路層。 本發明另提供一種嵌埋電容元件之封裝基板，其包括 -核心板、-電容元件、以及一增層結構。上述核心板係 具有设於核心板相對兩表面之第一線路層。上述電容元件 係設於核心板至少一表面之部份區域，並且其包含一高介 電材料層及一設於高介電材料層之相對兩表面之外 層》在該電容元件中，外線路層具有至少一對以高介電材 料層間隔且互相平行對應之外電極板'上述增層結構係設 於核心板之至少一表面及同侧電容元件之表面。該增層結 構具有至少-介電層、至少—疊置於介電層表面之第二線 路層、及設於介電層中之複數導電盲孔。在該增層結構中， 部份導電盲孔係電性連接第—線路層與第二線路層，並且 至少-導電盲孔係電性連接外線路層與第二線路層。 20 200931456 200931456 5 ❹ 10 15200931456 IX. Description of the Invention: [Technical Field] The present invention relates to a package substrate structure embedded in a capacitor element and a method of fabricating the same, and more particularly to a package 5 substrate structure of an embedded capacitor element which is easy to fabricate and has a small thickness and System of law. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the trend of having a versatile, high-performance product. In order to meet the high-integration integration and miniaturization of semiconductor packages, for more active and passive components and lines, semiconductor package substrates have gradually evolved from double layers to multiple layers (multi- Layer), using a layer connection in a limited space to expand the available circuit layout area on the semiconductor package substrate, thereby cooperating with a high line density integrated circuit 15 (integrated circuit) needs, reducing the package The thickness of the substrate is such that a greater number of lines and electronic components are accommodated in the same substrate unit volume. However, while the semiconductor device is integrated, the number of pins in the package structure increases, and the number of pins and the number of lines are often increased, resulting in an increase in noise. Therefore, passive components, such as 20 resistive components, capacitive materials and inductive components, are usually added to the semiconductor package structure to eliminate noise or electrical compensation and stabilization circuits, thereby enabling the packaged semiconductor wafer to meet the required power. Sexual characteristics. In order to meet the trend of thinness and thinness of semiconductor packages, in the conventional method, the surface adhesive technology (Surface Mount Technology; 200931456 SMT) is used to integrate most of the passive components onto the substrate surface, thus limiting the capacitance and circuit layout. The flexibility of space is also not conducive to the shrinking of the package size. Based on the above problems, many recent studies have used a press-fit method to bond a tantalum dielectric material between copper layers and make a line to form a capacitor element. As shown in Fig. 1, it is a cross-sectional view showing a structure in which a capacitor element is formed by a press-fit method. It mainly provides an inner layer circuit board 10 having an inner layer circuit layer 11 including a lower electrode plate lu<) a high dielectric material layer 12 formed on the inner layer circuit layer 11, and then the high dielectric layer The surface of the layer 12 of electrical material 12 is formed as an outer layer 13 and includes an upper electrode plate 131. Therefore, the upper and lower electrode plates 131, 1U and a portion of the high dielectric material layer 12 sandwiched therebetween serve as a capacitor. Element 17. The inner wiring layer 11 and the outer wiring layer 13 are electrically connected via a conductive via 14. Next, the subsequent process is continued to form a solder resist layer 15 having a plurality of openings 151 to expose the outer wiring layer 13 of the portion 15 as a connection pad 132. Sixty-two and this method has several missing points. One is the waste of the high dielectric material in the non-©, and the white material, which is not conducive to reducing the cost; secondly, the comprehensive I·sheng and dielectric constant material, because the non-capacitive area is in contact with the line, the easy 20 The leakage of parasitic capacitance occurs on the line, or on the upper and lower lines. Third, the thickness of the dielectric material of the cosmetic intercontracting layer is often less than 30 μm, and no glass fiber is used to strengthen the factory structure. After the two layers on the surface of the dielectric material layer respectively form a circuit layer, 2 because the two surfaces are not supported by the copper box. Fragmentation; Finally, due to the layout of the board and the line system in the same-layer line, the layout of the two is limited by the layout, which is not conducive to the flexibility of capacitance and line layout. Therefore, the above problems are indeed urgent issues to be solved in the industry today. SUMMARY OF THE INVENTION In view of the above disadvantages, the present invention provides a package substrate embedded with a capacitor element, which comprises a core board, a capacitor element, and a build-up structure. The core board has an opening through the core board and a first circuit layer disposed on opposite sides of the core board. The capacitive element is disposed in the opening of the core plate. The capacitive element comprises a layer of high dielectric material while covering the circuit layer outside the opposite surfaces of the layer of rain dielectric material. In the electric junction 2, the outer wiring layer has at least one pair of outer electrode plates spaced apart by a layer of high dielectric material and corresponding to each other in parallel. The build-up structure is disposed on at least one surface of the core board and the surface of the same side capacitive element. The build-up structure has at least one electrical layer, at least one second wiring layer stacked on the surface of the dielectric layer, and a plurality of conductive blind vias disposed in the dielectric layer. A plurality of the conductive blind vias are electrically connected to the first circuit layer and the second circuit layer, and the at least one conductive blind via is electrically connected to the outer circuit layer and the second circuit layer. The package substrate may further include at least one conductive via hole penetrating the capacitor element, and the conductive via hole is electrically connected to the circuit layer outside the two surfaces. Alternatively, the package substrate may include at least one conductive via extending through the capacitor element and the build-up structure, the conductive via being electrically connected to the circuit layer outside the two surfaces, and electrically connecting the outer circuit layer and the second layer Line layer. 7 200931456 In addition, the package substrate may further include a solder mask covering the build-up structure, and the solder resist layer has a plurality of openings to expose a portion of the second trace layer as a plurality of electrical connections. In the package substrate with the embedded capacitor element, the capacitor element may be packaged with 5 Ο 10 15 至少 at least one inner circuit layer is embedded in the high dielectric material layer, and each inner circuit layer and outer circuit layer are high. Dielectric material layer spacing. In the capacitive element, the inner wiring layer has at least one inner electrode plate which corresponds in parallel to the pair of outer electrode plates. In addition, the capacitive element may further comprise a conductive via extending at least through the high dielectric material layer, the conductive via being electrically connected to the outer wiring layer and the inner wiring layer. The invention further provides a package substrate embedded with a capacitive element, comprising: a core plate, a capacitor element, and a build-up structure. The core board has a first circuit layer disposed on opposite sides of the core board. The capacitor element is disposed on a portion of at least one surface of the core board, and includes a layer of high dielectric material and a layer disposed on opposite surfaces of the layer of high dielectric material. In the capacitor element, the outer circuit layer Having at least one pair of high dielectric material layers spaced apart from each other and corresponding to the outer electrode plate 'the above-mentioned buildup structure is disposed on at least one surface of the core plate and the surface of the same side capacitive element. The build-up structure has at least a dielectric layer, at least a second trace layer overlying the surface of the dielectric layer, and a plurality of conductive vias disposed in the dielectric layer. In the build-up structure, a portion of the conductive vias are electrically connected to the first circuit layer and the second circuit layer, and at least the conductive blind holes are electrically connected to the outer circuit layer and the second circuit layer. 20 200931456 200931456 5 ❹ 10 15
上述嵌埋電容元件之封裝基板更可包括至少一貫穿電 容7G件之導電盲孔，該導電盲孔係電性連接電容元件相對 兩表面之外線路層。 示此之外上述嵌埋電容元件之封裝基板也可再包括 至少-貫穿電容元件、核心板及增層結構之導電通孔，該 導電通孔係、電)生連接電容元件相對兩表面之外線路層，以 及電性連接外線路層與第二線路層。 另外，上述嵌埋電容元件之封裝基板亦可再包括—防 焊層覆蓋增層結構，且該防焊層具有複數開孔以顯露部份 第二線路層作為複數電性連接墊。 ，本發月上述嵌埋電容元件之封裝基板亦可使用下述方 法製成，但不限於此，舉例如下。 本發明亦提供一種嵌埋電容元件封裝基板之製法，其 提供；^心板，其中，核心板係具有一貫穿之開口 及又於核、板相對兩表面之第一線路層丨設置一電容元件 4π板5開口中’其中’電容元件包含-高介電材料層 及'^於円介電材料層之相對兩表面之外線路層，且外線 路層具有至少__對以高介電材料層間隔且互相平行對應之 卜電極板，以及形成—增層結構於核心板之至少一表面及 同側電谷7L件之表面’其中，增層結構具有至少一介電層、 至少-叠置於介電層表面之第二線路層、及設於介電層中 之複數導電盲孔。 20 200931456 上述嵌埋電容元件封裝基板之製法更可包括形成一防 焊層覆蓋增層結構，且該防焊層具有複數開孔而可以顯露 部伤第二線路層作為複數電性連接墊。 5The package substrate with the embedded capacitor element further includes at least one conductive via hole penetrating through the capacitor 7G, and the conductive via hole is electrically connected to the circuit layer outside the two surfaces. The package substrate of the embedded capacitor element may further include at least a conductive via hole penetrating through the capacitor element, the core board and the build-up structure, and the conductive via hole is electrically connected to the capacitor element opposite to the two surfaces. a circuit layer, and electrically connecting the outer circuit layer and the second circuit layer. In addition, the package substrate embedded with the capacitor element may further include a solder resist layer covering the buildup structure, and the solder resist layer has a plurality of openings to expose a portion of the second circuit layer as a plurality of electrical connection pads. The package substrate of the embedded capacitor element described above may be formed by the following method, but is not limited thereto, and is exemplified as follows. The invention also provides a method for fabricating a buried capacitor device package substrate, which provides a core plate, wherein the core plate has a through hole and a first circuit layer on the opposite surfaces of the core and the plate, and a capacitor element is disposed. In the 4π-plate 5 opening, the 'where' capacitive element comprises a layer of high dielectric material and a layer other than the opposite surfaces of the layer of dielectric material, and the outer layer has at least __ pairs of layers of high dielectric material The electrode plates are spaced apart and parallel to each other, and the surface-forming structure is formed on at least one surface of the core plate and the surface of the same-side electric valley 7L. The build-up structure has at least one dielectric layer, at least-overlapped a second circuit layer on the surface of the dielectric layer and a plurality of conductive blind holes disposed in the dielectric layer. 20 200931456 The method for fabricating the embedded capacitor component package substrate further includes forming a solder resist layer covering buildup structure, and the solder resist layer has a plurality of openings to expose the second circuit layer as a plurality of electrical connection pads. 5
1010
除此之外，上述嵌埋電容元件封裝基板之製法亦可再 已括形成至少一貫穿電容元件及增層結構之導電通孔，該 導電通孔係電性連接電容元件相對兩表面之外線路層，以 及電性連接外線路層與第二線路層。 在上述嵌埋電容元件封裝基板之製法中，電容元件也 可再包含有至少一貫穿電容元件之導電結構，該導電結構 係電ϋ連接N介電材料層相對兩表面之外線路層，且該導 電結構係為導電盲孔、導電通孔、或上述兩者之組合。此 外’電容元件亦可更包含有至少—内線路層嵌埋於高介電 材料層m内線路層與外線路層係以高介電材料層 間隔。該内線路層具有至少一内電極板，該内電極板係平 行對應於一成對之該些外電極板。 勺本發明亦提供一種嵌埋電容元件封裝基板之製法，其 。含：提供一核心板’纟中’核心板係具有設於相對兩表 :之第一線路層；設置-電容元件於核心板至少-表面之 雜區域，其中，電容元件包含—高介電材料層及一設於 :介電材料層之相對兩表面之外線路層且外線路層具有 ’十以网介電材料層間隔且互相平行對應之外電極 以及形成—增層結構於電容元件之表面及至少同側核 板之表面，其中，增層結構具有至少一介電層、至少 20 200931456 一疊置於介電層表面之第二線路層、及設於介電層中之複 數導電盲孔。 上述嵌埋電容元件封裝基板之製法更可包括形成一防 焊層覆蓋增層結構，且該防焊層具有複數開孔而可以顯露 5 部份第二線路層作為複數電性連接墊。 除此之外，上述嵌埋電容元件封裝基板之製法亦可再 包括形成至少一貫穿電容元件、核心板及增層結構之導電 通孔，該導電通孔係電性連接電容元件相對兩表面之外線 ❹ 路層，以及電性連接外線路層與第二線路層。 10 在上述嵌埋電容元件封裝基板之製法中，電容元件也 可再包含有至少一貫穿電容元件之導電結構，該導電結構 係電性連接高介電材料層相對兩表面之外線路層，且該導 電結構係為導電盲孔、導電通孔、或上述兩者之組合。 綜上所述，可瞭解到本發明所提供之嵌埋電容元件封 15裝基板及其製法，因其中之電容元件係先行使用高介電材 料層相對兩表面以層壓有金屬層之核心板製成’沒有習知 〇 技術中因高介電材料層於非電容區造成材料浪費，因此利 於降低成本。另一方面，埋設此種電容元件可避免於線路 間或上下層線路產生寄生電容之漏電問題發生。且透過嵌 20埋此種電容元件，因高介電材料層兩表面支撐性不佳之碎 裂現象也就不會發生。再者，埋設此種電容元件可避免習 知技術中因電極板與線路係佈局在同一層線路造成佈局空 間的限制，因此利於電容與線路佈局的靈活性；最後，由 於此種電容元件外觀及尺寸，比習知表面貼裝技術（surface 11 200931456 m〇unttechnology，SMT)常用電容之厚度薄且體積小，因 此有利於I埋人封裝基板中，以達到封裝基板整體輕薄短 小之要求。 5 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 ❹ 的具體實施例加以施行或應用，本說明書中的各項細節亦 10可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 實施例1 參考圖2A至2D，其係為本實施例之製作流程示意圖。 15 首先，如圖2A所示，提供一核心板20，該核心板20係 由兩金屬層21’，22’與其中間夾置一介電層23所構成。 0 接者’如圖2B所示，利用機械方式如鑽孔或切割，使 該核心板20中開設有一貫穿該核心板2〇之開口 2〇丨。然後， 利用圖案化製程，於核心板20兩表面分別形成一第一線路 20 層 21，22。 如圖2C所示’於核心板20之開口 201中置放一個電容元 件30。該電容元件30包含一高介電材料層33及一設於該高 介電材料層33之相對兩表面之外線路層31,32，其中該外線 路層31，32具有至少一對以該高介電材料層33間隔且互相平 12 200931456 5 ❹ 10 15 20 行對應之外電極板312,322。接著’在核心板20及電容元件 30之相對兩表面，分別壓合一介電層43 ’使部分該介電層 43材料填充進入核心板20之開口 201及電容元件30之間 隙，以嵌埋電容元件30於核心板20之開口 201中。於此所使 用之介電層43可為感光或非感光有機樹脂，舉例如ABF (Ajinomoto Build-up Film)、聯二苯環 丁二烯 (benzocylobutene，BCB )、液晶聚合物（liquid crystal polymer，LCP )、聚亞醯胺（polyimide，PI )、聚乙烯醚 (poly(phenylene ether) » PPE )、聚四氟乙稀 (poly(tetra-fluoroethylene) > PTFE)、FR4、FR5、雙順丁 醯二酸醯亞胺/三氮啡（bismaleimide triazine，BT )、芳香 尼龍（aramide)等，或亦可為混合環氧樹脂與玻璃纖維等材 料。而後，於介電層43之表面，利用物理方式如濺鍍、蒸 鍍或化學方式如電鍍、無電電鍍，形成一金屬層45’，46’ ’ 該金屬層45’,46’之材料，可為錫、銀、銅、金、鉻、鉍、 鈦、銻、辞、鎳、锆、鎂、銦、鎵、銅/鉻合金或錫/鉛合金° 本實施例中，該金屬層45’,46’之材料係使用銅。 然後，如圖2D-1所示，利用雷射蝕孔或機械鑽孔’齡 合電鍍與蝕刻，於介電層43表面形成第二線路層45,46 ’ . 且在介電層43中形成複數導電盲孔471，472,473,474，以分 別電性連接第二線路層45與外線路層31、第二線路層45與 外線路層32、第二線路層45與第一線路層21、及第二線絡 層46與第一線路層22。此外，形成貫穿介電層43及核心板 20之複數導電通孔48以電性連接第二線路層45,46及核心板 13 200931456 20之第一線路層21，22。上述之介電層43、第二線路層 45,46、以及導電盲孔471，472,473,474三者合起來構成增層 結構40,40’。接著，於增層結構40之表面，形成一防焊層 61,62，且該防焊層61，62具有複數開孔614,624以顯露部份 5 第二線路層45,46作為電性連接墊455,465。 如此，即完成本發明嵌埋電容元件之封裝基板，如圖 2D-1至2E-2所示。其中，圖2D-1之封裝基板包括：一核心 板20,係具有一貫穿核心板20之開口 201及一設於核心板20 0 相對兩表面之第一線路層21，22 ; —電容元件30，係設於核 10 心板20之開口 201，該電容元件30包含一高介電材料層33及 一設於該高介電材料層33之相對兩表面之外線路層3 1，32， 其中，該外線路層31,32具有至少一對以該高介電材料層33 間隔且互相平行對應之外電極板312,322 ;以及一增層結構 40,40’，係設於核心板20之至少一表面及同側該電容元件30 15 之表面，其中，該增層結構40,40’具有至少一介電層43、至 少一疊置於介電層43表面之第二線路層45,46、及設於介電 ^ 層43中之複數導電盲孔471，472,473,474，部份導電盲孔 ❹ 473,474係電性連接第一線路層21,22與第二線路層45,46， 並且至少二供導接相異電性之導電盲孔471，472，係設於同 20 側之增層結構40,導電盲孔471電性連接外線路層31與第二 線路層45，導電盲孔472延申並貫穿該高介電材料層33，以 直接電性連接外線路層32與第二線路層45。 圖2D-2為本實施例之第二態樣，其與圖2D-1之差異， 在於其包括至少一貫穿該電容元件30及增層結構40,40’之 200931456 導電通孔482，該導電通孔482係電性連接該電容元件30之 外線路層32，及增層結構40,40’之第二線路層45,46。 圖2D-3為本實施例之第三態樣，其與圖2D-1之差異， 在於其包括至少二貫穿該電容元件30及增層結構40,40’之 5 導電通孔481，482，該導電通孔481，482係分別電性連接該電 容元件30之外線路層31,32，及增層結構40,40’之第二線路 層 45,46。 圖2D-4為本實施例之第四態樣，其與圖2D-1之差異， 在於其至少二供導接相異電性之導電盲孔471,472係設於對 10 側之增層結構40,40’，並分別電性連接外線路層31，32與第 二線路層45,46。 圖2D-5為本實施例之第五態樣，其與圖2D-1之差異， 在於該電容元件30具有至少一導電盲孔35，而導電盲孔472 係與電容元件30之外線路層31電性連接，並藉由該導電盲 15 孔35以電性連接至外線路層32。 圖2E-1所示為本實施例之第六態樣，其與圖2D-1之差 異，在於該電容元件30係包含外線路層3 1，32、高介電材料 層33及内線路層34。其中，外線路層31,32位於電容元件30 相對兩表面具有外電極板312,322 ;内線路層34嵌埋於高介 20 電材料層33内，且内線路層34與外線路層31，32、及内線路 層34間係以高介電材料層33間隔。在該電容元件30中，内 線路層34同樣具有内電極板342，該内電極板342係平行對 應於外電極板3 12,322。部分導電通孔483,484係貫穿增層結 15 200931456 構40,40’及電容元件30，以電性連接外線路層31，32、内線 路層34及第二線路層45,46。 如圖2E-2所示為本實施例之第七態樣，其與圖2E-1之 差異，在於該電容元件30係包含外線路層31，32、高介電材 5 料層33、内線路層34、及導電通孔361，362。其中，導電通 孔361，362係電性連接外線路層31，32及内線路層34,增層結 構40,40’具有供導接相異電性之導電盲孔471,472以電性連 接外線路層31，32及第二線路層45,46。 ❹ 10 實施例2 參考圖3 A至3D，其係為本實施例之製作流程示意圖。 首先，如圖3A所示，提供一核心板20，該核心板20係 由兩金屬層2Γ,22’與其中間夾置一介電層23所構成。 接者，如圖3B所示，利用圖案化製程，於核心板20兩 15 表面分別形成一第一線路層21，22。在第一線路層21，22中， 已預備一空曠區域23a，23b (亦即無線路佈局）供設置電容 元件用。 如圖3C所示，將一電容元件30接置於空曠區域23a，23b 中。該電容元件30包含一高介電材料層33以及外線路層 20 31，32,其中外線路層31，32位於高介電材料層32之相對兩表 面且具有外電極板312,322，此外電極板312,322係以高介電 材料層33間隔，高介電材料層33兩表面之外電極板312,322 係互相平行對應。接著，在核心板20及電容元件30之相對 兩表面，分別壓合一介電層43,44，以固定電容元件30於空 25 曠區域23a，23b中並嵌埋其於介電層43,44中。於此所使用之 16 200931456 5 ❷ 10 15 ❹ 20 "電層43，44材料可參考實施例1所述。而後，於介電層a 44 之表面，利用物理方式如濺鍍、蒸鍍或化學方式如電鍍、 無電電鍍’形成一金屬層45，，46’，該金屬層45，，46,之材料 可參考實施例1所述。 然後’如圖3D所示，利用雷射蝕孔或機械鑽孔，配合 電鍍與蝕刻，於介電層43,44表面形成第二線路層45,46,並 且在介電層43,44中形成供導接相異電性之複數導電盲孔 471，472以電性連接第二線路層45,46及外線路層31，32，此 外’形成貫穿介電層43,44及核心板20之複數導電通孔48， 以電性連接第二線路層45，46及核心板20之第一線路層 21，22。上述之介電層43,44、第二線路層45,46、以及導電 盲孔471，472,473,474三者合起來構成增層結構4〇,4〇’。接 著’於增層結構40,40’之表面，形成一防焊層61，62，且該 防焊層61，62具有複數開孔614,624以顯露部份第二線路層 45,46作為電性連接墊455,465。 如此’即完成本發明嵌埋電容元件之封裝基板，如圖 3D所示’其包括：一核心板2〇係具有設於核心板2〇相對兩 表面之第一線路層21; —電容元件30,係設於核心板20至 少一表面之部份區域23a，23b，該電容元件30包含一高介電 材料層33及—設於該高介電材料層33之相對兩表面之外線 路層31，32’其中，該外線路層31具有至少一對以該高介電 材料層33間隔且互相平行對應之外電極板312,322 ;以及一 增層結構4〇,4〇，，係設於核心板2〇之至少一表面及同側電容 元件30之表面。該增層結構4〇,4〇，具有至少一介電層 17 200931456 43,44、至少一疊置於介電層43,44表面之第二線路層 45,46、及設於介電層43,44中之複數導電盲孔 471,472,473,474。在該增層結構40,40’中，部份導電盲孔 473,474係電性連接第一線路層21，22與第二線路層45,46， 5 並且至少一導電盲孔471係電性連接外線路層31與第二線 路層45,46,至少一導電盲孔472係電性連接外線路層32與第 二線路層45，46，以供導接相異電性。此外，本實施例亦包 括貫穿增層結構40,40’及核心板20之導電通孔48，該導電通 孔48係電性連接核心板20相對兩表面之第一線路層21，22及 10 增層結構40,40’之第二線路層45,46。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 15 【圖式簡單說明】 圖1係習知壓合式電容元件之封裝基板結構剖面示意圖。 圖2A至2D-1係本發明實施例1之製作流程剖面示意圖。 圖2D-2至2E-2係本發明實施例1之其他態樣。 20 圖3A至3D係本發明實施例2之製作流程剖面示意圖。 【主要元件符號說明】 1〇 内層電路板 11 内層線路層 18 200931456In addition, the method for fabricating the embedded capacitor device package substrate may further include forming at least one conductive via hole penetrating through the capacitor element and the build-up structure, the conductive via hole electrically connecting the capacitor element to the opposite surfaces a layer, and electrically connecting the outer circuit layer and the second circuit layer. In the above method for fabricating a buried capacitor device package substrate, the capacitor element may further include at least one conductive structure penetrating the capacitor element, the conductive structure electrically connecting the N dielectric material layer to the circuit layer outside the two surfaces, and the The conductive structure is a conductive blind via, a conductive via, or a combination of the two. Further, the capacitive element may further comprise at least an inner circuit layer embedded in the high dielectric material layer m. The circuit layer and the outer circuit layer are spaced apart by a layer of high dielectric material. The inner wiring layer has at least one inner electrode plate which is parallel to a pair of the outer electrode plates. The present invention also provides a method of fabricating a buried capacitor device package substrate. Including: providing a core board '纟中' core board having a first circuit layer disposed on two opposite tables; a capacitor-shaped component at least a surface of the core board, wherein the capacitor element comprises a high dielectric material And a layer disposed on the outer surface of the opposite layers of the dielectric material layer and the outer circuit layer having a plurality of layers spaced apart from each other by the dielectric material layer and corresponding to each other and forming a layered structure on the surface of the capacitor element And at least the surface of the ipsilateral core plate, wherein the buildup structure has at least one dielectric layer, at least 20 200931456, a second circuit layer stacked on the surface of the dielectric layer, and a plurality of conductive blind holes disposed in the dielectric layer . The method for fabricating the embedded capacitor device package substrate further includes forming a solder resist layer covering buildup structure, and the solder resist layer has a plurality of openings to expose the 5 portions of the second circuit layer as the plurality of electrical connection pads. In addition, the method for fabricating the embedded capacitor device package substrate may further include forming at least one conductive via hole penetrating through the capacitor element, the core plate and the build-up structure, the conductive via being electrically connected to the opposite surfaces of the capacitor element The outer layer is connected to the road layer, and the outer circuit layer and the second circuit layer are electrically connected. In the above method for fabricating a buried capacitor device package substrate, the capacitor element may further include at least one conductive structure penetrating through the capacitor element, the conductive structure electrically connecting the layer of the high dielectric material layer to the circuit layer outside the two surfaces, and The conductive structure is a conductive blind via, a conductive via, or a combination of the two. In summary, the embedded capacitor device package 15 substrate and the method for manufacturing the same are provided, wherein the capacitor element is a core plate with a metal layer laminated on opposite sides of the high dielectric material layer. In the process of 'no know-how', the material is wasted due to the high dielectric material layer in the non-capacitor region, which is beneficial to reduce the cost. On the other hand, embedding such a capacitive element can avoid the occurrence of a leakage problem of parasitic capacitance between lines or upper and lower lines. And by embedding such a capacitor element in the recess 20, the chipping phenomenon of the poor support of both surfaces of the high dielectric material layer does not occur. Furthermore, the embedding of such a capacitive element can avoid the limitation of the layout space caused by the electrode plate and the circuit system layout on the same layer line in the prior art, thereby facilitating the flexibility of the capacitance and the line layout; finally, due to the appearance of the capacitive element and Dimensions, compared with the conventional surface mount technology (surface 11 200931456 m〇unttechnology, SMT), the thickness of the commonly used capacitor is thin and small, so it is beneficial to the buried substrate of the package to meet the requirements of the overall thinness and shortness of the package substrate. [Embodiment] The embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Embodiment 1 Referring to Figures 2A to 2D, it is a schematic diagram of the manufacturing process of the present embodiment. First, as shown in Fig. 2A, a core board 20 is provided which is constructed by sandwiching a dielectric layer 23 between two metal layers 21', 22'. As shown in Fig. 2B, a mechanical opening such as drilling or cutting is used to open an opening 2 through the core plate 20 in the core plate 20. Then, a first line 20 layer 21, 22 is formed on both surfaces of the core board 20 by a patterning process. A capacitor element 30 is placed in the opening 201 of the core board 20 as shown in Fig. 2C. The capacitor element 30 includes a high dielectric material layer 33 and a circuit layer 31, 32 disposed on opposite surfaces of the high dielectric material layer 33, wherein the outer circuit layer 31, 32 has at least one pair The dielectric material layers 33 are spaced apart and are flat with each other 12 200931456 5 ❹ 10 15 20 rows corresponding to the outer electrode plates 312, 322. Then, a dielectric layer 43 is pressed onto the opposite surfaces of the core board 20 and the capacitor element 30 to partially fill the gap between the opening 201 of the core board 20 and the capacitor 30 to be embedded. The capacitive element 30 is in the opening 201 of the core board 20. The dielectric layer 43 used herein may be a photosensitive or non-photosensitive organic resin, such as ABF (Ajinomoto Build-up Film), benzocylobutene (BCB), liquid crystal polymer (liquid crystal polymer, LCP), polyimide (PI), poly(phenylene ether) PPE, poly(tetra-fluoroethylene) PTFE, FR4, FR5, dicis Bismuthimide triazine (BT), aramide, etc., or may be a mixture of epoxy resin and glass fiber. Then, on the surface of the dielectric layer 43, a metal layer 45', 46'' of the metal layer 45', 46' is formed by physical means such as sputtering, evaporation or chemical means such as electroplating or electroless plating. Tin, silver, copper, gold, chromium, niobium, titanium, niobium, rhodium, nickel, zirconium, magnesium, indium, gallium, copper/chromium alloy or tin/lead alloy. In this embodiment, the metal layer 45', The material used in 46' is copper. Then, as shown in FIG. 2D-1, a second wiring layer 45, 46' is formed on the surface of the dielectric layer 43 by laser etching or mechanical drilling 'age plating and etching, and is formed in the dielectric layer 43. The plurality of conductive blind vias 471, 472, 473, 474 are electrically connected to the second wiring layer 45 and the outer wiring layer 31, the second wiring layer 45 and the outer wiring layer 32, the second wiring layer 45 and the first wiring layer 21, and the second The wire layer 46 and the first circuit layer 22. In addition, a plurality of conductive vias 48 are formed through the dielectric layer 43 and the core board 20 to electrically connect the second circuit layers 45, 46 and the first circuit layers 21, 22 of the core board 13 200931456 20 . The dielectric layer 43, the second wiring layers 45, 46, and the conductive blind vias 471, 472, 473, 474 are combined to form the buildup structure 40, 40'. Next, on the surface of the build-up structure 40, a solder resist layer 61, 62 is formed, and the solder resist layers 61, 62 have a plurality of openings 614, 624 to expose the portion 5 of the second circuit layer 45, 46 as electrical connection pads 455, 465 . Thus, the package substrate of the embedded capacitive element of the present invention is completed, as shown in Figs. 2D-1 to 2E-2. The package substrate of FIG. 2D-1 includes: a core board 20 having an opening 201 extending through the core board 20 and a first circuit layer 21, 22 disposed on opposite surfaces of the core board 20 0. The capacitor element 30 includes a high dielectric material layer 33 and a circuit layer 3 1,32 disposed on opposite surfaces of the high dielectric material layer 33, wherein the capacitor element 30 is disposed in the opening 201 of the core 10 The outer circuit layers 31, 32 have at least one pair of outer electrode plates 312, 322 spaced apart from each other by the high dielectric material layer 33 and parallel to each other; and a build-up structure 40, 40' disposed on at least one of the core plates 20. The surface and the surface of the capacitive element 30 15 on the same side, wherein the build-up structure 40, 40' has at least one dielectric layer 43, at least one second circuit layer 45, 46 stacked on the surface of the dielectric layer 43, and The plurality of conductive blind vias 471, 472, 473, 474 disposed in the dielectric layer 43 are electrically connected to the first circuit layers 21, 22 and the second circuit layers 45, 46, and at least two are connected Conductive blind vias 471, 472 of different electrical properties are connected to the build-up structure 40 of the same 20 side, and the conductive blind vias 471 are electrically connected. An outer layer circuit 31 and the second circuit layer 45, conductive vias 472 extending through the application and the high dielectric material layer 33, directly electrically connected to the outer circuit layer 32 and the second wiring layer 45. 2D-2 is a second aspect of the present embodiment, which differs from FIG. 2D-1 in that it includes at least one 200931456 conductive via 482 extending through the capacitive element 30 and the build-up structure 40, 40'. The via 482 is electrically connected to the circuit layer 32 outside the capacitor element 30, and the second circuit layers 45, 46 of the build-up structure 40, 40'. 2D-3 is a third aspect of the present embodiment, which differs from FIG. 2D-1 in that it includes at least two conductive vias 481, 482 extending through the capacitive element 30 and the build-up structure 40, 40'. The conductive vias 481, 482 are electrically connected to the circuit layers 31, 32 outside the capacitor element 30, and the second circuit layers 45, 46 of the build-up structure 40, 40', respectively. 2D-4 is a fourth aspect of the present embodiment, which differs from FIG. 2D-1 in that at least two conductive blind vias 471, 472 for conducting the opposite phase are provided on the pair 10 side of the buildup structure 40. , 40', and electrically connected to the outer circuit layers 31, 32 and the second circuit layers 45, 46, respectively. 2D-5 is a fifth aspect of the embodiment, which differs from FIG. 2D-1 in that the capacitive element 30 has at least one conductive via 35 and the conductive via 472 is connected to the circuit layer outside the capacitor 30. 31 is electrically connected and electrically connected to the outer circuit layer 32 by the conductive blind 15 hole 35. 2E-1 shows a sixth aspect of the present embodiment, which differs from FIG. 2D-1 in that the capacitive element 30 includes an outer circuit layer 31, 32, a high dielectric material layer 33, and an inner circuit layer. 34. The outer circuit layers 31, 32 have outer electrode plates 312, 322 on opposite surfaces of the capacitor element 30; the inner circuit layer 34 is embedded in the high dielectric material layer 33, and the inner circuit layer 34 and the outer circuit layer 31, 32, The inner wiring layers 34 are spaced apart by a layer of high dielectric material 33. In the capacitor element 30, the inner wiring layer 34 also has an inner electrode plate 342 which corresponds in parallel to the outer electrode plates 3, 12, 322. A portion of the conductive vias 483, 484 extend through the buildup layer 15 200931456 40, 40' and the capacitor element 30 to electrically connect the outer wiring layers 31, 32, the inner wiring layer 34, and the second wiring layers 45, 46. FIG. 2E-2 shows a seventh aspect of the embodiment, which is different from FIG. 2E-1 in that the capacitor element 30 includes an outer circuit layer 31, 32, a high dielectric material 5 layer 33, and an inner surface. The circuit layer 34 and the conductive vias 361, 362. The conductive vias 361, 362 are electrically connected to the outer circuit layers 31, 32 and the inner circuit layer 34. The build-up structures 40, 40' have electrically conductive blind vias 471, 472 for conducting electrical connections. Layers 31, 32 and second circuit layers 45, 46. ❹ 10 Embodiment 2 Referring to FIG. 3A to 3D, it is a schematic diagram of the manufacturing process of the present embodiment. First, as shown in Fig. 3A, a core board 20 is provided which is composed of two metal layers 2, 22' interposed therebetween with a dielectric layer 23. As shown in FIG. 3B, a first circuit layer 21, 22 is formed on the surfaces of the core plates 20 and 15 respectively by a patterning process. In the first circuit layers 21, 22, an open area 23a, 23b (i.e., a wireless path layout) has been prepared for the provision of the capacitor elements. As shown in Fig. 3C, a capacitor element 30 is placed in the open area 23a, 23b. The capacitor element 30 includes a high dielectric material layer 33 and outer circuit layers 20 31, 32, wherein the outer circuit layers 31, 32 are located on opposite surfaces of the high dielectric material layer 32 and have outer electrode plates 312, 322, and further electrode plates 312, 322. The layers of the high dielectric material layer 33 are spaced apart, and the electrode plates 312, 322 of the two surfaces of the high dielectric material layer 33 are parallel to each other. Next, on the opposite surfaces of the core board 20 and the capacitor element 30, a dielectric layer 43 and 44 are respectively pressed to fix the capacitor element 30 in the empty 25 旷 regions 23a, 23b and embedded in the dielectric layer 43. 44. 16 200931456 5 ❷ 10 15 ❹ 20 " Electrical layer 43, 44 material can be referred to as described in Embodiment 1. Then, on the surface of the dielectric layer a 44, a metal layer 45, 46' is formed by physical means such as sputtering, evaporation or chemical means such as electroplating, electroless plating, and the material of the metal layer 45, 46 can be Refer to Example 1 for description. Then, as shown in FIG. 3D, a second wiring layer 45, 46 is formed on the surface of the dielectric layers 43, 44 by laser etching or mechanical drilling, by electroplating and etching, and formed in the dielectric layers 43, 44. The plurality of conductive vias 471, 472 for conducting the phase difference electrical connection electrically connect the second circuit layers 45, 46 and the outer circuit layers 31, 32, and further "form the plurality of dielectric layers 43, 44 and the core plate 20 The conductive vias 48 electrically connect the second circuit layers 45, 46 and the first circuit layers 21, 22 of the core board 20. The dielectric layers 43, 44, the second wiring layers 45, 46, and the conductive blind vias 471, 472, 473, 474 are combined to form a build-up structure 4", 4". Next, a solder resist layer 61, 62 is formed on the surface of the build-up structure 40, 40', and the solder resist layers 61, 62 have a plurality of openings 614, 624 to expose portions of the second circuit layers 45, 46 as electrical connections. Pad 455, 465. Thus, the package substrate of the embedded capacitor element of the present invention is completed, as shown in FIG. 3D, which includes: a core board 2 having a first circuit layer 21 disposed on opposite surfaces of the core board 2; And a partial region 23a, 23b disposed on at least one surface of the core board 20. The capacitor element 30 includes a high dielectric material layer 33 and a circuit layer 31 disposed on opposite surfaces of the high dielectric material layer 33. , wherein the outer circuit layer 31 has at least one pair of outer electrode plates 312, 322 spaced apart from each other by the high dielectric material layer 33 and parallel to each other; and a build-up structure 4〇, 4〇, which is attached to the core board At least one surface of the surface and the surface of the same side capacitive element 30. The build-up structure 4〇, 4〇, having at least one dielectric layer 17 200931456 43,44, at least one second wiring layer 45, 46 stacked on the surface of the dielectric layer 43, 44, and disposed on the dielectric layer 43 , a plurality of conductive blind holes 471, 472, 473, 474. In the build-up structure 40, 40', a portion of the conductive vias 473, 474 are electrically connected to the first circuit layer 21, 22 and the second circuit layers 45, 46, 5 and at least one conductive via 471 is electrically connected. The circuit layer 31 and the second circuit layers 45, 46, and at least one conductive blind via 472 are electrically connected to the outer circuit layer 32 and the second circuit layer 45, 46 for conducting electrical conductivity. In addition, the embodiment also includes a conductive via 48 extending through the build-up structure 40, 40' and the core board 20. The conductive via 48 is electrically connected to the first circuit layers 21, 22 and 10 of the opposite surfaces of the core board 20. The second circuit layers 45, 46 of the buildup structure 40, 40'. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 15 [Simple description of the drawings] Fig. 1 is a schematic cross-sectional view showing the structure of a package substrate of a conventional pressure-sensitive capacitive element. 2A to 2D-1 are schematic cross-sectional views showing a manufacturing process of Embodiment 1 of the present invention. 2D-2 to 2E-2 are other aspects of Embodiment 1 of the present invention. 20A to 3D are schematic cross-sectional views showing a manufacturing process of Embodiment 2 of the present invention. [Main component symbol description] 1〇 Inner circuit board 11 Inner circuit layer 18 200931456
111 下電極板 12, 33 高介電材料層 13 外層線路層 131 上電極板 132 連接墊 14,361,362,48,481，482,483 導電通孔 15,61,62 防焊層 151, 614,624 開孔 20 核心板 201 開口 21',22' 金屬層 21,22 第一線路層 23a,23b 空曠區域 23, 43,44 介電層 17,30 電容元件 31,32 外線路層 312,322 外電極板 34 内線路層 342 内電極板 35,471,472,473,474 導電盲孔 40,40' 增層結構 45,46 第二線路層 455,465 電性連接墊 19111 lower electrode plate 12, 33 high dielectric material layer 13 outer circuit layer 131 upper electrode plate 132 connection pad 14,361,362,48,481,482,483 conductive via 15,61,62 solder resist layer 151, 614,624 opening 20 core plate 201 opening 21 ',22' metal layer 21,22 first circuit layer 23a,23b open area 23, 43,44 dielectric layer 17,30 capacitive element 31,32 outer circuit layer 312,322 outer electrode plate 34 inner circuit layer 342 inner electrode plate 35,471,472,473,474 Conductive blind vias 40, 40' buildup structure 45, 46 second trace layer 455, 465 electrical connection pads 19