TWI224389B - Semiconductor package substrate with embedded resistors and method for fabricating the same - Google Patents
Semiconductor package substrate with embedded resistors and method for fabricating the same Download PDFInfo
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- TWI224389B TWI224389B TW92126796A TW92126796A TWI224389B TW I224389 B TWI224389 B TW I224389B TW 92126796 A TW92126796 A TW 92126796A TW 92126796 A TW92126796 A TW 92126796A TW I224389 B TWI224389 B TW I224389B
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- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
1224389 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種内嵌電阻元件半導體封裝基板及 其製作方法，尤指一種在多層電路板中内嵌有電阻元件之 半導體封裝基板及其製法，藉以提供半導體裝置良好之電 性功能。 【先前技術】 由於半導體製程之進步，以及半導體晶片上電路功能 的不斷提昇，使得半導體裝置之發展走向高度集積化，就 以球柵陣列式（BG A)半導體裝置為例，此種藉由成陣列方 式植佈於基板底面上之銲球（S ο 1 d e r b a 1 1 )以提供半導體 晶片與印刷電路板（PCB)等外界裝置電性連接之結構，相 較於傳統以導線架（L e a d f r a m e )為主之半導體裝置，該球 柵陣列式半導體裝置於相同單位面積内得設有較多之輸出 /輸入連接端，以容納更多之電子電路及半導體晶片接置 其上。 惟半導體裝置之集積化，封裝構造之接腳數目亦隨著 增加，而由於接腳數目之增多，導致雜訊亦隨之增大，因 此，一般為消除雜訊，係於半導體封裝構造中加入被動元 件，如電阻元件、電容元件與電感元件，以消除雜訊及穩 定電路，藉以使得所封裝之半導體晶片具有特定之電流特 性。 如第1圖所示，係習知在基板表面接置有被動元件之 剖視圖，該基板1 0表面之預設位置上形成有至少一對間隔 開之銲墊1 1，該對銲墊1 1係外露出用以覆蓋該基板1 0上之1224389 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package substrate with embedded resistance elements and a manufacturing method thereof, particularly a semiconductor package substrate with a resistance element embedded in a multilayer circuit board. And its manufacturing method, so as to provide good electrical functions of the semiconductor device. [Previous technology] Due to the advancement of semiconductor manufacturing processes and the continuous improvement of circuit functions on semiconductor wafers, the development of semiconductor devices has become highly integrated. Take ball grid array (BG A) semiconductor devices as an example. Array-type solder balls (S ο 1 derba 1 1) implanted on the bottom surface of the substrate to provide a structure for electrically connecting semiconductor wafers and external devices such as printed circuit boards (PCBs), compared to the traditional lead frame. As a main semiconductor device, the ball grid array type semiconductor device can be provided with more output / input connection terminals in the same unit area to accommodate more electronic circuits and semiconductor wafers mounted on it. However, with the integration of semiconductor devices, the number of pins in the package structure also increases. As the number of pins increases, the noise also increases. Therefore, in order to eliminate noise, it is generally added to the semiconductor package structure. Passive components, such as resistive, capacitive, and inductive components, eliminate noise and stabilize the circuit, so that the packaged semiconductor chip has specific current characteristics. As shown in FIG. 1, it is a conventional cross-sectional view of a passive component connected to the surface of a substrate. At least a pair of spaced-apart pads 1 1 are formed on a predetermined position on the surface of the substrate 10. The pair of pads 1 1 Is exposed to cover the substrate 10
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拒辉劑層1 2， 至塗覆有錫膏 使該被動元件 11。然而，因 確性控制不易 因此通常在被 如此在後續半 使錫膏1 3軟化 上之錫膏1 3相 品良率。 俾將至少一 1 3之該對銲 1 4藉由該錫 鍚膏1 3塗佈 ’以及拒銲 動元件1 4與 導體製程之 而在間隙中 互橋接，以 被動元件 墊1 1上並 膏1 3而電 數量與其 劑層1 2表 拒銲劑層 熱處理環 受毛細現 致產生被 1 4之兩 進行回 性連接 經回銲 面難以 12間易 境中， 象作用 動元件 端1 4 0分別黏著 銲銲接處理，以 至該基板銲墊 處理後之高度精 完全控制平整， 形成一間隙1 5， 於高溫狀態下將 造成該對鮮墊11 1 4短路而影響成 二二弟圖，鑒此，美國專利第6，1 〇 8，2 1 2號案係直 接在一基板20表面形成有銲墊21與電極端22，並於該銲墊 21與電極端22間形成有電性阻件（Electr ical ly r e s i s t i v e ν ο 1 u m e ) 2 3以構成一被動元件，以供該基板2 〇 透過植接於該銲墊2 1上之金屬凸塊2 4而與其餘電子裝置 25，如印刷電路板電性導接，同時經由該銲墊2卜電極 22、與電性阻件23所構成之被動元件以提供半導體裝置較 佳之電性品質。惟該基板表面整合有電阻元件之電阻電極 之距離（P i t ch )必須夠大，方能順利形成電性阻件並發揮 電阻之效能，然基板表面之面積有限，過大的電阻佈設面 積勢必擠壓基板表面其他線路之佈線密度，不利基板線路 佈局（Routability)之靈活性，導致該等被動元件佈設數 量受到侷限，亦不利半導體裝置高度集積化之發展趨勢； 甚者，被動元件佈設數量將隨著半導體封裝件高性能之要The anti-radiation agent layer 12 is coated with a solder paste to make the passive element 11. However, since the accuracy control is not easy, the solder paste 13 is usually softened in the subsequent half of the solder paste 13 and the yield rate of the phase 13 is lower.至少 Apply at least one 13 of the butt joints 1 4 with the solder paste 13 and the solder resistive element 14 and the conductor process to bridge each other in the gap, and paste on the passive element pad 11 and paste 1 3 The quantity of electricity and its flux layer 1 2 The capillaries of the heat treatment ring of the solder resist layer are caused by the capillary to be reconnected by the two of 1 4 It is difficult to pass through the reflow surface in 12 places, such as the end of the active element 1 4 0 Adhesive welding process, so that the height after the substrate pad treatment is completely controlled and flattened to form a gap 15, which will cause the pair of fresh pads 11 1 4 to short-circuit at high temperature and affect the two-dimensional map. US Patent No. 6,108,2 1 2 is formed by directly forming a pad 21 and an electrode terminal 22 on a surface of a substrate 20, and an electrical resistance member (Electr) is formed between the pad 21 and the electrode terminal 22. ical ly resistive ν ο 1 ume) 2 3 to form a passive component for the substrate 20 to pass through the metal bumps 24 that are implanted on the pad 21 and communicate with the rest of the electronic device 25, such as a printed circuit board. Conductive connection, and at the same time through the pad 2 electrode 22, and the electrical resistance member 23 As compared with the passive element to provide a good quality of the electrical semiconductor device. However, the distance (P it ch) of the resistance electrodes with integrated resistance elements on the substrate surface must be large enough to successfully form an electrical resistance element and exert the resistance effect. However, the area of the substrate surface is limited, and an excessively large resistor layout area will be squeezed The wiring density of other circuits on the substrate surface is detrimental to the flexibility of the substrate circuit layout (Routability), which results in the limitation of the number of these passive components and the development trend of high integration of semiconductor devices. Furthermore, the number of passive components will vary with the The key to high performance of semiconductor packages
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五、發明說明（3) 求而相對地遽增’如採前述方法該基板表面必須同時容納 半導體晶片以及大量被動元件，而不符合半導體封裝件輕 薄短小之發展潮流。 1 請參閱第3圖’為解決前述問題，美國專利第 6，2 7 8，3 5 6號案揭露一種具平面植入式被動元件之基板 3 〇，其係在一絕緣層3 1之上下表面形成有銅層3 2，該銅層 32具有一蝕刻圖像320，再藉由印刷（Printing)方式於該曰 鋼層32上形成一介電層33，並使其得以充填至該蝕刻圖像 3 2 0中’再於该銅層3 2及介電層3 3上以印刷方式形成有一 随層3 4，其中藉由形成在該銅層3 2間之阻層3 4作為一電 阻το件’以及藉由該銅層3 2間之蝕刻圖像3 2 〇内介電層3 3 作為一電容元件，俾在一基板上整合有多數之被動元件。 惟上述結構中，係僅以印刷方式於基板上形成該介電 層3 3與阻層34’因此其電容值與電阻值不易精確控制，此 外’該阻層3 4同時覆蓋於銅層3 2與介電層3 3兩不同材料之 界面上，於後續製程及測試之高溫、高濕環境易產生信賴 性問題，而影響該阻層與電極間之電性連接關係。 再者’隨著電子產業的蓬勃發展，電子產品亦逐漸邁 入多功能、高性能的研發方向。為滿足半導體封裝件高積 二度（Integration)以及微型化（Miniaturizati〇n)的封裝 ^求’提供多數主被動元件及線路載接之電路板亦逐漸由 單層板演變成多層板（Mu 11 i - 1 ayer board)，俾於有限的 二間下藉由層間連接技術（Interlayer connection)擴 大電路板上可利用的電路面積而配合高電子密度之積體電V. Description of the invention (3) The demand is relatively increased. If the aforementioned method is adopted, the substrate surface must simultaneously contain a semiconductor wafer and a large number of passive components, which does not meet the development trend of thin and short semiconductor packages. 1 Please refer to FIG. 3 'In order to solve the foregoing problem, US Patent No. 6, 2 7 8, 3 56 discloses a substrate 3 with a planar implanted passive component, which is above and below an insulating layer 31. A copper layer 32 is formed on the surface, the copper layer 32 has an etched image 320, and a dielectric layer 33 is formed on the steel layer 32 by printing, so that it can be filled into the etching pattern. As in 3 2 0, a trailing layer 3 4 is formed on the copper layer 32 and the dielectric layer 3 3 by printing. The resistance layer 3 4 formed between the copper layer 32 and 2 serves as a resistor το. And the internal dielectric layer 3 3 as a capacitor element, and a plurality of passive elements are integrated on a substrate. However, in the above structure, the dielectric layer 3 3 and the resistive layer 34 ′ are formed on the substrate only by printing. Therefore, it is difficult to accurately control the capacitance value and the resistive value. In addition, the resistive layer 3 4 covers the copper layer 3 2 at the same time. At the interface of two different materials with the dielectric layer 33, reliability problems are likely to occur in the high temperature and high humidity environment of subsequent processes and tests, which affects the electrical connection relationship between the resist layer and the electrode. Furthermore, with the vigorous development of the electronics industry, electronic products have gradually moved into a multi-functional, high-performance research and development direction. In order to meet the integration of semiconductor packages with high integration (Miniature Integration) and miniaturization (Miniaturization) packaging ^ "providing the most active and passive components and circuit-carrying circuit boards have gradually evolved from single-layer boards to multilayer boards (Mu 11 i-1 ayer board), to expand the available circuit area on the circuit board by using the interlayer connection technology to meet the high electron density integrated circuit
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1224389 c i r c u i t )需求。然而， 面形成有被動元件，惟 基板以符合半導體封裝 均未有所述及。 在一具多層電路之半導 時考量製程之信賴性與 薄短小與多功能及高電 元件與半導體晶片等電 昇電子產品之電性功能 、線路佈局性與半導體封 待解決之課題。 五、發明說明（4) 路（Integrated 僅提供在基板表 元件至多層封裝 化的封裝需求則 因此，如何 有被動元件，同 電子產品要求輕 有效數量之被動 裴基板中，以提 導體封裝基板之 加，實為目前亟 【發明内容】 鑒於以上所 提供一種内嵌電 成一整合有電阻 件高積集度與微 本發明之另 封裝基板及其製 置輕薄短小之目 本發明之又 封裝基板及其製 阻值準確度。 本發明之再 封裝基板及其製 前述習知技藝中係 如何應用該些被動 件高積集度與微型 體封裝基板中整合 準確度，俾在現今 性之趨勢下，提供 子元件於半導體封 ，而又不致影響半 裝件整體厚度之增 迷習知技術之缺點，本發明之主要目的係 P且元件之半導體封裝基板及其製法，俾形 元件之多層封裝基板，以符合半導體封裝 型化的封裝需求。 —目的係提供一種内嵌電阻元件之半導體 法’俾縮減基板使用面積，以達半導體裝 標。 ~目的係提供一種内嵌電阻元件之半導體 法’俾提昇製程之信賴性與電阻元件之電 —目的係提供一種内嵌電阻元件之半導體 $ ’提昇半導體裝置内被動元件之佈設數1224389 c i r c u i t) demand. However, passive components are formed on the surface, but the substrate to comply with the semiconductor package is not mentioned. Consider the reliability and thinness of the multi-layer circuit, the thin and small, multi-functional, high-power components, and the electrical functions of electronic products such as semiconductor wafers, circuit layout, and semiconductor packaging issues to be solved. V. Description of the invention (4) Road (Integrated only provides packaging requirements from substrate surface components to multi-layer packaging. Therefore, how to have passive components, like electronic products that require a light and effective number of passive substrates, to improve the efficiency of conductor packaging substrates? In addition, it is really urgent at the present time. [Content of the invention] In view of the above, an embedded package is formed into a package substrate which integrates the high integration degree of the resistor and the micro package of the present invention, and the purpose of making it thin and short. The accuracy of its resistance value. The repackaged substrate of the present invention and the above-mentioned conventional techniques are how to use the high accumulation of passive components and the integration accuracy of the microbody package substrate. Under the current trend, Providing sub-components in semiconductor packages without affecting the shortcomings of the conventional technology of increasing the overall thickness of the half-package. The main object of the present invention is the semiconductor package substrate of the P-component and its manufacturing method, and the multilayer package substrate of the 俾 -shaped component In order to meet the packaging needs of semiconductor packaging. — The purpose is to provide a semiconductor method 'reduction base for embedded resistance elements. The area of the board is used to achieve the semiconductor packaging standard. ~ The purpose is to provide a semiconductor method with embedded resistance elements' 俾 to increase the reliability of the process and the resistance of the resistance element-the purpose is to provide a semiconductor with embedded resistance elements to improve the semiconductor device Number of internal passive components
1224389 五、發明說明（5) 量，並增加基板佈局靈活性。 為達上揭及其它目的，本發明之内嵌電阻元件之半導 體封裝基板，主要係可於封裝基板内埋置有電阻元件，俾 提供半導體裝置整合有電阻元件，同時不致影響基板表面 線路佈局性。 本發明之内嵌電阻元件之半導體封裝基板製法係包括 下列步驟：首先，提供一具有第一線路層之内層電路板， 該第一線路層具有多數之電阻電極，接著於該内層電路板 上形成圖案化電阻材料，俾使該電阻材料電性連接至該電 阻電極，以定義電阻元件之電阻值；然後，於已形成有該 圖案化電阻材料之電路板表面形成至少一絕緣層，並使該 絕緣層形成有盲孔以外露出該電阻電極；之後，於該絕緣 層上形成至少一第二線路層，並藉由多數形成於該絕緣層 之導電盲孔以電性連接相鄰之圖案化線路層與電阻電極。 經由上述製程，本發明之内嵌電阻元件之半導體封裝 基板，主要包括：一内層電路板，其具有第一線路層，該 第一線路層具有多數之電阻電極；至少一圖案化之電阻材 料，係形成於該内層電路板上，並使該電阻材料電性連接 至該電阻電極，以定義電阻元件之電阻值；至少一圖案化 第二線路層，係間隔一絕緣層以堆疊於該已形成有圖案化 電阻材料之電路板表面；以及複數個導電盲孔，係形成於 該絕緣層中，以電性連接相鄰之圖案化線路層與電阻電 極 。 本發明之内嵌電阻元件之半導體封裝基板製法之另一1224389 V. Description of the invention (5) and increase the flexibility of substrate layout. In order to achieve the purpose of disclosure and other purposes, the semiconductor package substrate with embedded resistance elements of the present invention is mainly capable of embedding a resistance element in the package substrate, and providing a semiconductor device with integrated resistance elements without affecting the layout of the substrate surface. . The method for manufacturing a semiconductor package substrate with embedded resistance elements according to the present invention includes the following steps: First, an inner layer circuit board having a first circuit layer is provided. The first circuit layer has a plurality of resistance electrodes, and then formed on the inner layer circuit board. The patterned resistance material is electrically connected to the resistance electrode to define the resistance value of the resistance element; then, at least one insulating layer is formed on the surface of the circuit board on which the patterned resistance material has been formed, and the The resistive electrode is exposed outside the insulating layer with a blind hole formed; then, at least a second circuit layer is formed on the insulating layer, and an adjacent patterned circuit is electrically connected through a plurality of conductive blind holes formed in the insulating layer. Layer and resistance electrode. Through the above process, the semiconductor package substrate with embedded resistance element of the present invention mainly includes: an inner layer circuit board having a first circuit layer having a plurality of resistance electrodes; at least one patterned resistance material, Is formed on the inner layer circuit board, and the resistance material is electrically connected to the resistance electrode to define the resistance value of the resistance element; at least one patterned second circuit layer is separated by an insulation layer to be stacked on the formed A circuit board surface having a patterned resistance material; and a plurality of conductive blind holes formed in the insulation layer to electrically connect adjacent patterned circuit layers and resistance electrodes. Another method for manufacturing a semiconductor package substrate with embedded resistance element of the present invention
17307 全懋.ptd 第10頁 1224389 五、發明說明（6) 實施例係包括：首先，提供一具有第一線路層之内層電路 板，該第一線路層具有多數之電阻電極，接著於該内層電 路板上形成圖案化電阻材料，俾使該電阻材料電性連接至 該電阻電極，以定義電阻元件之電阻值；再於該已形成有 該圖案化電阻材料之電路板表面形成至少一絕緣層，並形 成有至少一圖案化第二線路層與貫穿該電路板之電鍍導通 孔（Plated through hole，PTH)，並藉由多數形成於該絕 緣層之導電盲孔以電性連接相鄰線路層與電阻電極。 經由上述製程，本發明另一之内嵌電阻元件之半導體 封裝基板，主要包括：一内層電路板，其具有一圖案化之 第一線路層，該第一線路層具有多數之電阻電極；至少一 圖案化電阻材料，係形成該内層電路板上，並電性導接該 電阻電極上；至少一圖案化第二線路層，係間隔一絕緣層 以堆疊於該已形成有圖案化電阻材料之電路板表面；複數 電鍍導通孔，係貫穿該絕緣層與線路層，以供電性導接相 關圖案化之線路層與電阻電極；以及複數個導電盲孔，係 形成於該絕緣層中以電性連接相鄰線路層與電阻電極。 藉由本發明之内嵌電阻元件之半導體封裝基板及其製 法，係先在基板内形成一具有一第一線路層之内層電路 板，該第一線路層具有多數之電阻電極，接著於該内層電 路板上形成圖案化電阻材料，俾使該電阻材料電性連接至 該電阻電極，以定義電阻元件之電阻值，亦即依照所使之 電阻材料材質及作用於該電阻電極間之電阻材料長度、面 積等尺寸以精確決定所需之電阻值，俾提昇電阻元件之電17307 全懋 .ptd Page 10 1224389 V. Description of Invention (6) The embodiment includes: First, an inner circuit board having a first circuit layer is provided, and the first circuit layer has a plurality of resistance electrodes, and then the inner layer A patterned resistance material is formed on the circuit board, and the resistance material is electrically connected to the resistance electrode to define the resistance value of the resistance element; and then at least one insulating layer is formed on the surface of the circuit board on which the patterned resistance material has been formed. And formed with at least one patterned second circuit layer and a plated through hole (PTH) through the circuit board, and electrically connects adjacent circuit layers through a majority of conductive blind holes formed in the insulation layer With resistance electrode. Through the above process, another semiconductor package substrate with a resistance element embedded therein according to the present invention mainly includes: an inner layer circuit board having a patterned first circuit layer having a plurality of resistance electrodes; at least one The patterned resistance material is formed on the inner circuit board and electrically connected to the resistance electrode; at least one patterned second circuit layer is separated by an insulating layer to be stacked on the circuit on which the patterned resistance material has been formed The surface of the board; a plurality of plated through-holes that pass through the insulating layer and the circuit layer to electrically connect the patterned circuit layer and the resistance electrode with power supply; and a plurality of conductive blind holes formed in the insulating layer for electrical connection Adjacent circuit layers and resistor electrodes. According to the semiconductor package substrate with embedded resistance element and the manufacturing method thereof, an inner layer circuit board having a first circuit layer is formed in the substrate, and the first circuit layer has a plurality of resistance electrodes, and then the inner layer circuit A patterned resistance material is formed on the board, and the resistance material is electrically connected to the resistance electrode to define the resistance value of the resistance element, that is, according to the material of the resistance material used and the length of the resistance material acting between the resistance electrodes, Area and other dimensions to accurately determine the required resistance value and increase the power of the resistance element
17307 全懋.ptd 第11頁 1224389 五、發明說明（7) 阻值準確度與製程之信賴性，同時透過多數之電鍍導通孔 或導電盲孔與線路層以電性導通至該電阻電極，以形成一 内嵌有電阻元件之多層封裝基板，因而提昇半導體裝置内 被動元件之佈設數量，並增加基板佈局靈活性，俾符合半 導體封裝件高積集度與微型化的封裝需求。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 請參閱第4A至第4G圖，為本發明之内嵌電阻元件之半 導體封裝基板製作方法示意圖。 如第4 A圖所示，首先，提供一内層電路板4 1，以於該 内層電路板41之表面形成有一導電金屬層42，該導電金屬 層4 2係可為銅金屬或其他具導電性之金屬所構成。 如第4B圖所示，藉由蝕刻製程以圖案化該導電金屬層 4 2以形成一第一線路層4 3。當然，該内層電路板4 1亦可為 一多層電路板，以在該多層電路板之表面絕緣層上形成有 第一線路層4 3，該第一線路層4 3中具有多數之電阻電極 4 3 0以供後續與電阻元件電性導接。 如第4 C圖所示，接著，於該内層電路板4 1上形成一電 阻材料44，該電阻材料44包含有厚膜（Thick film)及薄膜17307 全懋 .ptd Page 11 1224389 V. Description of the invention (7) Resistance accuracy and process reliability, meanwhile, through most of the plated through holes or conductive blind holes and circuit layers to electrically connect to the resistance electrode, Forming a multi-layer packaging substrate with embedded resistance elements, thereby increasing the number of passive components in a semiconductor device, and increasing the flexibility of the substrate layout, which meets the packaging requirements of semiconductor packages with high accumulation and miniaturization. [Embodiment] The following describes the embodiment of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. Please refer to FIGS. 4A to 4G, which are schematic diagrams of a method for manufacturing a semiconductor package substrate with an embedded resistance element according to the present invention. As shown in FIG. 4A, first, an inner layer circuit board 41 is provided. A conductive metal layer 42 is formed on the surface of the inner layer circuit board 41. The conductive metal layer 42 may be copper metal or other conductive materials. Made of metal. As shown in FIG. 4B, the conductive metal layer 42 is patterned by an etching process to form a first circuit layer 43. Of course, the inner circuit board 41 may also be a multi-layer circuit board, so that a first circuit layer 43 is formed on a surface insulation layer of the multi-layer circuit board, and the first circuit layer 43 has a plurality of resistance electrodes. 4 3 0 for subsequent electrical connection with the resistive element. As shown in FIG. 4C, a resistive material 44 is formed on the inner-layer circuit board 41. The resistive material 44 includes a thick film and a thin film.
17307 全懋.ptd 第12頁 122438917307 懋 .ptd Page 12 1224389
1224389 五、發明說明（9) 小，可依所使用之電阻材料材質及形成於電阻♦ 之電阻材料尺寸加決定。此外，該電阻材料可;，間相钜 覆盍於該電極上，可避免於後續製程及測試之高今或全部 環境易產生信賴性問題，而影響該阻層與電=遮、高^ 接關係。 之電性連 如第4E圖所示，接著於該已形成有該圖案 4 4之電路板表面形成至少一絕緣層4 5，該絕緣爲咆卩且枓料 係可為絕緣有機材料或陶瓷材料，如環氧樹脂p 4 5之枒質 r e s i η )、聚乙醯胺（p〇 ^ y i i de )、雙順丁 稀二駿 〇xy 氮阱（Bismaleimide triazine-based)樹脂，气‘亞胺 /: 維（Glass f iber )之複合材料等組成。而形成所$破螭織 4 5之方法包含有滾輪旋塗（1?〇1]^1_(：〇31:丨1^)、£迷绝緣層 (Punting)及疊層法（Laminati〇n)等方式，當^刷 層4 5並不限於僅由單一有機材料所形成，亦可^、，讀絕緣 材料層所疊合而成。 不同絶緣 如第4F圖所示，再藉由機械鑽孔或雷射鑽孔μ 於該絕緣層内形成有多數之盲孔45 〇，並使至少一寺^方式以 得以外露出該電阻電極4 3 0。 —盲孔4 5 〇 如第4G圖所示，於該絕緣層45之表面及盲孔45〇 ;、 一圖案化之第二線路層4 6與複數個導電盲孔4 5 1，俾开二成 形成導電盲孔4 5 1以電性連接該第二線路層4 6與電阻=由 430 ’以完成一内嵌（Embedded)有電阻元件之多層封=$ 板之製程。有關形成第二線路層係可以增層（β u丨1 ^ 術或疊層技術（Lamina t ion)形成，其可藉電鍍方式配 ' 3增1224389 V. Description of the invention (9) Small, it can be determined according to the size of the resistance material used and the size of the resistance material formed in the resistor. In addition, the resistance material can be covered on the electrode indirectly, which can avoid reliability problems in the current or all environments in subsequent processes and tests, which affects the resistance layer and the electrical connection. relationship. The electrical connection is as shown in FIG. 4E, and then at least an insulating layer 45 is formed on the surface of the circuit board on which the pattern 44 has been formed. The insulation is roaring and the material can be an insulating organic material or a ceramic material. , Such as epoxy resin p 4 5 (resi η), polyvinylamine (p〇 ^ yii de), bis cis butadiene oxo nitrogen trap (Bismaleimide triazine-based) resin, gas' imine / : Glass (fiber) composite materials. The method of forming all of the woven fabrics includes roller spin coating (1? 〇1) ^ 1 _ (: 〇31: 丨 1 ^), insulating layer (Punting), and lamination method (Laminati). ) And other methods, when the brush layer 45 is not limited to being formed of a single organic material, it can also be formed by stacking layers of insulating materials. Different insulation is shown in Figure 4F, and then by a mechanical drill Holes or laser drill holes μ form a large number of blind holes 45 ° in the insulating layer, and expose the resistor electrode 4 3 0 in at least one way. —Blind hole 4 5 0 as shown in FIG. 4G As shown, on the surface of the insulating layer 45 and the blind holes 45 °, a patterned second circuit layer 46 and a plurality of conductive blind holes 4 5 1 are opened to form conductive blind holes 4 5 1 for electrical properties. Connect the second circuit layer 46 to the resistance = 430 ′ to complete an embedded multilayered encapsulation with resistance elements = $ board. The formation of the second circuit layer can be increased (β u 丨 1 ^ Formation or lamination technology (Lamina ion), which can be equipped with '3
1224389 五、發明說明（ίο) 層技術形成該圖案化線路層，亦可藉由壓合鋼猪再以#刻 技術形成該圖案化線路層。當然，後續亦可繼續於該基板 表面持續進行絕緣層與線路層之增層，俾形成具更多線路 層之封裝基板。該基板可應用於覆晶式（F 1 i p Ch丨p)封裝 基板，亦或一般之打線式（W i r e b ο n d i n g )封裝基板。 請參閱第5A至第5H圖，為本發明之内嵌電阻元件之半 導體封裝基板另一實施例之製作方法剖面示意圖。其中， 5A至5E圖之製程係與4A至4E圖之製程相同，故在此不另為 文贅述。 ”、、 接著請參閱第5 F圖所示，俟經由雷射、蝕刻等方式圖 案化該第一線路層43上之電阻材料44，以配合先前至少一 第一線路層43中之多數電阻電極43 0，而於該基板中鑲埋 有電阻兀件後，再於該基板中進行機械或雷射鑽孔 (Dri 1 1 ing)以形成有貫穿通孔47。 …^ 5G圖所示，對該基板外側及通孔表面形成一如銅 層等導電^金屬層4 8，復以填充材料，例如環氧樹脂 (P Xy)專^緣材質或锡膏（Solder paste)等導電材質填 =ί 5二以形成一電鑛導通孔（PTH) 4 7 0，俾藉由該電鐘導 通孔4 7 0以雷地道拉zr 兔性V接至該電阻電極4 3 0。1224389 V. Description of the Invention (ίο) layer technology to form the patterned circuit layer, or the patterned circuit layer can be formed by pressing steel pigs and then using #etch technology. Of course, it is also possible to continue to add insulation layers and circuit layers on the surface of the substrate to form a package substrate with more circuit layers. The substrate can be applied to a flip-chip (F 1 i p Ch 丨 p) package substrate, or a general wire (W i r e b ο n d i n g) package substrate. Please refer to FIGS. 5A to 5H, which are schematic cross-sectional views illustrating a method for fabricating a semiconductor package substrate with embedded resistance elements according to another embodiment of the present invention. Among them, the process of 5A to 5E is the same as that of 4A to 4E, so it will not be described in detail here. Then, please refer to FIG. 5F, and pattern the resistive material 44 on the first circuit layer 43 by laser, etching, etc. to match most of the resistor electrodes in the at least one first circuit layer 43 previously. 43 0, and after the resistor element is embedded in the substrate, mechanical or laser drilling (Dri 1 1 ing) is performed in the substrate to form a through-hole 47. ^ A conductive metal layer 48 such as a copper layer is formed on the outside of the substrate and on the surface of the through hole, and then filled with a filler material, such as an epoxy (P Xy) edge material or a conductive paste (Solder paste). 52 to form a power slab via (PTH) 4 7 0, and then the zr rabbit V is pulled to the resistance electrode 4 3 0 through the electrical circuit via 4 7 0.
士口 A tJ 亡 ^圖所示，再於該絕緣層45内形成有多數之導電 二玖层1 ’教於該絕緣層4 5上形成有至少一圖案化之第二 1 e49’俾藉由該導電盲孔45 1以電性連接該第二線路 層4 9與電1¾¾4 π Λ 電極430’以完成一内欲（Embedded )有電阻元 曰、裝基板之製程。當然，後續亦可繼續於該基板As shown in the figure, a large number of conductive second layers 1 are formed in the insulating layer 45, and at least one patterned second 1 e49 'is formed on the insulating layer 45. The conductive blind hole 45 1 is electrically connected to the second circuit layer 49 and the electric 1¾¾4 π Λ electrode 430 ′ to complete an embedded process of mounting a resistor element and mounting a substrate. Of course, the subsequent can also continue on the substrate
__1 17307 全懋.ptd__1 17307 Full 懋 .ptd
第15頁 1224389 五、發明說明（11) 表面持續進行絕緣層與線路層之增層，俾形成具更多線路 層之封裝基板，且該基板亦可應用於覆晶式封裝基板或一 般之打線式封裝基板。 請參閱第4G及5H圖，係為應用本發明之内嵌電阻元件 之半導體封裝基板剖面示意圖。 該封裝基板係包括有一内層電路板4 1、至少一絕緣層 4 5、與絕緣層4 5交錯疊置之線路層4 6，4 9、至少一電阻材 料4 4、多數電性連接電阻材料之電阻電極4 3 0、多數電性 導接線路層與電阻電極之電鍍導通孔4 7 0、以及貫穿該些 絕緣層以電性連接該線路層與電阻電極之導電盲孔4 5 1。 該絕緣層4 5係可由有機材質、纖維強化有機材質或顆 料強化有機材質等所構成，例如環氧樹脂聚乙醯胺、順雙 丁稀二酸醯亞胺/三氮阱樹脂、氰酯等。該線路層4 6，4 9可 為一圖案化之銅層。 該電阻材料4 4包含有厚膜及薄膜電阻被動元件，而該 厚膜電阻材料係如銀粉或碳顆粒散布於樹脂中，及氧化釕 與玻璃粉末散布在一黏結劑塗佈再固化而形成；相對該薄 膜電阻材料係如鎳鉻、鎳碟、鎳錫、鉻Is、及氮化鈦合金 等，其可藉由濺鍍、電鍍或無電鍍等方式形成。而選擇使 用厚膜電阻元件或使用薄膜電阻元件，則是以製作多層基 板之製作成本與所製作電阻元件之電性精確度來決定。且 該半導體封裝基板所需電阻值之大小，可依所使用之電阻 材料材質及形成於電阻電極間相距之電阻材料尺寸加決 定。Page 15 1224389 V. Description of the invention (11) The surface is continuously increased by the insulation layer and the circuit layer to form a package substrate with more circuit layers, and the substrate can also be used for flip-chip package substrates or general wire bonding. Package substrate. Please refer to FIGS. 4G and 5H, which are schematic cross-sectional views of a semiconductor package substrate to which the embedded resistance element of the present invention is applied. The package substrate includes an inner layer circuit board 41, at least one insulating layer 4, 5, circuit layers interlaced with the insulating layer 4, 5, 4, 6, 9, at least one resistive material 4, 4, and most electrically connected resistive materials. The resistance electrode 430, most of the electrically conductive via layers and the plated through holes 470 of the resistance electrode, and the conductive blind holes 451 that penetrate the insulation layers to electrically connect the circuit layer and the resistance electrode. The insulating layer 4 5 may be composed of organic materials, fiber-reinforced organic materials, or particle-reinforced organic materials, such as epoxy polyacetamide, cis-bisbutyric acid imine / trinitrogen trap resin, and cyanate. Wait. The circuit layers 46, 49 can be a patterned copper layer. The resistive material 44 includes a thick-film and thin-film resistive passive element, and the thick-film resistive material is formed by, for example, silver powder or carbon particles dispersed in a resin, and ruthenium oxide and glass powder dispersed in an adhesive and then cured; In contrast, the thin film resistance material is nickel-chromium, nickel disk, nickel-tin, chromium Is, and titanium nitride alloy, etc., which can be formed by sputtering, electroplating, or electroless plating. The choice of using a thick-film resistor or a thin-film resistor is determined by the manufacturing cost of the multilayer substrate and the electrical accuracy of the resistor. In addition, the required resistance value of the semiconductor package substrate can be determined according to the material of the resistance material used and the size of the resistance material formed between the resistance electrodes.
17307 全懋.ptd 第16頁 1224389 五、發明說明 該電 形成有貫 層等導電 或錫膏等 孔以電性 透過 法，係將 電阻元件 電性功能 用面積， 藉由 法，係先 第一線路 成於該内 電阻值而 電極上， 極間之電 值，可避 賴性問題 昇電阻元 數之電鍍 電極，以 昇半導體 活性，俾 (12) 鍍導通孔 穿通孔， 金屬層， 導電材質 導接至該 本發明之 電阻元件 ’以提昇 ，並增加 以達半導 本發明之 在内層電 層具有多 層電路板 加以圖案 亦即依照 阻材料長 免於後續 ，而影響 件之電阻 導通孔或 形成一内 裝置内被 符合半導 47 0係利用機械或雷射鑽孔以在基板中 再對该基板外側及；g ^丨本 , 及通孔表面形成一如銅 復以填充材料，如夢翁士 植、文、S ， 如&乳树脂等絕緣材質 填滿通孔加以形成梭茲 電阻電極。u卑精由該電鍍導通 内嵌被動元件> $1 鑲嵌至基板中，i t肢裝基板及其製 該半導體裝晉力皁提供半導體裝置具備 基板線路^局翁破動元件之佈設數量與 體裝置輕薄姑r'舌性’且可縮減基板使 内嵌電阻元件之，=“ ° 路板形成—围半導體封裝基板及其製 數之電阻電極，、弟一線路層，且該 之表面後，再仿=ί至少一電阻材料形 化該電阻材料^際電性功能所需之 所使之電阻材料材：：：全部覆蓋於該 度、面積等尺寸r 、及作用於該電阻電 製程及測試之高=精，決定所需之電阻 該阻層與電極^㊆巧屬環境易產生信 值準確度與製程:性連接關係，俾提 導電盲孔與線路^ “賴性。同時透過多 嵌有電阻元件之:以電性導通至該電阻 動元件之佈設二層封裝基板，因而提 體封裝件高積隹 並增加基板佈局靈 、木度與微型化的封裝需17307 Quan 懋 .ptd Page 16 1224389 V. Description of the Invention The electrical formation of holes with conductive layers such as through layers or solder paste by the electrical transmission method is to use the area of the electrical function of the resistance element. The circuit is formed on the internal resistance value and the electrode, and the electric value between the electrodes can avoid the problem of resistance. Electroplated electrodes that increase the number of resistance elements to increase semiconductor activity. (12) plated through-holes, through-holes, metal layers, conductive materials It is connected to the resistance element of the present invention to enhance and increase the conductivity of the present invention. The inner layer of the present invention has a multi-layer circuit board for patterning, that is, the resistance material is prevented from being followed up, which affects the resistance vias of the device or Forming an inner device in accordance with the semiconducting 47 0 series using mechanical or laser drilling to the outside of the substrate and the substrate; g ^ this book, and the surface of the through hole is formed as copper compound filled with a material, such as dream Weng Shizhi, Wen, S, and other insulating materials such as & milk resin fill the through holes to form a shuttle resistance electrode. uBei Jing is embedded with passive components from the electroplating conduction > $ 1 embedded in the substrate, it is mounted on the substrate and the semiconductor device Jinli soap is provided to provide semiconductor devices with substrate lines ^ bureau Weng breaking components and the number of body devices Thin and thin, 'tongue' and can reduce the substrate to embed the resistance element, = "° circuit board formation-surrounding the semiconductor package substrate and its number of resistance electrodes, a circuit layer, and the surface, and then Imitation = At least one resistive material is used to shape the resistive material required for the electrical function of the resistive material: :: covers all the dimensions r, such as the degree and area, and acts on the resistive electrical process and test High = fine, determine the required resistance. This resistance layer and electrode are environmentally easy to generate signal accuracy and process: sexual connection relationship, and improve conductive blind holes and lines. At the same time, through the multiple embedded resistance elements: a two-layer package substrate is electrically connected to the resistance element, so the package has a high accumulation and increases the substrate layout flexibility, woodiness, and miniaturization.
17307 全懋.ptd 1224389 五、發明說明（13) 求。 先前圖式中僅以部分電阻材料表示，實際上該電阻材 料以及線路層之數目以及相對位置，及電阻材料所形成於 電路板之任一内層線路層，其非僅限於可形成於核心電路 板（C 〇 r e 1 a y e r )之線路層，係依實際製程所需而加以設計 並分佈於基板之疊層間，且該製程可實施於内層電路板之 單一側面或雙側面。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。17307 全懋 .ptd 1224389 V. Description of Invention (13). In the previous drawings, only a part of the resistance material is used. In fact, the number and relative position of the resistance material and the circuit layer, and any inner layer circuit layer formed by the resistance material on the circuit board are not limited to being formed on the core circuit board. The circuit layer of (Core 1 ayer) is designed and distributed between the stacks of the substrate according to the actual manufacturing process, and the process can be implemented on a single side or both sides of the inner circuit board. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.
17307 全懋.ptd 第18頁 1224389 圖式簡單說明 【圖式簡單說明】 第1圖係為習知在基板表面接置有被動元件之剖面示 意圖； 第2圖係為美國專利第6，1 0 8，2 1 2號案整合被動元件之 基板剖面示意圖； 第3圖係為美國專利第6，2 7 8，3 5 6號案整合被動元件之 基板剖面示意圖； 第4A圖至4G圖係為本發明之内嵌電阻元件之半導體封 裝基板製作方法剖面示意圖；以及 第5A圖至5H圖係本發明之内嵌電阻元件之半導體封裝 基板製作方法另一實施例之剖面示意圖。 1 0，2 0，3 0 基板 11,21 銲墊 12 拒銲劑層 13 錫膏 14 被動元件 15 間隙 22 電極 2 3 電性阻件 2 4 金屬凸塊 25 電子裝置 31,45 絕緣層 3 2 銅層17307 Quan 懋 .ptd Page 18 1224389 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a schematic cross-sectional view of a passive component known on the surface of a substrate; Figure 2 is a US patent No. 6,1 0 Schematic cross-sectional view of the substrate of the passive component integrated in the case No. 8, 2 1 2; Figure 3 is a schematic cross-sectional view of the substrate of the integrated passive component in the US Patent No. 6, 2 7 8, 3 5 6; Figures 4A to 4G are A schematic cross-sectional view of a method for manufacturing a semiconductor package substrate with an embedded resistance element according to the present invention; and FIGS. 5A to 5H are schematic cross-sectional views of another embodiment of a method for manufacturing a semiconductor package substrate with an embedded resistance element according to the present invention. 1 0, 2 0, 3 0 Substrate 11, 21 Solder pad 12 Solder resist layer 13 Solder paste 14 Passive component 15 Gap 22 Electrode 2 3 Electrical resistance 2 4 Metal bump 25 Electronic device 31, 45 Insulation layer 3 2 Copper Floor
17307 全懋.ptd 第19頁 122438917307 懋 .ptd page 19 1224389
圖式簡單說明 33 介 電 層 34 阻 層 41 内 層 電 路 板 42, 48 導 電 金 屬 層 43 第 一 線 路 層 44 電 阻 材 料 46, 49 第 二 線 路 層 47 普 貝 穿 通 孔 140 被 動 元 件 兩端 320 ii 刻 圖 像 430 電 阻 電 極 450 盲 孔 451 導 電 盲 孔 470 電 鍍 導 通 子LBrief description of the drawing 33 Dielectric layer 34 Resistive layer 41 Inner circuit board 42, 48 Conductive metal layer 43 First circuit layer 44 Resistive material 46, 49 Second circuit layer 47 Pope through-hole 140 Passive component ends 320 ii Like 430 resistance electrode 450 blind hole 451 conductive blind hole 470 plated conductor L
17307 全懋.ptd 第20頁17307 懋 .ptd Page 20
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8621748B2 (en) | 2007-02-06 | 2014-01-07 | Ibiden Co., Ltd. | Manufacturing method for a printed wiring board |
| TWI691242B (en) * | 2018-01-16 | 2020-04-11 | 大陸商鵬鼎控股（深圳）股份有限公司 | Embedded flexible circuit board and manufacturing method for same |
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2003
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8621748B2 (en) | 2007-02-06 | 2014-01-07 | Ibiden Co., Ltd. | Manufacturing method for a printed wiring board |
| TWI691242B (en) * | 2018-01-16 | 2020-04-11 | 大陸商鵬鼎控股（深圳）股份有限公司 | Embedded flexible circuit board and manufacturing method for same |
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