TW201013874A - Chip package - Google Patents

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Publication number
TW201013874A
TW201013874A TW097136967A TW97136967A TW201013874A TW 201013874 A TW201013874 A TW 201013874A TW 097136967 A TW097136967 A TW 097136967A TW 97136967 A TW97136967 A TW 97136967A TW 201013874 A TW201013874 A TW 201013874A
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TW
Taiwan
Prior art keywords
adhesive layer
wafer
circuit substrate
transition temperature
glass transition
Prior art date
Application number
TW097136967A
Other languages
Chinese (zh)
Inventor
Geng-Shin Shen
Wei David Wang
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW097136967A priority Critical patent/TW201013874A/en
Publication of TW201013874A publication Critical patent/TW201013874A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate.

Description

——------ϋϋ3-ί 19193-0P3twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種晶片封農（chip package)，且特 別是有關於一種可提高可靠度（reliability)與降低生產成 本的晶片封裝。 【先前技術】 近年來’逐漸發展出具有多値堆疊晶片（stacked chips )的曰曰片封裝。晶片封裝是將多個晶片堆疊（贫狀让） 於承載器（carrier)的上方且透過焊線（b〇ndingwire)或 凸塊（bump)電性連接至承载器，其中凸塊例如是金凸塊 (gold bump )、銅凸塊（copper bump )、聚合物凸塊（p〇lymer bump)或銲料凸塊（s〇ider bump)，而承載器例如是一印 刷電路板（print circuit board)或一導線架（iea(i-frame)。 一般來說，每一堆疊於承載器上的晶片可藉由膠合物（例 如膠帶或液態黏著劑）黏附於其他晶片或承載器上。特別 ❿ 疋富使用膠▼作為晶片接合製程.（die-bonding process) 或晶片堆疊製程（chip-stacking process)的膠合物時，具 有適當的大小及粘性的膠帶是貼附於晶片或承載器上。當 使用液態黏著劑作為晶片接合製程或晶片堆疊製程的膠合 物時，先將液態黏著劑配置於晶片上或承載器上，晶片與 承載器接合時或之後固化液態黏著劑。由於進行晶片接合 製程或晶片堆疊製程之前，必需先將膠帶裁剪成適當的大 小，因此此處所使用的膠帶不適於大量生產。此外，晶片 JU3-t I9193-0P3twf.doc/n ❹ 鲁 Π 〇 201013874 ^裝，可靠度會因液態黏著劑的厚度難以控制而受到影 i ^ Ϊ何將晶片封裝的可靠度提升以及降低晶片封 裝的生產成本，為亟待解決之問題。 【發明内容】 成本本t月提供—種晶片封裝，可提高可靠度與降低生產 路某Ϊ出—種晶片封裝，其包括〜具有—開口的線 著層以及—封裝:二。、；元件、-第-黏 斜於笛-士: 曰片有—第—主動面與一相 板上並雷2_第—ts ’其中第—晶片倒裝於線路基 板盘Γΐΐ接至線路基板。第—焊線電性連接至線路基 晶片的第一背面上。第1著層黏附於第 曰曰片的第-背面與元件之間，其中第 - Β階黏著層以及一第二㈣黏著層。第黏^層包括-第 附於第-日階黏著層黏 3产綠著^ 月 第二8階教著層黏附於第- 蓋第一晶片、元件、第-黏著層以及第—焊線:板且设 在本發明之-實施例中，上述之開口為1孔或一凹 之—實施射，上狀辑為1 弟一日曰片具有—第二背面與—相對於第二 面。第二晶片的筮—典而获忐筮^ ++, 的第一主動 曰片的第一月面稭由弟一黏著層黏附於第一晶片 6 201013 874 u3t 19193.0p3twf.doc/n 的第一背面。 在本發明之一實施例中，上述之晶片封裝更包括多條 第二焊線。第二焊線電性連接至第二晶片與線路基板。 在本發明之一實施例中，上述之元件為一熱散器。 在本發明之一實施例中，上述之第一焊線包括金線。 在本發明之一實施例中，上述之晶片封裝更包括一第 二黏著層。第二黏著層黏附於第一晶片的第一主動面與線 路基板之間。 ⑩ 在本發明之一實施例中，上述之第二黏著層包括一第 三B階黏著層以及一第四B階黏著層。第三B階黏著層黏 附於第一晶片的第一主動面上。第四B階黏著層黏附於第 三B階黏著層與線路基板之間。 在本發明之一實施例中，上述之第三B階黏著層的玻 璃轉化溫度與第四B階黏著層的玻璃轉化溫度實質上相 同。 在本發明之一實施例中，上述之第三B階黏著層的玻 φ 璃轉化溫度不同於第四B階黏著層的玻璃轉化溫度。 在本發明之一實施例中，上述之第一 B階黏著層的玻 璃轉化溫度與第二B階黏著層的玻璃轉化溫度實質上相 同。 在本發明之一實施例中，上述之第一 B階黏著層的玻 璃轉化溫度不同於第二B階黏著層的玻璃轉化溫度。 基於上述，由於本發明採用的第一黏著層具有呈半固 態狀的一第一 B階黏著層與一第二B階黏著層，因此第一 7 U〇3-t 19193-0P3twf.doc/n 201013874 黏著層的厚度容易控制。此外，因第―黏著層可直接形戍 於晶圓（wafer)之背面上，有利於大量生產。 *為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 立圖1為本發明之第一實施例之一種晶片封裝的剖面示 忍圖。請參考圖1，在本實施例中，晶片封裝1〇〇包括一 f有一開口 110a的線路基板110、一第一晶片12〇、多條 弟知線130、一元件140、一第一黏著層丨5〇以及一封^ 膠體160。第一晶片12〇具有一第一主動面12〇&與一相對 於第一主動面120a的第一背面120b，其中第一晶片12〇 倒裝於線路基板110並電性連接至線路基板11〇。第一焊 線130電性連接至線路基板110與第一晶片12〇，其中每 —第一焊線130穿過線路基板no的開口 11〇a。元件 配置於第一晶片120的第一背面120b上。第一黏著層150 鞑附於第一晶片120的第一背面120b與元件140之間，其 中第一黏著層150包括一第一 B階黏著層15〇a以及一第 階黏著層150b。第一 B階黏著層150a黏附於第一晶 片120的第一背面120b上。第二B階黏著層15〇b黏附於 第一 B階黏著層15〇a與元件140之間。封裝膠體16〇配 置於線路基板110上且覆蓋第一晶片120、元件140、第一 黏著層150以及第一焊線130。 在本實施例中，線路基板110可為一電路板，例如是 u03-t 19193-0P3twf.doc/n 201013874 FR-4基板、FR-5基板、BT基板或其他適合的基板。 請再參考圖1 ’線路基板110具有多個第一連接墊 112，且這些第一連接墊in配置於線路基板11〇的一表 面’其中第一晶片120具有多個第一焊墊122。這些第一 連接墊112配置於線路基板11〇的開口 11〇a的周圍，且線 路基板110的開口 ll〇a暴露出這些第一焊墊122。這些第 一連接墊112分別藉由這些第一焊線130電性連接至這些 第一焊墊122。在本實施例中，第一焊線13〇為打線接合 ® 製程所形成的金線。在此必須說明的是，線路基板110的 開口 110可以是一貫孔（請參考圖5 A )、一凹口（請參考 圖5B)或其他適合的形態。 在本實施例中’元件140為一散熱器。為了提升散熱 效果’封裝膠體160可僅覆蓋部份的元件140 (散熱器）， 換句話說’元件140 (散熱器）的部份表面是暴露於封裝 膠體160外。在其他實施例中，封裝膠體16〇亦可完全覆 蓋元件140 (散熱器）。 ❷ 請再參考圖1 ’封裝膠體160填入線路基板11()的開 口 110a並包覆這些第一焊線130 ’以便保護這些第一焊線 130避免受到毁壞。 在本實施例中，配置於第一晶片120的第一背面i20b 上的一第一黏著層150可透過以下的步驟進行製作。首 先，提供一晶圓’此晶圓上具有多個成陣列排列的第一晶 片120。接著，形成一第一雙階黏著層於第一晶片12〇的 第一背面120b上’藉由加熱或紫外線照射使得第一雙階黏————ϋϋ3-ί 19193-0P3twf.doc/n IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a chip package, and particularly to a A chip package that improves reliability and reduces production costs. [Prior Art] In recent years, a wafer package having a plurality of stacked chips has been gradually developed. The chip package is to stack a plurality of wafers (poor) over the carrier and electrically connect to the carrier through a bonding wire or a bump, wherein the bump is, for example, a gold bump. A gold bump, a copper bump, a polymer bump or a solder bump, and the carrier is, for example, a printed circuit board or A lead frame (iea (i-frame). Generally, each wafer stacked on a carrier can be adhered to other wafers or carriers by a glue (such as a tape or a liquid adhesive). When using glue ▼ as a die for a die-bonding process or a chip-stacking process, a tape of appropriate size and tack is attached to the wafer or carrier. When the adhesive is used as a bonding process for the wafer bonding process or the wafer stacking process, the liquid adhesive is first disposed on the wafer or on the carrier, and the liquid adhesive is cured when the wafer is bonded to the carrier or after. Before the wafer stacking process, the tape must be cut to the appropriate size, so the tape used here is not suitable for mass production. In addition, the chip JU3-t I9193-0P3twf.doc/n Π LuΠ 〇201013874 ^, reliability The problem is that the reliability of the liquid adhesive is difficult to control, and the reliability of the chip package is improved and the production cost of the chip package is lowered, which is an urgent problem to be solved. [Explanation] The cost is provided in this month. , can improve the reliability and reduce the production road - a kind of chip package, including ~ with an open line layer and - package: two.,; components, - the first - slanted to the flute -: - a first active surface and a phase plate and a second ts - ts ' wherein the first wafer is flip-chip mounted on the circuit substrate to the circuit substrate. The first bonding wire is electrically connected to the first back surface of the wiring substrate The first layer adheres between the first back surface of the second film and the element, wherein the first-order adhesive layer and a second (four) adhesive layer. The first adhesive layer includes - the first-day adhesive layer Sticky 3 production green ^ ^ second 8th order The layer is adhered to the first cover of the first wafer, the element, the first adhesive layer, and the first bonding wire: and is disposed in the embodiment of the present invention, wherein the opening is 1 hole or a concave surface The first piece of the first active piece is the first moon piece of the second wafer, and the second surface is opposite to the second side. An adhesive layer adheres to the first back of the first wafer 6 201013 874 u3t 19193.0p3twf.doc/n. In an embodiment of the invention, the chip package further includes a plurality of second bonding wires. The second bonding wire is electrically connected to the second wafer and the circuit substrate. In an embodiment of the invention, the component is a heat spreader. In an embodiment of the invention, the first bonding wire comprises a gold wire. In an embodiment of the invention, the chip package further includes a second adhesive layer. The second adhesive layer is adhered between the first active surface of the first wafer and the wiring substrate. In one embodiment of the invention, the second adhesive layer comprises a third B-stage adhesive layer and a fourth B-stage adhesive layer. A third B-stage adhesive layer is adhered to the first active surface of the first wafer. The fourth B-stage adhesive layer is adhered between the third B-stage adhesive layer and the circuit substrate. In one embodiment of the invention, the glass transition temperature of the third B-stage adhesive layer is substantially the same as the glass transition temperature of the fourth B-stage adhesive layer. In one embodiment of the invention, the glass transition temperature of the third B-stage adhesive layer is different from the glass transition temperature of the fourth B-stage adhesive layer. In one embodiment of the invention, the glass transition temperature of the first B-stage adhesive layer is substantially the same as the glass transition temperature of the second B-stage adhesive layer. In one embodiment of the invention, the glass transition temperature of the first B-stage adhesive layer is different from the glass transition temperature of the second B-stage adhesive layer. Based on the above, since the first adhesive layer used in the present invention has a first B-stage adhesive layer and a second B-stage adhesive layer in a semi-solid state, the first 7 U〇3-t 19193-0P3twf.doc/n 201013874 The thickness of the adhesive layer is easy to control. In addition, since the first adhesive layer can be directly formed on the back side of the wafer, it is advantageous for mass production. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] Fig. 1 is a cross-sectional view showing a wafer package of a first embodiment of the present invention. Referring to FIG. 1, in the embodiment, the chip package 1 includes a circuit substrate 110 having an opening 110a, a first wafer 12, a plurality of lines 130, an element 140, and a first adhesive layer.丨5〇 and a ^ colloid 160. The first wafer 12 has a first active surface 12A and a first back surface 120b opposite to the first active surface 120a, wherein the first wafer 12 is flip-chip mounted on the circuit substrate 110 and electrically connected to the circuit substrate 11 Hey. The first bonding wire 130 is electrically connected to the circuit substrate 110 and the first wafer 12A, wherein each of the first bonding wires 130 passes through the opening 11〇a of the circuit substrate no. The component is disposed on the first back surface 120b of the first wafer 120. The first adhesive layer 150 is attached between the first back surface 120b of the first wafer 120 and the element 140. The first adhesive layer 150 includes a first B-stage adhesive layer 15A and a first-order adhesive layer 150b. The first B-stage adhesive layer 150a is adhered to the first back surface 120b of the first wafer 120. The second B-stage adhesive layer 15Ab is adhered between the first B-stage adhesive layer 15A and the element 140. The encapsulant 16 is disposed on the circuit substrate 110 and covers the first wafer 120, the component 140, the first adhesive layer 150, and the first bonding wire 130. In this embodiment, the circuit substrate 110 can be a circuit board, such as a u03-t 19193-0P3twf.doc/n 201013874 FR-4 substrate, an FR-5 substrate, a BT substrate, or other suitable substrate. Referring again to FIG. 1, the circuit substrate 110 has a plurality of first connection pads 112, and the first connection pads in are disposed on a surface of the circuit substrate 11A, wherein the first wafer 120 has a plurality of first pads 122. The first connection pads 112 are disposed around the openings 11A of the circuit substrate 11A, and the openings 141a of the circuit substrate 110 expose the first pads 122. The first connection pads 112 are electrically connected to the first pads 122 by the first bonding wires 130, respectively. In the present embodiment, the first bonding wire 13 is a gold wire formed by a wire bonding process. It must be noted here that the opening 110 of the circuit substrate 110 may be a uniform hole (please refer to Fig. 5A), a notch (refer to Fig. 5B) or other suitable configuration. In this embodiment, the element 140 is a heat sink. In order to enhance the heat dissipation effect, the encapsulant 160 may cover only a portion of the component 140 (heat sink). In other words, a portion of the surface of the component 140 (heat sink) is exposed outside the encapsulant 160. In other embodiments, the encapsulant 16 can also completely cover the component 140 (heat sink). ❷ Referring again to FIG. 1 ' the encapsulant 160 fills the opening 110a of the circuit substrate 11 () and covers the first bonding wires 130' to protect the first bonding wires 130 from damage. In this embodiment, a first adhesive layer 150 disposed on the first back surface i20b of the first wafer 120 can be fabricated through the following steps. First, a wafer is provided. The wafer has a plurality of first wafers 120 arranged in an array. Then, a first double-step adhesive layer is formed on the first back surface 120b of the first wafer 12'. The first double-step adhesive is made by heating or ultraviolet irradiation.

Ju3-t 19I93-0P3twf.doc/n 201013874 著層被部份固化而形成第一 B階黏著層ls〇a。之後，形成 -第二雙階黏著層於第—B階黏著層㈣上。最後，藉 由加熱或紫外線照射使得第二雙階黏著層被部份固化而形 成第二B階黏著層i5〇b。此時，第—B階黏著層·與 第二B階黏著層150b便被形成於晶圓的背面上。當晶圓 ，切割（單體化）之後’即可得到第一背面隱上形成有 第一黏著層150的第一晶片12〇。因此，具有第一 B階黏 著f 15〇a與第二B階黏著層150b的第一黏著層15〇有利 於i產。此外，第一 B階黏著層i5〇a與第二B階黏著層 150b的开)成方式可以藉由旋轉塗佈法、印刷法或其他適合 的方式。 ’ 在第二B階黏著層150b被部份固化之同時，第一 b 階黏著層150a也可再進一步被固化而具有較佳的機械強 度，以保持第一晶片120與元件140之間的間距（gap)。 此時，第一 B階黏著層15〇a可為部份固化或是全部固化 來提供足夠的支撐力，而第二B階黏著層15〇b可呈現柔 φ 軟且具黏性的狀態。Ju3-t 19I93-0P3twf.doc/n 201013874 The layer is partially cured to form the first B-stage adhesive layer ls〇a. Thereafter, a second second-order adhesive layer is formed on the first-B-stage adhesive layer (four). Finally, the second double-step adhesive layer is partially cured by heating or ultraviolet irradiation to form a second B-stage adhesive layer i5〇b. At this time, the first-stage B-adhesive layer and the second B-stage adhesive layer 150b are formed on the back surface of the wafer. When the wafer is diced (singulated), the first wafer 12A on which the first adhesive layer 150 is formed on the first back surface is obtained. Therefore, the first adhesive layer 15 having the first B-stage adhesive f 15〇a and the second B-stage adhesive layer 150b is advantageous for the production. Further, the opening of the first B-stage adhesive layer i5〇a and the second B-stage adhesive layer 150b may be by spin coating, printing or other suitable means. While the second B-stage adhesive layer 150b is partially cured, the first b-stage adhesive layer 150a can be further cured to have better mechanical strength to maintain the spacing between the first wafer 120 and the component 140. (gap). At this time, the first B-stage adhesive layer 15〇a may provide sufficient support for partial curing or full curing, and the second B-stage adhesive layer 15〇b may exhibit a soft and viscous state.

在本實施例中’當元件140貼附於第一晶片12〇或封 裂膠體160覆蓋元件140之後，第一 B階黏著層150a與 第二B階黏著層150b會被完全固化。舉例而言，第一 b 階黏著層150a與第二B階黏著層150b可為ABLESTIK的 8〇〇8或8008HT，且其玻璃轉換溫度大約介於攝氏八十度 與攝氏三百度之間。此外，第一 B階黏著層150a與第二BIn the present embodiment, after the element 140 is attached to the first wafer 12 or the sealing colloid 160 covers the element 140, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b are completely cured. For example, the first b-stage adhesive layer 150a and the second B-stage adhesive layer 150b may be ABLESTIK's 8〇〇8 or 8008HT, and the glass transition temperature is approximately between eighty degrees Celsius and three degrees Celsius. In addition, the first B-stage adhesive layer 150a and the second B

階黏著層 150b 亦可為 ABLESTIK 的 6200、6201、6202C 201013874 'V 03-t 19193-0P3twf.doc/n 或 HITACHI Chemical CO.，Ltd.提供的 SA-200-6、 SA-200-10’且其玻璃轉換溫度大約介於攝氏負四十度與攝 氏一百五十度之間。第一 B階黏著層150a的玻璃轉換溫 度可大於、等於或小於第二B階黏著層15〇b的玻璃轉換 溫度。此外，例如可將一些導電粒子（如銀粒子、銅粒子 及金粒子）攙雜於第一；B階黏著層15〇a與第二B階黏著 層150b中以增加導電性。 請再參考圖1，晶片封裝1〇〇更可包括一第二黏著層 ❹ 170，其貼附於第一晶片120的第一主動面i2〇a與線路基 板no之間。換句話說，第一晶片120藉由第二黏著層17〇 貼附於線路基板110。 圖2為本發明之第二實施例之一種晶片封裝的剖面示 思圖。請同時參考圖2與圖1，在本實施例中，圖2之晶 片封裳200與圖1之晶片封裝1〇〇相似，惟二者主要差異 之處在於：圖2之晶片封裝200中的第二黏著層170包括 一黏附於第一晶片120的第一主動面12〇a上的第三b階 ❹ 黏著層17如以及一黏附於第三B階黏著層170a與鍊路基 板110之間的第四B階黏著層170b。在此必須說明的是， 第三B階黏著層170a與第四B階黏著層170b可以藉由旋 轉塗佈法、印刷法或其他適合的方式形成於第一晶片12〇 的第一主動面120a上或線路基板11〇上。 在本實施例中’當第一晶片120被貼附於線路基板110 或封裝膠體160覆蓋第一晶片120之後，第三b階黏著層 170a與第四B階黏著層170b會被完全固化。第三b階黏 11 u03-t 19193-0P3twf.doc/n 201013874 著層170a與第四B階黏著層170b可為ABLESTIK的8008 或8008HT，且其玻璃轉換溫度大約介於攝氏八十度與攝 氏三百度之間。此外，第三B階黏著層170a與第四B階 黏著層 170b 亦可為 ABLESTIK 的 6200、6201、6202C 或 HITACHI Chemical CO., Ltd.提供的 SA-200-6、 SA-200-10’且其玻璃轉換溫度大約介於攝氏負四十度與攝 氏一百五十度之間。第三B階黏著層17〇a的玻璃轉換溫 度可大於、等於或小於第四B階黏著層17〇b的玻璃轉換 ® 溫度。此外，例如可將一些導電粒子（如銀粒子、銅粒子 及金粒子）攙雜於第三B階黏著層17〇a與第四B階黏著 層l7〇b中以增加導電性。 一圖3與圖4為本發明之第三實施例之晶片封裝的剖面 示意圖。請同時參考圖3與圖丨，在本實施例中，圖3之 晶片封裝300與圖1之晶片封裝1〇〇相似，惟二者主要差 異之處在於：圖3之元件14〇為一第二晶片。此外，請同 時參考圖4與圖2，在本實施例中，圖4之晶片封震働 ❹ 與圖2之晶片封裳勘相似，惟二者主要差異之處在於： 圖4之元件140為一第二晶片。 ' 明同參考圖3與圖4，線路基板11〇具有多個第一 連接塾112與多個第二連接塾114，其中第一連接塾ιΐ2 配置於線路基板110的一表面，而第二連接塾114則配置 於„ U〇的另—表面。元件140 (第二晶片）具有 -弟-背面1働與-相對於第二背面·的第二主動面 140a凡件140 (第一晶片）的第二背面ι働藉由第—黏 12 ^3-t 19193-0P3twf.d〇c/n 201013874 y uo貼附於第一晶片12〇的第一背面^爲。元件刚 (弟二晶片）包括多個配置於第二主動面⑽&的第二焊塾 一此外’ a曰片封震300更包括多條第二焊線180 ’這些 ft焊線180電性連接至元件⑽（第二晶片）的第二焊 墊=2與線路基板i㈣第二連接墊114。在此必須說明 疋元件14〇亦可為一被動元件，其例如是一電容器、 一電阻器或一電感器。The step adhesive layer 150b may also be SA2000-1, SA-200-10' provided by ABLESTIK, 6200, 6201, 6202C 201013874 'V 03-t 19193-0P3twf.doc/n or HITACHI Chemical CO., Ltd. The glass transition temperature is approximately between minus 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the first B-stage adhesive layer 150a may be greater than, equal to, or less than the glass transition temperature of the second B-stage adhesive layer 15〇b. Further, for example, some conductive particles (e.g., silver particles, copper particles, and gold particles) may be doped in the first; the B-stage adhesive layer 15A and the second B-stage adhesive layer 150b may be added to increase conductivity. Referring again to FIG. 1, the chip package 1b further includes a second adhesive layer ❹ 170 attached between the first active surface i2〇a of the first wafer 120 and the line substrate no. In other words, the first wafer 120 is attached to the wiring substrate 110 by the second adhesive layer 17'. Figure 2 is a cross-sectional view showing a chip package of a second embodiment of the present invention. Referring to FIG. 2 and FIG. 1 simultaneously, in the present embodiment, the wafer package 200 of FIG. 2 is similar to the chip package 1 of FIG. 1, but the main difference between the two is: in the chip package 200 of FIG. The second adhesive layer 170 includes a third b-stage adhesive layer 17 adhered to the first active surface 12A of the first wafer 120, and adhered between the third B-stage adhesive layer 170a and the link substrate 110. The fourth B-stage adhesive layer 170b. It should be noted that the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b may be formed on the first active surface 120a of the first wafer 12A by spin coating, printing or other suitable manner. On or on the circuit substrate 11 〇. In the present embodiment, after the first wafer 120 is attached to the wiring substrate 110 or the encapsulant 160 covers the first wafer 120, the third b-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b are completely cured. The third b-th order 11 u03-t 19193-0P3twf.doc/n 201013874 The layer 170a and the fourth B-stage adhesive layer 170b can be ABLESTIK 8008 or 8008HT, and the glass transition temperature is about 80 degrees Celsius and Celsius. Between three Baidu. In addition, the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b may also be SA200200, SA-200-10' provided by ABLESTIK 6200, 6201, 6202C or HITACHI Chemical CO., Ltd. The glass transition temperature is approximately between minus 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the third B-stage adhesive layer 17〇a may be greater than, equal to, or less than the glass transition temperature of the fourth B-stage adhesive layer 17〇b. Further, for example, some conductive particles (e.g., silver particles, copper particles, and gold particles) may be doped in the third B-stage adhesive layer 17A and the fourth B-stage adhesive layer 17b to increase conductivity. 3 and 4 are schematic cross-sectional views showing a wafer package in accordance with a third embodiment of the present invention. Referring to FIG. 3 and FIG. 3 simultaneously, in the embodiment, the chip package 300 of FIG. 3 is similar to the chip package 1 of FIG. 1, but the main difference between the two is that the component 14 of FIG. Two wafers. In addition, please refer to FIG. 4 and FIG. 2 at the same time. In this embodiment, the wafer seal of FIG. 4 is similar to the wafer seal of FIG. 2, but the main difference is that: the component 140 of FIG. 4 is A second wafer. Referring to FIG. 3 and FIG. 4, the circuit substrate 11A has a plurality of first connection ports 112 and a plurality of second connection ports 114, wherein the first connection port 2 is disposed on a surface of the circuit substrate 110, and the second connection The 塾114 is disposed on the other surface of the 〇U. The element 140 (the second wafer) has a 弟-back 1働 and a second active surface 140a relative to the second back surface 140a (the first wafer) The second back surface is attached to the first back surface of the first wafer 12 by the first adhesion 12 ^3-t 19193-0P3twf.d〇c/n 201013874 y uo. The element just includes the second chip a plurality of second soldering pads disposed on the second active surface (10) & a further comprising a plurality of second bonding wires 180'. The ft bonding wires 180 are electrically connected to the component (10) (second wafer) The second pad = 2 and the circuit substrate i (four) the second connection pad 114. It must be noted here that the 疋 element 14 〇 can also be a passive component, such as a capacitor, a resistor or an inductor.

雖’、、;、本發明已以實施例揭露如上，然其並非用以限定 本發月任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範㈣，當可作些許之更動與潤飾，故本 發月之保ft圍當視後附之巾請專利範圍所界定者為準。 【圖式簡單說明】 圖1為本發明之第一實施例之一種晶片封裝的剖面示 意圖。 圖2為本發明之第二實施例之一種晶片封裝的剖面示 意圖。 圖3與圖4為本發明之第三實施例之晶片封裝的剖面 示意圖。 一圖5A與圖5B為本發明之不同實施例之線路基板的上 視不意圖。 【主要元件符號說明】 100、200、300、400 :晶片封裝 13 ^J3-t 19193-0P3twf.doc/n 110 :線路基板 110a :開口 112 :第一連接墊 114 :第二連接墊 120 :第一晶片 120a :第一主動面 120b :第一背面 122 :第一焊墊 φ 130 :第一焊線 140 :元件 140a :第二主動面 140b :第二背面 142 :第二焊墊 150 :第一黏著層 150a :第一 B階黏著層 150b :第二B階黏著層 ❹ 160 :封裝膠體 170 :第二黏著層 170a :第三B階黏著層 170b :第四B階黏著層 180 :第二焊線 14Although the present invention has been disclosed in the above embodiments, it is not intended to limit the ordinary knowledge in the technical field of the present invention, and may be modified without departing from the spirit and scope of the present invention. And retouching, so the original warranty of the month of the ft. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a wafer package of a first embodiment of the present invention. Figure 2 is a cross-sectional view showing a wafer package of a second embodiment of the present invention. 3 and 4 are schematic cross-sectional views showing a wafer package of a third embodiment of the present invention. 5A and 5B are top views of a circuit substrate according to different embodiments of the present invention. [Description of main component symbols] 100, 200, 300, 400: chip package 13 ^ J3-t 19193-0P3twf.doc / n 110: circuit substrate 110a: opening 112: first connection pad 114: second connection pad 120: a wafer 120a: a first active surface 120b: a first back surface 122: a first bonding pad φ130: a first bonding wire 140: an element 140a: a second active surface 140b: a second back surface 142: a second bonding pad 150: first Adhesive layer 150a: first B-stage adhesive layer 150b: second B-stage adhesive layer ❹ 160: encapsulant 170: second adhesive layer 170a: third B-stage adhesive layer 170b: fourth B-stage adhesive layer 180: second solder Line 14

Claims (1)

»3-t 19193-0P3twf.doc/n 201013874 十、申請專利範圍： ι· 一種晶片封裝，包括： 一線路基板，具有一開口； 第一晶片，具有一第一主動面與一相對於該第一主 動面的第一背面，其中該第一晶片倒裝於該 ^ 性連接至鱗板； 4基板並電 夕條第一焊線，電性連接至該線路基板與該第一曰 片，其中各該第一烊線穿過該線路基板的該開口；曰曰 一元件，配置於該第一晶片的該第一背面上； 元件:黏附於該第一晶片的該第-背面與該 兀件之間’其中该弟一黏著層包括： -第-Β階黏著層，黏附於該第—晶片的 月面上；以及 π 二第二Β難著層，_於該第—Β階 該兀件之間；以及 e，、 一封裝膠體，配置於該線路基板上且覆 片、該元件、該第1著層以及該些第—焊線^第—晶 咖1減叫轉，其中_ 件為！:第如二申!^第1項所述之晶片封裝’其中該元 的第-片有―第二背面與—相對於該第二背面 的苐一主動面’該第二晶片的該第二背 層黏附於該第―晶片的該第-背面。 ^ 侔第4」=f㈣3項麟之^封裝，更包括多 條第-祕电性連接至該第二晶片與該線路基板。 15 201013874 19193-0P3twf.doc/n 5. 如申請專利範圍第1項所述之晶片封裝，其中該元 件為一熱散器。 6. 如申請專利範圍第1項所述之晶片封裝，其中該些 第一焊線包括金線。 7. 如申請專利範圍第1項所述之晶片封裝，更包括一 第二黏著層，黏附於該第一晶片的該第一主動面與該線路 基板之間。 8. 如申請專利範圍第7項所述之晶片封裝，其中該第 ❿ 二黏著層包括： 一第三B階黏著層，黏附於該第一晶片的該第一主動 面上；以及 一第四B階黏著層，黏附於該第三B階黏著層與該線 路基板之間。 9. 如申請專利範圍第8項所述之晶片封裝，其中該第 三B階黏著層的玻璃轉化溫度與該第四B階黏著層的玻璃 轉化溫度實質上相同。 _ 10.如申請專利範圍第8項所逑之晶片封裝，其中該 第三B階黏著層的玻璃轉化溫度不ίή於該第四B階黏著層 的玻璃轉化溫度。 11. 如申請專利範圍第1項所述之晶片封裝，其中該 第一 Β階黏著層的玻璃轉化溫度與該第二Β階黏著層的玻 璃轉化溫度實質上相同。 12. 如申請專利範圍第1項所述之晶片封裝，其中該 第一 Β階黏著層的玻璃轉化溫度不同於該第二Β階黏著層 的玻璃轉化溫度。 16»3-t 19193-0P3twf.doc/n 201013874 X. Patent application scope: ι· A chip package comprising: a circuit substrate having an opening; the first wafer having a first active surface and a first surface a first back surface of the active surface, wherein the first wafer is flip-chip mounted on the slat; the substrate is electrically connected to the circuit substrate and the first cymbal, wherein Each of the first turns passes through the opening of the circuit substrate; a first component is disposed on the first back surface of the first wafer; and an element: the first back surface adhered to the first wafer and the component Between the two layers of the adhesive layer includes: - a first - order adhesive layer, adhered to the moon surface of the first wafer; and a second Β second hard layer, _ the first - And e, an encapsulant, disposed on the circuit substrate, and the cover sheet, the component, the first layer, and the first-bonding wire--the crystal coffee 1 are reduced, wherein the ! The chip package of the first item, wherein the first piece of the element has a second back surface and a second active surface of the second back surface The back layer is adhered to the first back surface of the first wafer. ^ 侔 4" = f (4) 3 items of the Lin ^ package, including a plurality of first-secret connection to the second wafer and the circuit substrate. 5. The chip package of claim 1, wherein the component is a heat spreader. 6. The wafer package of claim 1, wherein the first bonding wires comprise gold wires. 7. The wafer package of claim 1, further comprising a second adhesive layer adhered between the first active surface of the first wafer and the wiring substrate. 8. The wafer package of claim 7, wherein the second adhesive layer comprises: a third B-stage adhesive layer adhered to the first active surface of the first wafer; and a fourth The B-stage adhesive layer is adhered between the third B-stage adhesive layer and the circuit substrate. 9. The wafer package of claim 8, wherein the third B-stage adhesive layer has a glass transition temperature substantially the same as a glass transition temperature of the fourth B-stage adhesive layer. 10. The wafer package of claim 8, wherein the glass transition temperature of the third B-stage adhesive layer is not dependent on the glass transition temperature of the fourth B-stage adhesive layer. 11. The wafer package of claim 1, wherein the glass transition temperature of the first layer of the adhesive layer is substantially the same as the glass transition temperature of the second layer of the adhesive layer. 12. The wafer package of claim 1, wherein the glass transition temperature of the first layer of the adhesive layer is different from the glass transition temperature of the second layer of the adhesive layer. 16
TW097136967A 2008-09-25 2008-09-25 Chip package TW201013874A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158763A (en) * 2015-05-13 2016-11-23 南茂科技股份有限公司 Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method
CN114267669A (en) * 2020-09-16 2022-04-01 美光科技公司 Edge-band notched substrate packages and associated systems and methods

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158763A (en) * 2015-05-13 2016-11-23 南茂科技股份有限公司 Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method
TWI567880B (en) * 2015-05-13 2017-01-21 南茂科技股份有限公司 Film packaging substrate, chip on film package and packaging method thereof
CN106158763B (en) * 2015-05-13 2018-09-07 南茂科技股份有限公司 Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method
CN114267669A (en) * 2020-09-16 2022-04-01 美光科技公司 Edge-band notched substrate packages and associated systems and methods
US11848299B2 (en) 2020-09-16 2023-12-19 Micron Technology, Inc. Edge-notched substrate packaging and associated systems and methods

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