201013888 ~------008-t 19193-0P4twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝（chippackage)，且特 別是有關於一種可提高可靠度（reliability)與降低生產成 本的晶片封裝。 【先前技術】 近年來，逐漸發展出具有多個堆疊晶片（stacked ❹ chiPs)的晶片封裝。晶片封裝是將多個晶片堆疊（stack) 於承載器（carrier)的上方且透過焊線（b〇ndingwke)或 凸塊（bump)電性連接至承載器，其中凸塊例如是金凸塊 (gold bump )、銅凸塊（copper bump )、聚合物凸塊（p〇lymer bump)或銲料凸塊（s〇ider bump)，而承載器例如是一印 刷電路板（print circuit board)或一導線架（lead_fram〇。 -般來說，每-堆疊於承載器上的晶片可藉由膝合物（例 如膠帶或液態黏著劑）黏附於其他晶片或承載器上。特別 ❹ 是’當使用膠帶作為晶片接合製程（die-bondling process) 或曰日片堆疊製程（chip-stacking process )的膠合物時，具 有適當大乂'及枯性的膠帶是貼附於晶片或承載器上。當使 用液祕著劑作為晶片接合製程或晶片堆疊製程的膠合物 時，先將液態黏著劑配置於晶片上或承載器上，晶片^承 載器接合時^之後固化液態黏著劑。由於進行晶片接^製 程或晶片堆疊製程之前’必需先將膠帶裁剪成適當的大 小，因此此處所使用的膠帶不適於大量生產。此外:晶片 201013888 ^ —- «J08-t 19193-0P4twf.doc/n 靠二液，著劑的厚度難以控制而受到影 裝的生產成本待:度提升以及降低晶片封 【發明内容】 成本本發供-種晶片域，可提高可纽與降低生產 -曰片封裝，其包括-線路基板、-第 裝膠體。第—晶片且有 者層以及一封 面的第-背面以及多個配置於第—主於第主動 Φ筮一曰μΛΑ- 弟主動面的第—焊墊，其 4的弟-月面軸於線路基板上，且第一 性連接至線路基板。第一焊曰 晶片Μ Μ -: 綠電連接至線路基板與第一 魯 =d二於第—晶片的第-主動面的上 =第一黏者層黏附於第—晶片的第-主動面與元件之 ;、且未覆蓋第-料。第—轉層包括— 二 =二】Γ著層。第一 β階黏著層黏附於第-： SC : 第二B階黏著層黏附於第一 B階 兀π T膠體配置於線路基板上且覆蓋第 日日片、兀件、第一黏著層以及第—谭線。 蓋乐 在本發明之一實施例中 —連接塾。第-連接塾透&一上焊m板具有多個第 ^,,.nn &谇線電性連接至第一焊墊。 晶片 第τ巾，上叙科為-第二 第-明片具有-紅背面與—相對於第二背面的第 JLJ_^ 008-t 19193-0P4twf.doc/n 面。第二晶片的第二背面藉由第—黏著層黏附於第一晶片 的第一主動面。 曰 在本發明之-實施例中，上述之晶片封 第二焊線。第二焊線電性連接至第二晶片與線^条 在本發明之-實施例中’上述之第二晶片具有多個第 -焊签，且線路基板具有多個第二連接塾。第 過第二焊線電性連接至第二焊墊。 m 在本發明之-實關巾，上述之元件.散孰器。 ^發明之-實施例中，上述之第―焊線包括金線。 在本發明之一實施例中，上述之晶片封農，更包括一 第二黏著層黏附於第—晶片的第—背面與線 在本發明之-實施例中，上述之第二轉層包括一第 ς =黏著層以及—第四B階黏著層。第三 =著一=二:第四_著層一 _ :轉=:以：著 璃轉施例中，上述之第三Β階黏著層的玻 /皿度不问於第四Β階黏著層的玻璃轉化溫度。 實施例中，上述之第—Β _著層的玻 同。/皿又，、第—Β階黏著層的玻璃轉化溫度實質上相 201013888 „J08-t 19193-0P4twf.doc/n 在本發明之一實施例中’上述之第一 B階黏著層的玻 璃轉化溫度不同於第二B階黏著層的玻璃轉化溫度。 在本發明之一實施例中’上述之第一晶片的尺寸與元 件的尺寸實質上相同。 ^ 在本發明之一實施例中’上述之第一晶片的邊緣對眘 元件的邊緣。 在本發明之一實施例中’上述之第一晶片的邊緣未對 齊元件的邊緣。 β 基於上述，由於本發明採用的第一黏著層具有呈半固 態狀的一第一Β階黏著層與一第二β階黏著層，因此第一 黏著層的厚度容易控制。此外，因第一黏著層可直接形成 於晶圓（wafer)之主動面上，有利於大量生產。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】201013888 ~------008-t 19193-0P4twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a chip package, and in particular to an improvement Reliability and wafer packaging that reduces production costs. [Prior Art] In recent years, a wafer package having a plurality of stacked wafers (stacked ❹ chiPs) has been gradually developed. The chip package stacks a plurality of wafers above the carrier and is electrically connected to the carrier through a bonding wire or a bump, wherein the bumps are, for example, gold bumps ( Gold bump ), copper bump, polymer bump, or solder bump, and the carrier is, for example, a printed circuit board or a wire. (lead_fram〇. - Generally, each wafer stacked on a carrier can be attached to other wafers or carriers by a knee joint (such as tape or liquid adhesive). In particular, when using tape as a tape In the case of a die-bondling process or a chip-stacking process, tapes with appropriate bulk and dryness are attached to the wafer or carrier. When the agent is used as the bonding process of the wafer bonding process or the wafer stacking process, the liquid adhesive is first disposed on the wafer or on the carrier, and the liquid adhesive is cured after the bonding of the wafer. The wafer bonding process or wafer is performed. stack Before the process, the tape must be cut to the appropriate size, so the tape used here is not suitable for mass production. In addition: wafer 201013888 ^ --- «J08-t 19193-0P4twf.doc/n by the two liquid, the thickness of the agent It is difficult to control and the production cost of the image is to be increased: and the wafer seal is reduced. [Inventive content] The cost of the present invention is increased by the wafer field, which can improve the production and production of the chip-chip package, including - circuit substrate, - a colloid. The first wafer and the other layer and the first back surface of the surface and a plurality of first pads disposed on the first active surface of the first active surface The shaft is connected to the circuit substrate and is firstly connected to the circuit substrate. The first solder chip Μ Μ -: the green power is connected to the circuit substrate and the first er=d2 is on the first active surface of the first wafer = A layer of adhesive adheres to the first active surface of the first wafer and the component; and does not cover the first material. The first to the second layer includes - two = two layers of the layer. The first layer of the beta layer adheres to the first layer : SC : The second B-stage adhesive layer is adhered to the first B-stage 兀π T colloid disposed on the line On the substrate and covering the first day, the first piece, the first adhesive layer and the first-thick line. In one embodiment of the invention, the cover is connected. The first-connected and the upper-welded m-plate has a plurality of The first ^, . nn & 谇 谇 电 电 电 电 电 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ ^ 008-t 19193-0P4twf.doc/n face. The second back side of the second wafer is adhered to the first active surface of the first wafer by the first adhesive layer. In the embodiment of the present invention, the wafer described above encloses a second bonding wire. The second bonding wire is electrically connected to the second wafer and the wire strip. In the embodiment of the invention, the second wafer has a plurality of first-welding marks, and the circuit substrate has a plurality of second connecting ports. The second bonding wire is electrically connected to the second bonding pad. m In the present invention - the actual closing towel, the above-mentioned components. Inventive-embodiment, the above-mentioned first bonding wire includes a gold wire. In an embodiment of the invention, the wafer encapsulation further comprises a second adhesive layer adhered to the first back surface and the line of the first wafer. In the embodiment of the present invention, the second transfer layer comprises a Dijon = Adhesive layer and - Fourth B-stage adhesive layer. The third = the first = two: the fourth _ layer _: turn =: to: the glass to the application, the third layer of the adhesive layer of the glass / dish is not asked the fourth layer of adhesion Glass transition temperature. In the embodiment, the above-mentioned first - Β _ layer is the same as the glass. /, and the glass transition temperature of the first-stage adhesive layer is substantially 201013888 „J08-t 19193-0P4twf.doc/n In one embodiment of the invention, the glass transition of the first B-stage adhesive layer described above The temperature is different from the glass transition temperature of the second B-stage adhesive layer. In one embodiment of the invention, the size of the first wafer described above is substantially the same as the size of the element. ^ In an embodiment of the invention, the above The edge of the first wafer is opposite the edge of the component. In one embodiment of the invention, the edge of the first wafer is not aligned with the edge of the component. β is based on the above, since the first adhesive layer used in the present invention has a semi-solid state a first step adhesive layer and a second beta adhesive layer, so that the thickness of the first adhesive layer is easily controlled. Further, since the first adhesive layer can be directly formed on the active surface of the wafer, it is advantageous The above and other objects, features, and advantages of the present invention will become more apparent and understood.
圖1為本發明之第一實施例之一種晶片封裳的剖面示 意圖。請參考®卜在本實施例中，曰曰曰片封裝刚包括一 線路基板11G、-第—晶片12〇、多條第—焊線13〇、一元 件140、-第-黏著層15〇以及—封裝谬體⑽。第一晶片 =具有-第—主動面施、—相對於第—线面施 的弟-为面120b以及多個配置於第—主動面1施上的第 政其中第—晶片120的第—背® 12%黏附於線 路基板110上，且第一晶片120電性連接至線路基板11〇。 201013888 8 …a---------J08-t 19193-〇P4twf.doc/n 第一焊線130電性連接至線路基板u〇與第_晶片i2〇的 這些第一焊塾122。元件14〇配置於第一晶片12〇的第一 主動面120a的上方。第一黏著層15〇|占附於第一晶片 的第一主動面120a與元件140之間，且未覆蓋第一焊墊 122。第-黏著層150包括一第一 B階黏著層咖以及一 第二B階黏著層15〇b。第一 B階黏著層咖黏附於第一 晶片120的部份第一主動面偷上。第二B階黏著層隱 黏附於第B階黏著層150a與元件14〇之間。封裝膠體 髎⑽配置於線路基板11G上且覆蓋第、元件 140、第一黏著層150以及這些第一焊線1；3()。舉例而言， 線路基板110可為一電路板，例如是FR_4基板、FR 5基 板、BT基板或其他適合的基板。 請再參考圖1，線路基板11〇具有多個第一連接墊 112 ’且這些第一連接墊112配置於線路基板11〇的一表 面。這些第一連接墊112分別透過這些第一焊線13〇電性 連接至這些第一焊墊122。在本實施例中，第一焊線13〇 _ 為打線接合製程所形成的金線。 在本實施例中’元件140為一散熱器。為了提升散熱 效果’封裝膠體160可僅覆蓋部份的元件140 (散熱器）， 換句話說’元件140 (散熱器）的部份表面是暴露於封裝 膠體160外。在其他實施例中，封裝膠體160亦可完全覆 蓋元件140 (散熱器）。請再參考圖1，封裝膠體16〇能保 護這些第一焊線130避免受到毀壞。 在本實施例中，配置於第一晶片120的第一主動面 201013888 -------JU8-t 19193-0P4twf. doc/n 120a上的一第一黏著層15〇可透過以下的步驟進行製作。 首先，提供一晶圓，此晶圓上具有多個成陣列排列的第一 晶片120。接著，形成一第一雙階黏著層於第一晶片12〇 的第一主動面120a上’藉由加熱或紫外線照射使得第一雙 P皆黏著層被部份固化而形成第一 B階黏著層15加。之後， 形成一第二雙階黏著層於第一 B階黏著層15〇&上。最後， 藉由加熱或紫外賴射使得第二㈣姆層被部份固化而 形成第二B階黏著層15〇b。此時，第一 B階黏著層i5〇a 與第雜著層隱便被形成於晶圓駐動面上。當 晶圓被切割（單體化）之後，即可得到第—主動面施 上形成有第-黏著層15G的第-晶片12()。因此，具有第 -BP皆黏著層1他與第二3階黏著層⑽的第—黏著層 150有利於量產。此外，第—B階黏著層}施盘第二^ ，黏著層15Gb的形成方式可以藉由旋轉塗佈法印刷法或 其他適合的方式。 在第二B階黏著層150b被部份固化之同時，第一 b ^著層15Ga也可再進-步麵具有較佳的機械強 度，以保持第-晶片12〇與元件14〇之間的間距（卿）。 ，時，第-B p自b黏著層15Ga可為部份固域是全部固化 ^供足夠的支標力，而第_著層隱可 軟且具黏性的狀態。 永 担=本實_中，當元件14G_於第—晶片12〇或封 ，膠體160覆蓋元件140之後，第—β階黏著層⑽斑 弟二B階黏著層i5〇b會被完全固化。舉例而古，第^ 201013888 P白黏著層150a與第—b階黏著層15此可為ablESTIK的 8008或議8HT，且其玻璃轉換溫度大約介於攝氏八十度BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer package of a first embodiment of the present invention. Please refer to the embodiment. In the embodiment, the enamel package just includes a circuit substrate 11G, a first wafer 12 〇, a plurality of first bonding wires 13 〇, an element 140, a first-adhesive layer 15 〇, and - Encapsulation body (10). The first wafer = has a - first active surface, - a face 120b opposite to the first line surface, and a plurality of first backs of the first wafer 120 disposed on the first active surface 1 ® 12% is adhered to the circuit substrate 110, and the first wafer 120 is electrically connected to the circuit substrate 11A. 201013888 8 ...a---------J08-t 19193-〇P4twf.doc/n The first bonding wire 130 is electrically connected to the first substrate 122 of the circuit substrate u〇 and the first wafer i2〇 . The element 14 is disposed above the first active surface 120a of the first wafer 12A. The first adhesive layer 15〇 is disposed between the first active surface 120a of the first wafer and the element 140 and does not cover the first pad 122. The first adhesive layer 150 includes a first B-stage adhesive layer and a second B-stage adhesive layer 15〇b. The first B-stage adhesive layer is adhered to a portion of the first active surface of the first wafer 120. The second B-stage adhesive layer is affixed between the B-stage adhesive layer 150a and the element 14A. The encapsulant 髎 (10) is disposed on the circuit substrate 11G and covers the first, the element 140, the first adhesive layer 150, and the first bonding wires 1; 3(). For example, the circuit substrate 110 can be a circuit board such as an FR_4 substrate, an FR 5 substrate, a BT substrate, or other suitable substrate. Referring again to FIG. 1, the circuit substrate 11A has a plurality of first connection pads 112' and these first connection pads 112 are disposed on a surface of the circuit substrate 11A. The first connection pads 112 are electrically connected to the first pads 122 through the first bonding wires 13 respectively. In the present embodiment, the first bonding wire 13 〇 _ is a gold wire formed by the wire bonding process. In this embodiment, the element 140 is a heat sink. In order to enhance the heat dissipation effect, the encapsulant 160 may cover only a portion of the component 140 (heat sink). In other words, a portion of the surface of the component 140 (heat sink) is exposed outside the encapsulant 160. In other embodiments, the encapsulant 160 can also completely cover the component 140 (heat sink). Referring again to Figure 1, the encapsulant 16 can protect these first bonding wires 130 from damage. In this embodiment, a first adhesive layer 15〇 disposed on the first active surface 201013888-------JU8-t 19193-0P4twf.doc/n 120a of the first wafer 120 can pass through the following steps. Make it. First, a wafer is provided having a plurality of first wafers 120 arranged in an array. Then, a first double-step adhesive layer is formed on the first active surface 120a of the first wafer 12'. The first double-P adhesive layer is partially cured by heating or ultraviolet irradiation to form a first B-stage adhesive layer. 15 plus. Thereafter, a second double-step adhesive layer is formed on the first B-stage adhesive layer 15 〇 & Finally, the second (four)th layer is partially cured by heating or ultraviolet radiation to form a second B-stage adhesive layer 15〇b. At this time, the first B-stage adhesive layer i5〇a and the first hybrid layer are formed on the wafer holding surface. After the wafer is diced (singulated), the first wafer 12 () on which the first adhesive layer 15G is formed is applied to the first active surface. Therefore, the first adhesive layer 150 having the first-BP adhesive layer 1 and the second third-order adhesive layer (10) is advantageous for mass production. Further, the second-stage adhesive layer} can be applied to the second layer, and the adhesive layer 15Gb can be formed by a spin coating method or other suitable means. While the second B-stage adhesive layer 150b is partially cured, the first b-layer 15Ga may also have a better mechanical strength to maintain the between-wafer 12 and the component 14? Spacing (clear). , the first-B p-b adhesion layer 15Ga may be sufficient for some solid domains to provide sufficient support force, and the first layer may be soft and viscous. For the first time, when the element 14G_ is on the first wafer 12 or the seal, and the colloid 160 covers the element 140, the first-stage adhesion layer (10) and the second-order adhesion layer i5〇b are completely cured. For example, the ^201013888 P white adhesion layer 150a and the -b order adhesion layer 15 can be ablESTIK 8008 or 8HT, and the glass transition temperature is about 80 degrees Celsius
與攝氏二百度之間。此外，第一 B階黏著層15〇a與第二B 階黏著層150b亦可為ABLESTIK的62〇〇、6施、62〇2C 或 HITACHI Chemical C0.，Ltd·提供的 SA_2〇〇_6、 SA-200-10,且其玻璃轉換溫度大約介於攝氏負四十度與攝 氏一百五十度之間。第一 B階黏著層15〇a的玻璃轉換溫 度可大於、等於或小於第二B階黏著層15〇b的玻璃轉換 Φ 溫度。此外，例如可將一些導電粒子（如銀粒子、銅粒子 及金粒子）攙雜於第一 B階黏著層15〇a與第二B階黏著 層150b中以增加導電性。 請再參考圖1 ’晶片封裝⑽更可包括-第二黏著層 170’其貼附於第一晶片12G的第一背面懿與線路基板 110之間。換句話說’第一晶片120藉由第二黏著層17〇 貼附於線路基板11〇〇在本實施例中，第一晶片12〇的尺 寸與元件140 (散熱器）的尺寸實質上相同。此外，第一 φ 晶片120的邊緣對齊元件H0 (散熱器）的邊緣。 立圖2為本發明之第二實施例之一種晶片封裝的剖面示 意圖。請同時參考圖2與圖卜在本實施例中，圖2之晶 片封裝200與圖1之晶片封裝1〇〇相似，惟二者主要差g 之處在於：圖2之晶片封裝200中的第二黏著層17〇包ς :黏附於第-晶片120的第一背面i施上的第三^皆黏 著層170a以及一黏附於第三B階黏著層17〇&與線路基板 U〇之間的第四B階黏著層i70b。在此必須說明的是，第 11 ---------ug-t 19193-0P4twf.doc/n 三B階黏著層17〇a與第四B階黏著層17%可以藉由旋轉 塗佈法、印刷法或其他適合的方式形成於第一晶片的 第一背面120b上或線路基板11()上。 在本實施例中，第一晶片120的尺寸與元件140 (散 熱器）的尺寸實質上相同。此外，第一晶片12〇的邊緣未 . 對齊元件丨4〇 (散熱器）的邊緣。 在本實施例中，當第一晶片120被貼附於線路基板11〇 或封裝膠體160覆蓋第一晶片120之後，第三B階黏著層 ❿ 17〇a與第四B階黏著層i70b會被完全固化。第三b階黏 著層170a與第四B階黏著層n〇b可為ABLESTIK的8008 或8008HT，且其玻璃轉換溫度大約介於攝氏八十度與攝 氏三百度之間。此外，第三B階黏著層17〇a與第四B階 黏著層 170b 亦可為 ABLESTIK 的 6200、62(U、6202C 或 HITACHI Chemical CO·，Ltd.提供的 SA-200-6、 SA-200-10,且其玻璃轉換溫度大約介於攝氏負四十度與攝 氏一百五十度之間。第三B階黏著層17〇a的玻璃轉換溫 ⑩ 度可大於、等於或小於第四B階黏著層1701>的玻璃轉換 溫度。此外，例如可將一些導電粒子（如銀粒子、銅粒子 及金粒子）攙雜於第三B階黏著層170a與第四B階黏著 層170b中以增加導電性。 圖3與圖4為本發明之第三實施例之晶片封裝的剖面 示意圖。請同時參考圖3與圖1，在本實施例中，圖3之 晶片封裝300與圖1之晶片封裝1〇〇相似，惟二者主要差 異之處在於：圖3之元件140為一第二晶片。此外，請同 12 ^8-t 19193-0P4twf.doc/n ❹ 鲁 201013888 時參考圖4與圖2，在本實施例中，圖4之晶片封裝400 與圖2之晶片封裝200相似，惟二者主要差異之處在於·· 圖4之元件140為一第二晶片。 請同時參考圖3與圖4，線路基板11〇具有多個第一 連接墊112與多個第二連接墊丨14，其中這些第一連接墊 112與這些第二連接墊114配置於線路基板11()的同一表 面。元件140 (第二晶片）具有一第二背面14%與一相對 於第一背面140b的第二主動面140a。元件14〇(第二晶片） 的第二背面14〇b藉由第一黏著層15〇貼附於第一晶片12〇 的第一主動面120a。元件140 (第二晶片）包括多個配置 於第二主動面140a的第二焊墊142。此外，晶片封裝3〇〇 更包括多條第二焊線180，這些第二焊線18〇電性連接至 ^件140 (第二晶片）的第二焊墊142與線路基板11〇的 第二連接墊114。在本實施例中，第一 B階黏著層15〇&與 第二B階黏著層150b可形成於具有元件14〇 (第二晶片1 之晶圓（wafer)的背面上。當晶圓被切割（單體化）=後， 即可得到第二背面1働上形成有第—黏著層15G的 H0 (第二晶片）。因此’具有第一 B階黏著層咖 二B階黏著層隱的第-黏著層15G有利於量產。此外， 第一 B階黏著層150a與第二b階黏著層15%的形成方 可以藉由旋轉塗佈法、印刷法或其他適合的方式。在此必 須說明的是，元件14G亦可為—被動元件，其例如是—雷 容器、一電阻器或一電感器。 电 雖然本發明已以實施例揭露如上，然其並非用以限定 13 201013888 8-t 19193-0P4twf.doc/n ，明’任何所屬技術領域中具有通常知識者，在 本發明之精神和範圍内，當可作些許之更動與 發明之保護範圍當視後附之申請專利範圍所界定者為 【圖式簡單說明】 圖1為本發明之第一實施例之一種晶片封 意圖。 仅叼到面示 圖2Between the two degrees of Celsius and Celsius. In addition, the first B-stage adhesive layer 15A and the second B-stage adhesive layer 150b may also be SA 〇〇 6 6 of ABLESTIK, 62 〇〇, 6 、, 62 〇 2C or HITACHI Chemical C0., Ltd. SA-200-10, and its glass transition temperature is between about 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the first B-stage adhesive layer 15〇a may be greater than, equal to, or less than the glass transition Φ temperature of the second B-stage adhesive layer 15〇b. Further, for example, some conductive particles (e.g., silver particles, copper particles, and gold particles) may be doped in the first B-stage adhesive layer 15a and the second B-stage adhesive layer 150b to increase conductivity. Referring to FIG. 1 again, the chip package (10) may further include a second adhesive layer 170' attached between the first back surface of the first wafer 12G and the circuit substrate 110. In other words, the first wafer 120 is attached to the wiring substrate 11 by the second adhesive layer 17A. In the present embodiment, the size of the first wafer 12A is substantially the same as the size of the element 140 (heat sink). Further, the edge of the first φ wafer 120 is aligned with the edge of the element H0 (heat sink). Figure 2 is a cross-sectional view of a wafer package in accordance with a second embodiment of the present invention. Please refer to FIG. 2 and FIG. 2 simultaneously. In this embodiment, the chip package 200 of FIG. 2 is similar to the chip package 1 of FIG. 1, but the main difference between the two is: the first in the chip package 200 of FIG. a second adhesive layer 17 : a third adhesive layer 170a adhered to the first back surface i of the first wafer 120 and an adhesive layer adhered between the third B-stage adhesive layer 17 and the circuit substrate U The fourth B-stage adhesive layer i70b. It must be noted here that the 11th ---------ug-t 19193-0P4twf.doc/n three B-stage adhesive layer 17〇a and the fourth B-stage adhesive layer 17% can be coated by spin coating A cloth method, a printing method, or other suitable means is formed on the first back surface 120b of the first wafer or on the circuit substrate 11(). In the present embodiment, the size of the first wafer 120 is substantially the same as the size of the element 140 (heat sink). Further, the edge of the first wafer 12 is not aligned with the edge of the component 散热器4〇 (heat sink). In this embodiment, after the first wafer 120 is attached to the circuit substrate 11 or the encapsulant 160 covers the first wafer 120, the third B-stage adhesive layer ❿ 17〇a and the fourth B-stage adhesive layer i70b are Fully cured. The third b-stage adhesive layer 170a and the fourth B-stage adhesive layer n〇b may be ABLESTIK's 8008 or 8008HT, and the glass transition temperature is approximately between eighty degrees Celsius and three degrees Celsius. In addition, the third B-stage adhesive layer 17A and the fourth B-stage adhesive layer 170b may also be 6200, 62 of ABLESTIK (U, 6202C or SA-200-6, SA-200 supplied by HITACHI Chemical CO., Ltd.). -10, and its glass transition temperature is between about 40 degrees Celsius and 150 degrees Celsius. The glass transition temperature of the third B-stage adhesive layer 17〇a can be greater than, equal to, or less than the fourth B. The glass transition temperature of the order adhesion layer 1701>. Further, for example, some conductive particles (such as silver particles, copper particles, and gold particles) may be doped in the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b to increase conductivity. 3 and FIG. 4 are schematic cross-sectional views of a wafer package according to a third embodiment of the present invention. Referring also to FIG. 3 and FIG. 1, in the present embodiment, the chip package 300 of FIG. 3 and the chip package 1 of FIG. 〇〇 is similar, but the main difference between the two is that the component 140 of Figure 3 is a second wafer. In addition, please refer to Figure 4 and Figure 2 when 12^8-t 19193-0P4twf.doc/n 2010 Lu 201013888 In the present embodiment, the chip package 400 of FIG. 4 is similar to the chip package 200 of FIG. 2, but the main difference between the two The component 140 of FIG. 4 is a second wafer. Referring to FIG. 3 and FIG. 4 simultaneously, the circuit substrate 11A has a plurality of first connection pads 112 and a plurality of second connection pads 14, wherein the A connection pad 112 and the second connection pads 114 are disposed on the same surface of the circuit substrate 11 (). The component 140 (second wafer) has a second back surface 14% and a second active surface 140a opposite to the first back surface 140b. The second back surface 14〇b of the element 14〇 (second wafer) is attached to the first active surface 120a of the first wafer 12A by the first adhesive layer 15〇. The element 140 (second wafer) includes a plurality of configurations The second pad 142 of the second active surface 140a. In addition, the chip package 3 further includes a plurality of second bonding wires 180, and the second bonding wires 18 are electrically connected to the device 140 (second wafer) The second bonding pad 142 and the second connection pad 114 of the circuit substrate 11 . In the embodiment, the first B-stage adhesive layer 15 〇 & and the second B-stage adhesive layer 150 b may be formed with the component 14 〇 (the first On the back side of the wafer of the two wafers 1. When the wafer is cut (single) = then the second back 1 is obtained. H0 (second wafer) having the first adhesive layer 15G is formed thereon. Therefore, the first adhesive layer 15G having the first B-stage adhesive layer and the B-stage adhesive layer is advantageous for mass production. In addition, the first B-stage adhesive The formation of the layer 150a and the second b-stage adhesive layer may be 15% by spin coating, printing or other suitable means. It must be noted that the component 14G may also be a passive component, for example - A lightning vessel, a resistor or an inductor. Although the present invention has been disclosed above by way of example, it is not intended to limit the scope of the present invention, which is within the spirit and scope of the present invention. The scope of protection of the invention is defined by the scope of the appended claims. FIG. 1 is a schematic view of a wafer seal according to a first embodiment of the present invention. Only to face up Figure 2
為本發明之第二實施例之一種晶片封裴的剖面八 圖3與圖4 示意圖。 為本發明之第三實施例之晶片封袭 的剖面 【主要元件符號說明】 100、200、300、400 :晶片封裝 110 ·線路基板 112 :第一連接塾 114 :第二連接墊 120 :第一晶片 120a .第一主動面 120b :第一背面 122 :第一焊墊 130 :第一焊線 140 :元件 140a .第·—主動面 201013888… 19193 -0P4twf.doc/n 140b :第二背面 142 :第二焊墊 150 :第一黏著層 150a :第一 B階黏著層 150b :第二B階黏著層 160 :封裝膠體 170 :第二黏著層 170a :第三B階黏著層 參 170b :第四B階黏著層 180 :第二焊線A cross-sectional view of a wafer package of the second embodiment of the present invention is shown in Figs. 3 and 4. The wafer sealing section of the third embodiment of the present invention [main element symbol description] 100, 200, 300, 400: chip package 110 · circuit substrate 112: first connection port 114: second connection pad 120: first Wafer 120a. First active surface 120b: first back surface 122: first solder pad 130: first bonding wire 140: element 140a. - active surface 201013888... 19193 - 0P4twf.doc / n 140b: second back surface 142: The second bonding pad 150: the first adhesive layer 150a: the first B-stage adhesive layer 150b: the second B-stage adhesive layer 160: the encapsulant 170: the second adhesive layer 170a: the third B-stage adhesive layer ginseng 170b: the fourth B Adhesive layer 180: second bonding wire