TW200921873A - Chip-to-substrate interconnection device with wire-bonding - Google Patents

Chip-to-substrate interconnection device with wire-bonding Download PDF

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Publication number
TW200921873A
TW200921873A TW096142571A TW96142571A TW200921873A TW 200921873 A TW200921873 A TW 200921873A TW 096142571 A TW096142571 A TW 096142571A TW 96142571 A TW96142571 A TW 96142571A TW 200921873 A TW200921873 A TW 200921873A
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Taiwan
Prior art keywords
wafer
wire
substrate
bonding
solder joint
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TW096142571A
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Chinese (zh)
Inventor
Alex Liu
Winson Chang
Cary Chou
Chia-Chang Chang
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Powertech Technology Inc
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Priority to TW096142571A priority Critical patent/TW200921873A/en
Publication of TW200921873A publication Critical patent/TW200921873A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed is a chip-to-substrate interconnection device with wire-bonding, at least comprising a substrate, a chip disposed on the substrate and a bonding wire. The bonding wire has a first bond and a second bond, where the first bond is bonded to a bonding pad of the chip, the second bond is bonded to a finger on the substrate. Moreover, the bonding wire has a wire section between the first and the second bonds including a plurality of protruding bending points and a plurality of denting bending points, which are located above the active surface of the chip with staggered intervals. Accordingly, the problem that long bonding wire contacts edge(s) of the active surface of the chip will be solved.

Description

200921873 九、發明說明： 【發明所屬之技街領域】 本發明係有關於-種多晶片主動面朝上堆疊技衍 特別#有關於—種打線連接之晶片與基板互連 【先前技術】 。 在晶片封裝與晶片組裝的領域中’打線接合(wire bonding於其簡易性及便捷性，最常使用 f ：； 與基板兩者電性互連之技術。打線形成之銲線是 彎折之細金屬線(如金線、銅線或其合金線），使晶片上 的銲墊和基板上導電線路的手指相連接藉以將：曰 粒之電性訊號傳輸到外界。因此，銲線的電性連接品: 是非常重要的，其決定了積體電路產品之信賴性與運作 效能。 然而，習知晶片之銲墊形成位置應為晶片主動面之 周邊區域，以縮短銲線在主動面上之長度。當該鋒塾位 t 置變更至於晶片主動面之内圍區域，如主動面之中央區 域時，則銲線在主動面上之長度會增加，又習知晶片主 動面之邊緣為切割面，無保護層設計。當銲線在主動面 上之長度越長則越容易有位移之現象，一旦長銲線碰觸 至晶片主動面之邊緣，將會有漏電流與短路問題。 如第1圖所示’為習知打線連接之晶片與基板互連結 構之截面示意圖。該晶片與基板互連結構100主要包含一 基板110、一晶片120以及一銲線130。該基板110係具有 至少一接指111。該晶片1 20係具有一位於其主動面j 2丨上 5 200921873200921873 IX. Description of the invention: [Technical street field to which the invention pertains] The present invention relates to a multi-wafer active face-up stacking technique. Specially related to a type of wire-bonded wafer-to-substrate interconnection [Prior Art]. In the field of chip packaging and wafer assembly, 'wire bonding is simple and convenient. The most common use is f:; the technology of electrically interconnecting with the substrate. The wire formed by the wire is bent. A metal wire (such as a gold wire, a copper wire or an alloy wire thereof) connects the pad on the wafer and the finger of the conductive line on the substrate to transmit the electrical signal of the particle to the outside. Therefore, the electrical property of the wire Connector: It is very important, which determines the reliability and operational efficiency of the integrated circuit product. However, the pad formation position of the conventional wafer should be the peripheral area of the active surface of the wafer to shorten the bonding line on the active surface. Length: When the front position t is changed to the inner area of the active surface of the wafer, such as the central area of the active surface, the length of the bonding wire on the active surface is increased, and the edge of the active surface of the wafer is known as the cutting surface. , no protective layer design. The longer the length of the bonding wire on the active surface, the easier it is to have displacement. Once the long bonding wire touches the edge of the active surface of the wafer, there will be leakage current and short circuit problem. Figure A schematic cross-sectional view of a conventional wafer-to-substrate interconnect structure. The wafer-to-substrate interconnect structure 100 includes a substrate 110, a wafer 120, and a bonding wire 130. The substrate 110 has at least one finger 111. The wafer 1 20 has one on its active surface j 2 5 5 200921873

之銲墊123，利用一黏晶層140黏著該晶片12〇之背面122 而設置於該基板110上。該銲線13〇之—第一銲點131係結 合於該銲墊丨23，其一第二銲點Π2係結合於該基板11〇之 對應接指111。當該晶片1 20之該銲墊} 23至該晶片1 2〇 之主動面邊緣1 24之距離增加，特別是大於該晶片丄20 之主動面邊緣1 2 4至該接指1 1 1之距離，正常打線之該 銲線1 3 0容易碰觸到該晶片1 2 0之主動面邊緣1 2 4。因 此，目前該銲線丨3 〇之線弧高度必須拉高以避免觸及晶 片主動面邊緣。但這樣將造成整體產品高度大為增加， 而無法達到積體電路元件輕薄短小之需求，如在封裝時 會造成模具與封裝膠體的多餘材料成本。 【發明内容】 本發明之主要目的係在於提供一種打線連接之晶片 與基板互連結構，在正常或被降低銲線之線弧高度下， 維持穩定，避免長銲線碰觸到晶片之主動面邊緣之問 題0 本發明之次一目的係在於提供一種打線連接之晶片 與基板互連結構，可增加銲線之線弧強度。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明之—種打線連接之晶片與基板 互連結構主要包含一基板、一晶片以及一銲線。該基板係 具有至少一接指。該晶片係設置於該基板上並具有_主動面 以及至少—位於該主動面上之銲塾。該鋒線係、具有—第一輝 點與-第二銲點，該第一銲點係結合於該銲塾，該第二銲點 6 200921873 係結合於該接指，其中該銲線在該第-銲點與該第二銲點之 問之線段係形成有複㈣凹轉析點與複數個凸轉折點並£ 交錯間隔。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的打線連接之晶H i 片-、基板互連結構中，該些凸轉 折點之數量相對於該些凹轉折點之數量係可為多—個，以使 該第一銲點與該第二銲點各鄰接有一凸轉折點。 在前述的㈣連接之晶片與基板互連結構中，該晶片之 主動面係可具有-在該接指與該銲，之間之邊緣，並且該晶 片之該邊緣至該銲墊之距離係大於 饰大於該晶片之該邊緣至該接 指之距離’以使所有的凹轉折點皆位於該主動面之上方。 在前述的打線連接之w與基板互連結構中，上述鄰接 於該第二鲜點之凸轉折點係可對準於該晶片之邊緣之上方。 在前述的打線連接之晶片與基板互連結構令，在該此凹 轉折點之中-凹轉折點係可連接上述鄰接於該n點之 凸轉折點，其係接觸至該晶片之該主動面。 在前述的打線連接之晶片與基板互連結構中，該銲線係 可為正向打線形成’而使該第，為—頭鍵合端，且該第 一銲點為一尾鍵合端。 在前述的打線連接之晶片與基板互連結構中非用以 限定本發明地，該些凹轉折點至相鄰接之凸轉折點之線長 係可概為等長^ 在前述的打線連接之晶片與基板互連結構中，該第二銲 7 200921873 轉折點至相 點至所鄰接之凸轉折點之線長係可大於該些凹 鄰接之凸轉折點之線長。 ’該銲線之 在前述的打線連接之晶片與基板互連結構中 該線段係可為波浪狀並能位於該主動面之上方。 在前述的打線連接之晶片與基板互連結構中，非用以 限定本發明地，該銲線之該線段係可為雙M狀並位於該主 動面之上方。The pad 123 is disposed on the substrate 110 by bonding a back surface 122 of the wafer 12 with a die layer 140. The bonding wire 13 is bonded to the pad 23, and a second pad 2 is bonded to the corresponding finger 111 of the substrate 11. The distance from the pad of the wafer 110 to the active edge 1 24 of the wafer 1 2 is increased, in particular, greater than the distance from the active edge 1 24 of the wafer 20 to the finger 1 1 1 The bonding wire 1 30 of the normal wire is easy to touch the edge 1 2 4 of the active surface of the wafer 120. Therefore, the height of the line arc of the wire 丨3 必须 must be raised to avoid touching the edge of the active surface of the wafer. However, this will result in a large increase in the overall product height, and will not be able to meet the demand for the thinness and shortness of the integrated circuit components, such as the excess material cost of the mold and the encapsulant during packaging. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wire-to-substrate interconnection structure for wire bonding, which is stable under the normal or reduced wire arc height of the bonding wire, and prevents the long bonding wire from contacting the active surface of the wafer. Edge Problem 0 The second object of the present invention is to provide a wire-to-substrate interconnection structure for wire bonding, which can increase the wire arc strength of the wire. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The wafer-to-substrate interconnect structure according to the present invention mainly comprises a substrate, a wafer and a bonding wire. The substrate has at least one finger. The wafer is disposed on the substrate and has an active surface and at least a solder fillet on the active surface. The front line has a first point and a second point, the first point is bonded to the pad, and the second pad 6 200921873 is coupled to the finger, wherein the wire is in the - The line between the solder joint and the second solder joint is formed with a complex (four) concave turn-off point and a plurality of convex turning points and a staggered interval. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the above-mentioned wire-bonded crystal H i-chip-substrate interconnection structure, the number of the convex turning points may be more than the number of the concave turning points, so that the first solder joint and the second Each of the solder joints has a convex turning point adjacent to it. In the aforementioned (iv) connected wafer and substrate interconnection structure, the active surface of the wafer may have an edge between the finger and the solder, and the distance from the edge of the wafer to the pad is greater than The decoration is larger than the distance from the edge of the wafer to the finger so that all the concave turning points are located above the active surface. In the aforementioned wire bonding and substrate interconnection structure, the convex inflection point adjacent to the second fresh spot may be aligned above the edge of the wafer. In the foregoing wire bonding substrate-substrate interconnection structure, a concave inflection point is connected to the convex inflection point adjacent to the n point, which is in contact with the active surface of the wafer. In the above-mentioned wire-bonding substrate-substrate interconnection structure, the bonding wire may be formed by positive wire bonding and the first bonding terminal, and the first bonding point is a tail bonding terminal. In the foregoing wafer-to-substrate interconnection structure, the wire-to-substrate interconnection structure is not limited to the present invention, and the line lengths of the concave turning points to the adjacent convex turning points may be substantially equal to each other. In the substrate interconnection structure, the line length of the second welding 7 200921873 turning point to the adjacent convex turning point may be greater than the line length of the convex turning points of the concave adjacent. The wire can be wavy and can be positioned above the active surface in the previously bonded wire-to-substrate interconnect structure. In the aforementioned wire-bonded wafer-to-substrate interconnect structure, which is not intended to limit the present invention, the wire segment of the wire may be double M-shaped and located above the active surface.

在前述的打線連接之晶片與基板互連結構中，另可包含 有一非液態黏晶層，黏接該晶片之一背面至該基板。 在前述的打線連接之晶片與基板互連結構中，該銲墊係 可為中央型銲墊。 【實施方式】 依據本發明之第一具體實施例，具體揭示一種打線 連接之晶片與基板互連結構。請參閲第2圖所示，一種 打線連接之晶片與基板互連結構2〇〇主要包含一基板 210、一晶片220以及一銲線230。 該基板210係具有至少一接指211，可配置於該基板21〇 之一上表面。通常該基板210係為一印刷電路板或各種晶片 載板。s亥晶片2 2 0係設置於該基板上2 1 〇並具有一主動面2 2 1 以及至少一位於該主動面221上之銲墊223。在本實施例 中’可利用一非液態黏晶層240 ’例如膠帶、B階黏膠（B_stage adhesive)或是晶片貼附物質（Die Attach Material，DAM)，黏 接該晶片220之一背面222至該基板210之上表面而無溢膠 現象’故該基板210之接指211可極接近該基板21〇之一黏 200921873 晶區域（即可供設置該晶片220之位置）。該非液態黏晶層24〇 可孭先形成於該晶片220之該背面222再貼附至該基板 21〇;或者，該非液態黏晶層240可先形成於該基板21〇，以 供黏接該晶片220。而該晶片220之主動面22 1係可具有一 在該接指2 11與該銲墊223之間之邊緣224。 該銲線230係具有一第一銲點231與一第二銲點232，該 第一銲點23 1係結合於該銲墊223，該第二銲點232係結合 (、於該接指2U。其中該銲線230在該第一銲點23丨與該第二 銲點232之間之線段係形成有複數個凹轉折點233與複數個 凸轉折點234並呈交錯間隔，在本實施例中，該銲線23〇之 該線段係可為波浪狀並位於該主動面22丨之上方。 在本實施例中，該銲線230係可為正向打線（forward bonding)形成，而使該第一銲點231為一頭鍵合端（或稱球接 2端，baU bond)’且該第二銲點232為一尾鍵合端（或稱訂 f .合式接合端，Sthchb〇nd)，此乃為一般傳統的打線技術，除 k 了可降低打線成本外，亦易於控制打線之弧度。在該銲線230 之打線形成過程，該第一銲點23丨係可利用毛細管（capiuary) 又稱兗嘴或銲針（圖未繪出）利用電子點火（spark discharge) 或氫焰燒將該銲線23G的端點結出—球體，而後再將該球體 壓置於該晶片靡之第—銲點231上而使該球體受壓變形， 再利用超曰波銲接（ultras〇mc welding)技術令其銲結於該第 銲點23 1上；接著，向上拉舉該銲嘴，沿著設計好的路徑， 、i過前f折、拉長、後彎折與再拉伸的重覆動作，以形成該 些凹轉折點233與該些凸轉折點2以，再將該銲線2儿拉銲 9 200921873 =該第二_點232上，同時並拉斷該銲線23〇以形成該第二 鈈點232，最後完成該銲線23〇的形成動作。In the above-mentioned wire bonding substrate-substrate interconnection structure, a non-liquid adhesive layer may be further included to adhere the back surface of the wafer to the substrate. In the aforementioned wire bonding substrate-substrate interconnection structure, the pad may be a center type pad. [Embodiment] According to a first embodiment of the present invention, a wire-to-substrate interconnection structure for wire bonding is specifically disclosed. Referring to FIG. 2, a wire-to-substrate interconnect structure 2 is mainly composed of a substrate 210, a wafer 220, and a bonding wire 230. The substrate 210 has at least one finger 211 and can be disposed on an upper surface of the substrate 21〇. Typically, the substrate 210 is a printed circuit board or a variety of wafer carriers. The IGBT chip 2 2 0 is disposed on the substrate and has an active surface 2 2 1 and at least one pad 223 on the active surface 221 . In this embodiment, a non-liquid adhesive layer 240 such as a tape, a B-stage adhesive, or a Die Attach Material (DAM) may be used to bond the back surface 222 of the wafer 220. Up to the upper surface of the substrate 210 without overflow phenomenon, the contact 211 of the substrate 210 can be in close proximity to the substrate 21 黏 one of the 200921873 crystal regions (ie, the position at which the wafer 220 can be disposed). The non-liquid viscous layer 24 can be formed on the back surface 222 of the wafer 220 and then attached to the substrate 21 〇; or the non-liquid viscous layer 240 can be formed on the substrate 21 〇 for bonding Wafer 220. The active surface 22 1 of the wafer 220 can have an edge 224 between the contact 2 11 and the pad 223. The bonding wire 230 has a first solder joint 231 and a second solder joint 232. The first solder joint 23 1 is coupled to the solder pad 223, and the second solder joint 232 is coupled to the second solder joint 232. A line segment between the first pad 23 丨 and the second pad 232 is formed with a plurality of concave turning points 233 and a plurality of convex turning points 234 at a staggered interval. In this embodiment, The wire segment of the wire 23 can be wavy and located above the active surface 22A. In this embodiment, the wire 230 can be formed by forward bonding, and the first The solder joint 231 is a bonding end (or a ball joint 2, baU bond) ' and the second solder joint 232 is a tail bonding end (or called a f. joint end, Sthchb〇nd), which is For the conventional wire bonding technology, in addition to k, the wire bonding cost can be reduced, and the arc of the wire can be easily controlled. In the wire forming process of the wire 230, the first pad 23 can be utilized as a capillary. The nozzle or soldering pin (not shown) uses the spark discharge or hydrogen flame to extinguish the end of the wire 23G. The body is then pressed onto the first solder joint 231 of the wafer to deform the sphere, and then soldered to the solder joint by ultrasonic welding (ultras mc welding) technology. 23 1; then, the nozzle is pulled up, along the designed path, i, the front f fold, the elongated, the rear bend and the re-stretching repeated action to form the concave turning points 233 and The convex turning points 2 are, and then the bonding wire 2 is welded 9 200921873 = the second_point 232, and the bonding wire 23 is pulled off to form the second defect 232, and finally the bonding wire is completed. 23 〇 formation action.

因此，該些凸轉折點234之數量相對於該些凹轉折點加 之數量係可為多一個，以使該第一銲點231與該第二銲點 232各鄰接有一凸轉折點234。在該些凸轉折點Mu之中， 其中-鄰接於該第二輝點232之—凸轉折點2姐必然會連 接有-位於該主動S 221上之凹轉折點233a，利用該凹轉 折點233A可使該凸轉折點而更為遠離該晶片22〇之邊 緣224,進而確保該銲線23〇與該晶片22〇之邊緣224不相 接觸，而不致於造成碰觸而產生露電流與短路之問題。因 此，該晶片與基板互連結構200在正常或被降低之銲線 230之線弧高度下維持穩定，使其更便於製造及得到較 佳之訊號傳遞效果並降低積體電路產品之厚度。當該晶 片與基板互連結構200運用於積體電路封裝則可以減 少所使用封膠體體積。 在一較佳結構中，利用該凹轉折點233A之角度控制，上 述鄰接於該第二銲點232之凸轉折點234A係可對準於該晶 片220之邊緣224之上方，以確保該銲線23〇遠離該該晶片 220之邊緣224而不致碰觸造成短路。此外，較佳地，該晶 片220之s亥邊緣224至該鋅墊223之距離係大於該晶片220 之β玄邊緣2 2 4至g玄接指2 1 1之距離，以使所有的凹轉折點2 3 3 皆位於該主動面22 1之上方。 在一實際運用上’如第2圖所示，在該些凹轉折點233 之中一凹轉折點233A係可連接上述鄰接於該第二銲點232 10 200921873 之凸轉折點234A。即使該凹轉折點23从係接觸至該晶月 220之該主動面221(圖中未緣出），仍被該晶片22〇之該主動 面221上之表面保護層（passivaU〇niayer)所電氣絕緣，不會 影響電性傳遞品質。然'該凸轉折點234A可更往上趣起後再 向下打線連接至該接指2 u，而能更加遠離該晶片之該 邊緣224。在本實施例_，該些凹轉折點233至相鄰接之凸 轉折點234之線長係可概為等長，以構成等距之波浪狀彎 折，亦可不需要等長。通常該第二銲點232至所鄰接之凸轉 折點234A之線長係可大於該些凹轉折點233至相鄰接之凸 轉折點234之線長。 更具體而言，該銲墊223係可為中央型銲墊，而具有較 長之銲線距離在該晶片22〇之主動面22丨上，以便於形成本 發明之波浪狀銲線230。 在第二具體實施例中’揭示另一種打線連接之晶片與基 板互連結構。如第3圖所示，該晶片與基板互連結構3 〇 〇 主要包含一基板310、一晶片320以及一銲線330。該基板 3 1 0之上表面係具有至少一接指3丨丨。該晶片32〇係設置於 該基板310上並具有一主動面321以及至少一位於該主動面 32 1上之銲墊323。可利用一黏晶層340黏接該晶片320之 一背面322至該基板310。該晶片320之主動面321可具有 一在該接指311與該銲墊323之間之邊緣324。 該銲線3 3 0係具有一第一銲點3 3 1與一第二銲點3 3 2，該 第一銲點331係結合於該銲墊323，該第二銲點332係結合 於該接指311，其中該銲線330在該第一銲點331與該第二 11 200921873 曰’’之間之線奴係形成有複數個凹轉折點333與複數個 凸轉㈣334並呈交錯間隔（如第3圖所示）。在該些凸轉折 '有凸轉折點3 3 4 A ’其係鄰接於該第二銲點3 3 2 且概約對準於該晶片320之邊緣324之上方。Therefore, the number of the convex turning points 234 may be one more than the number of the concave turning points, so that the first soldering point 231 and the second soldering point 232 are adjacent to each other with a convex turning point 234. Among the convex turning points Mu, wherein - adjacent to the second bright point 232 - the convex turning point 2 sister is bound to be connected with a concave turning point 233a on the active S 221, by which the convex turning point 233A can be used to make the convex The turning point is further away from the edge 224 of the wafer 22, thereby ensuring that the bonding wire 23 is not in contact with the edge 224 of the wafer 22 without causing contact problems to cause current leakage and short circuit. Thus, the wafer-to-substrate interconnect structure 200 remains stable at the line arc height of the normal or lowered bond wires 230, making it easier to manufacture and providing better signal transfer and reducing the thickness of the integrated circuit product. When the wafer and substrate interconnect structure 200 is applied to an integrated circuit package, the volume of the sealant used can be reduced. In a preferred configuration, by the angular control of the concave turning point 233A, the convex turning point 234A adjacent to the second solder joint 232 can be aligned above the edge 224 of the wafer 220 to ensure the bonding wire 23〇. Moving away from the edge 224 of the wafer 220 without touching it causes a short circuit. In addition, preferably, the distance from the edge 224 of the wafer 220 to the zinc pad 223 is greater than the distance between the β-edge 2 2 4 of the wafer 220 and the finger 1 21 to make all the concave turning points. 2 3 3 are located above the active surface 22 1 . In a practical application, as shown in Fig. 2, a concave turning point 233A is connected to the concave turning point 234A adjacent to the second welding point 232 10 200921873 among the concave turning points 233. Even if the concave turning point 23 is in contact with the active surface 221 of the crystal moon 220 (not shown), it is electrically insulated by the surface protective layer (passiva U〇niayer) on the active surface 221 of the wafer 22 Will not affect the quality of electrical transmission. However, the convex turning point 234A can be more interesting and then connected downward to the finger 2 u, and can be further away from the edge 224 of the wafer. In this embodiment, the line lengths of the concave turning points 233 to the adjacent convex turning points 234 may be substantially equal to form an equidistant wavy bend, and may not be equal in length. Generally, the line length of the second solder joint 232 to the adjacent convex turning point 234A may be greater than the line length of the concave turning point 233 to the adjacent convex turning point 234. More specifically, the pad 223 can be a center pad with a longer bond line distance on the active face 22 of the wafer 22 to facilitate formation of the wavy bond wire 230 of the present invention. In the second embodiment, another wire-bonded wafer-to-substrate interconnect structure is disclosed. As shown in FIG. 3, the wafer-substrate interconnect structure 3 〇 〇 mainly includes a substrate 310, a wafer 320, and a bonding wire 330. The upper surface of the substrate 310 has at least one finger 3丨丨. The wafer 32 is disposed on the substrate 310 and has an active surface 321 and at least one pad 323 on the active surface 32 1 . A back side 322 of the wafer 320 can be bonded to the substrate 310 by a die layer 340. The active surface 321 of the wafer 320 can have an edge 324 between the finger 311 and the pad 323. The bonding wire 303 has a first soldering point 3 3 1 and a second soldering point 3 3 2 , and the first soldering point 331 is coupled to the bonding pad 323, and the second soldering point 332 is coupled to the bonding pad 323. The finger 311, wherein the wire bond between the first solder joint 331 and the second 11 200921873 形成'' is formed with a plurality of concave turning points 333 and a plurality of convex turns (four) 334 at a staggered interval (such as Figure 3). The convex transitions 'having a convex turning point 3 3 4 A ' are adjacent to the second solder joint 3 3 2 and are approximately aligned above the edge 324 of the wafer 320.

在本實施例中，在該第一銲點331與該第二鲜點332之 門之I線ϋ為雙M狀並位於該主動面w i之上方。在該 些凹轉折點333之中—凹轉折點333A係可連接上述鄰接於 該第二輝‘點332之凸轉折點334A，更能遠離該晶片32〇之 :亥邊緣324 ’不致於造成該銲線33()碰觸至該晶片似之該 邊緣324。因此，該銲線咖能在—正常或被降低之鲜線弧 局之條件下維持穩定，以便於製造，得到較佳之訊號傳 遞效果並能降低所需要的封膠體體積之功效。 以上所述’僅是本發明的較佳實施例而已，並非對 本發月作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：習知打線連接之晶片與基板互連結構之截面示意 圖。 第2圖.依據本發明之第一具體實施例，一種打線連接 12 200921873 之晶片與基板互連結構之截面示意圖。 第3圖：依據本發明之第二具體實施例，另一種打線連 接之晶片與基板互連結構之截面示意圖。 【主要元件符號說明】 100 晶片與基板互連結構 110 基板 111接指 120 晶片 121主動面 122 背面 123 銲墊 124邊緣 130 銲線 1 3 1第一銲點 132第二銲點 140 黏晶層 200 晶片與基板互連結構 210 基板 211接指 220 晶片 221主動面 222 背面 223 銲塾 224邊緣 230 銲線 231第一銲點 232 第二銲點 233 凹轉折點 233A凹轉折點 234 凸轉折點 234A凸轉折點 240 非液態黏晶層 300 晶片與基板互連結構 310 基板 311接指 320 晶片 321主動面 322 背面 323 銲墊 3 24邊緣 330 銲線 331第一銲點 332 — 力曰田 弟一鲜點 333 凹轉折點 333A凹轉折點 13 200921873 334凸轉折點 334A凸轉折點 340黏晶層 14In this embodiment, the I line of the first solder joint 331 and the second fresh spot 332 is double M-shaped and located above the active surface w i . Among the concave turning points 333, the concave turning point 333A is connectable to the convex turning point 334A adjacent to the second glow point 332, and is further away from the wafer 32: the edge 324' does not cause the bonding wire 33 () Touching the wafer like the edge 324. Therefore, the wire can be stabilized under the condition of a normal or reduced fresh line arc for manufacturing, better signal transmission and lowering the required seal volume. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view showing a structure of a wafer-substrate interconnection structure of a conventional wire bonding. 2 is a cross-sectional view showing a wafer-to-substrate interconnection structure of a wire bonding 12 200921873 in accordance with a first embodiment of the present invention. Figure 3 is a cross-sectional view showing another interconnected structure of a wafer-to-substrate connection in accordance with a second embodiment of the present invention. [Main component symbol description] 100 wafer and substrate interconnection structure 110 substrate 111 interface 120 wafer 121 active surface 122 back surface 123 solder pad edge 130 solder wire 1 3 1 first solder joint 132 second solder joint 140 adhesive layer 200 Wafer-to-substrate interconnect structure 210 substrate 211 finger 220 wafer 221 active surface 222 back surface 223 solder 224 edge 230 solder wire 231 first solder joint 232 second solder joint 233 concave turning point 233A concave turning point 234 convex turning point 234A convex turning point 240 Liquid viscous layer 300 wafer and substrate interconnection structure 310 substrate 311 finger 320 wafer 321 active surface 322 back 323 pad 3 24 edge 330 wire 331 first solder joint 332 - force 曰 Tiandi fresh point 333 concave turning point 333A Concave turning point 13 200921873 334 convex turning point 334A convex turning point 340 adhesive layer 14

Claims (1)

200921873 十、申請專利範圍： 1、 一種打線連接之晶片與基板亙連結構，包含； 一基板，具有至少一接指； 一晶片’設置於該基板上並具有一主動面以及至少一位 於該主動面上之銲塾；以及 一辉線’具有一第一銲點與一第二銲點，該第一銲點係 結合於該銲墊，該第二銲點係結合於該接指，其中該 銲線在該第一銲點與該第二銲點之間之線段係形成有 複數個凹轉折點與複數個凸轉折點並呈交錯間隔。 2、 如申請專利範圍第1項所述之打線連接之晶片與基板 互連結構’其中該些凸轉折點之數量相對於該些凹轉 折點之數量為多一個，以使該第一銲點與該第二銲點 各鄰接有一凸轉折點。 3、 如申請專利範圍第1或2項所述之打線連接之晶片與 基板互連結構’其中該晶片之主動面係具有一在該接 指與該銲墊之間之邊緣，並且該晶片之該邊緣至該銲 塾之距離係大於該晶片之該邊緣至該接指之距離，以 使所有的凹轉折點皆位於該主動面之上方。 4、 如申請專利範圍第3項所述之打線連接之晶片與基板 互連結構’其中上述鄰接於該第二銲點之凸轉折點係 對準於該晶片之邊緣之上方。 5、 如申請專利範圍第3項所述之打線連接之晶片與基板 互連結構，其中在該些凹轉折點之中一凹轉折點係連 接上述鄰接於該第二銲點之凸轉折點，其係接觸至該 15 200921873 晶片之該主動面。 s、如申請專利範圍第1項所述之打線連接之晶片與基板 互連結構，其中該銲線係為正向打線形成，而使該第 一銲點為一頭鰱合端，且該第二銲點為一尾鍵合端。 7、 如申請專利範圍第1或2項所述之打線連接之晶片與 基板互連結構，其中該些凹轉折點至相鄰接之凸轉折 點之線長係概為等長。200921873 X. Patent application scope: 1. A wire-bonding structure of a wafer and a substrate, comprising: a substrate having at least one finger; a wafer being disposed on the substrate and having an active surface and at least one active And the first solder joint is coupled to the solder pad, and the second solder joint is coupled to the finger, wherein the solder joint A line segment between the first solder joint and the second solder joint is formed with a plurality of concave turning points and a plurality of convex turning points at a staggered interval. 2. The wafer-to-substrate interconnection structure of the wire bonding connection described in claim 1 wherein the number of the convex turning points is one more than the number of the concave turning points, so that the first solder joint and the first solder joint The second solder joints each have a convex turning point adjacent to each other. 3. The wafer-to-substrate interconnection structure of the wire bonding as described in claim 1 or 2, wherein the active surface of the wafer has an edge between the bonding finger and the bonding pad, and the wafer is The distance from the edge to the solder fillet is greater than the distance from the edge of the wafer to the finger such that all of the concave turning points are above the active surface. 4. The wafer-to-substrate interconnect structure as described in claim 3, wherein the convex inflection point adjacent to the second solder joint is aligned above the edge of the wafer. 5. The wafer-to-substrate interconnection structure of the wire bonding according to claim 3, wherein a concave turning point is connected to the convex turning point adjacent to the second bonding point among the concave turning points, and the contact is To the active face of the 15 200921873 wafer. s. The wafer-to-substrate interconnection structure of the wire bonding according to claim 1, wherein the bonding wire is formed by positive wire bonding, and the first bonding point is a twisting end, and the second wire is The solder joint is a one-end bond end. 7. The wafer-to-substrate interconnection structure of the wire bonding according to claim 1 or 2, wherein the line lengths of the concave turning points to the adjacent convex turning points are equal in length. 8、 如中請專利範圍第7項所述之打線連接之晶片與基板 互連結構，其中該第二録點至所鄰接之凸轉折點之線 長係大於該些凹轉折點至相鄰接之凸轉折點之線長。 9、 如申請專利範圍第1項所述之打線連接之晶片與基板 互連結構，其中該銲線之該線段係為波浪狀並位於該 主動面之上方。 申明專利圍第1項所述之打線連接之晶片與基板 互連結構，其中該輝線之該線段係為雙Μ狀並位於該 主動面之上方。 Η、如中請專利範㈣丨項所述之打線連接之“與基板 互連結構，另包含有-非液態黏晶層，黏接該晶片之 一背面至該基板。 12、如中請專利範圍第1項所述之打線連接之晶片與基板 互連結構，以該銲墊係為中央型銲墊。 168. The wafer-to-substrate interconnection structure of the wire bonding according to claim 7, wherein the line length of the second recording point to the adjacent convex turning point is greater than the concave turning point to the adjacent convex portion. The line of the turning point is long. 9. The wafer-to-substrate interconnection structure of the wire bonding as described in claim 1, wherein the wire segment of the wire is wavy and located above the active surface. The invention relates to a wire-to-substrate interconnection structure according to the first aspect of the invention, wherein the line segment of the glow line is double-shaped and located above the active surface. Η 如 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利The wafer-to-substrate interconnection structure of the wire bonding according to the above item 1 is characterized in that the bonding pad is a central type bonding pad.
TW096142571A 2007-11-09 2007-11-09 Chip-to-substrate interconnection device with wire-bonding TW200921873A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382506B (en) * 2009-09-24 2013-01-11 Powertech Technology Inc Method and structure of multi-chip stack having central pads with upward active surfaces
TWI614815B (en) * 2014-07-11 2018-02-11 英特爾公司 Bendable and stretchable electronic devices and methods

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382506B (en) * 2009-09-24 2013-01-11 Powertech Technology Inc Method and structure of multi-chip stack having central pads with upward active surfaces
TWI614815B (en) * 2014-07-11 2018-02-11 英特爾公司 Bendable and stretchable electronic devices and methods
US10204855B2 (en) 2014-07-11 2019-02-12 Intel Corporation Bendable and stretchable electronic devices and methods

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