TWI281245B - Wiring bonding structure between a semiconductor chip and a substrate and its method - Google Patents

Wiring bonding structure between a semiconductor chip and a substrate and its method Download PDF

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Publication number
TWI281245B
TWI281245B TW094147742A TW94147742A TWI281245B TW I281245 B TWI281245 B TW I281245B TW 094147742 A TW094147742 A TW 094147742A TW 94147742 A TW94147742 A TW 94147742A TW I281245 B TWI281245 B TW I281245B
Authority
TW
Taiwan
Prior art keywords
pad
bonding
solder joint
wire
substrate
Prior art date
Application number
TW094147742A
Other languages
Chinese (zh)
Other versions
TW200725860A (en
Inventor
Kuo-Sheng Chung
Hui-Chin Fang
Chih-Cheng Hung
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094147742A priority Critical patent/TWI281245B/en
Application granted granted Critical
Publication of TWI281245B publication Critical patent/TWI281245B/en
Publication of TW200725860A publication Critical patent/TW200725860A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49427—Wedge bonds outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A wiring bonding structure between a semiconductor chip and a substrate, mainly includes a substrate, a semiconductor chip, a first bonding wire, a second bonding wire and a bump. The semiconductor chip has a first pad and a second pad. The first bonding wire has a first beginning bond on the first pad and a first ending bond on a common connecting pad, moreover, the bump is bonded to the first ending bond. The second bonding wire has a second beginning bond on the second pad and a second ending bond which is bonded to the bump. The bump is disposed on the first ending bond of the first bonding wire, and the second ending bond of the second bonding wire is bonded to the bump to avoid occurrence of contact short between the first and second bonding wires connecting to the common connecting pad with adjacent bonding wires and to increase bonding strength of the first and second ending bonds.

Description

1281245 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導 以避免高密度打 關於-種半導體m此 日日片封裝構造’特別係有 等體曰日片與基板之打線結構， 線而造成短路。 【先前技術】 目前半導體封裝製程中，對 勒ί ^ ?於封裝的體積要求是越來 越小，但疋對於功能的要求 .^ 丨疋丨日加，以打線方式達到電 雜，鲈舳\ 片雖然虻小，線路卻相形複 …，銲墊/、銲線的數量也越來越多， 、夕以致打線作業的困難 度增加’因此必要時會在基板上設計有制連接墊，以供 :接複數個銲線打線連接’但是當連接塾之間距過小，則 谷易ie成連接在共用連接墊之銲線與鄰近銲線產生碰 觸，而造成產品短路。 如第1圖所示，在習知之半導體封裝構造中，一基板 係具有複數個連接墊m，該些連接墊1U係包含有一共 用連接塾111a’該半導體晶片120之一主動面121係具有 複數個銲墊122，該些銲墊122係包含有一第一銲墊 122a、一第二銲墊i22b及一第三銲墊122c，分別以打線 形成之一第一銲線130、一第二銲線14〇及一第三銲線ι5〇 電性連接該第一銲墊122a、該第二銲墊122b及該第三銲 墊122c至該共用連接墊111a。該第一銲線130係具有一 第一起始銲點13 1以及一第一終結銲點132，該第一起始 銲點131係形成於該第一銲墊122a上，該第一終結銲點 1281245 132係形成於該共用連接墊uu之中間位置，該第二銲線 140之一第一起始銲點141係形成於該第二銲墊12几，該 第二銲線140之一第二終結銲點142係形成於該共用連接 墊112之靠近該晶片120位置，該第三銲線15〇之一第三 赵始銲點151係形成於該第三銲墊122〇，該第三銲線 之第二終結銲點152係形成於該共用連接墊112之較遠 離該日日片12G位置’該第—終結銲點132、該第二終結鲜 點142及該第三終結銲點152係為水平面的線形排列。複 數個銲線1 60係電性連接其餘之該些銲墊丄及該些連接 墊11由於該第一終結銲點132、該第二終結銲點142 及該第三終結銲點152係線形排列於該共用連接墊llla 之不同位置’ ^該第―銲線13G、該第二銲線及該第 三銲線150之長度與打線方式須依照所排列之位置作調 整，尤其是該第一銲線130及該第三銲線15〇之長度較 長，該第一銲線13〇及該第三銲線15〇係會產生一水平方 向之弓曲，在封模時容易導致該第一銲線、該第三銲 線150與相鄰之該些銲線16〇碰觸而造成短路。 【發明内容】 本發明之主要目的係在於提供一種半導體晶片與基 板之打線結構，一第一銲線係具有一第一起始銲點以及一 第、’、ς…鋅點，其中該第一起始銲點係形成於一半導體晶 片之一第一銲墊上，該第一終結銲點係形成於一基板之一 共用連接墊上，-凸塊係設置於該第—終結銲點上，一第 麵線之苐一起始知點係形成於該半導體晶片之一第 7 1281245 二銲塾上’該第二銲線之一第二終結銲點係鍵合於該凸 塊，以避免該第一銲線、該第二銲線與相鄰銲線過於接近 而造成短路。 本發明之次一目的係在於提供一種半導體晶片與基 板間打線結構，其中該第一終結銲點與該第二終結銲點係 為垂直向對應’該凸塊係由打線形成並壓鲜於該第一終結 録點’該第二終結銲點係鍵合於該凸塊，以加強該第一終 φ 結銲點與該第二終結銲點之鍵合強度。 依據本發明，一種半導體晶片與基板之打線結構主要 包含一基板、一半導體晶片、一第一銲線、一第二銲線以 及一凸塊。該基板係具有一共用連接墊，該半導體晶片係 至少具有一第一銲墊以及一第二銲墊，該第一銲線係具有 一第一起始銲點以及一第一終結銲點，其中該第一起始銲 點係形成於該第一銲墊上’該第一終結銲點係形成於該共 用連接墊上’該凸塊係設置於該第一終結銲點上，該第二 # 銲線係具有一第二起始銲點以及一第二終結銲點，其中該 第二起始銲點係形成於該第二銲墊上，該第二終結銲點係 鍵合於該凸塊。 【實施方式】 請參閱第2、3圖，在本發明之一具體實施例中，一 種半導體晶片與基板之打線結構主要包含一基板2丨〇、一 半導體晶片220、一第一銲線，23〇、一第二銲線25〇以及 一第一凸塊241。該基板210係具有複數個連接墊211及 一共用連接墊212,該半導體晶片22〇係設置於該基板21〇 8 1281245 上’該半導體晶片220具有一主動面221，該主動面22i 上係具有複數個銲墊222、至少一第一銲墊223以及一第 二銲墊224,其中該第一銲墊223與該第二銲墊224係為 相鄰之銲墊。複數個銲線270係個別連接該些連接墊2ιι 與對應之該些銲墊222，該第一銲線230係具有一第一起 始銲點231以及一第一終結銲點232,該第一起始銲點 係形成於該第一銲墊223上，該第一終結銲點232係形成 • 於該共用連接墊212上，該第一凸塊241係以打線形成， 其係設置於該第一終結銲點232上並壓銲於該第一終結銲 ' 點232。該第二銲線250係具有一第二起始銲點251以及 一第二終結銲點252，該第二起始銲點251係形成於該第 二銲墊224上，該第二終結銲點252係鍵合於該第一凸塊 241上，如第3圖所示，該第一終結銲點232與該第二終 結銲點252係為垂直向對應，以增加該第一終結銲點232 及該第二終結銲點252之鍵合強度。本實施例中，另包含 鲁 有第一凸塊242及一第二銲線26〇，該第二凸塊2々2係 没置於該第二終結銲點252上，該半導體晶片22〇另具有 一第二銲墊225，該第三銲線260之一第三起始銲點261 係形成於該第三銲墊225上，該第三銲線260之一第三終 結銲點262係鍵合於該第二凸塊242上。該第一鲜線23〇 之該第一終結銲點232、該第二銲線250之該第二終結銲 點252及該第三銲線260之該第三終結銲點262係垂直向 排列於該共用連接墊212上，因此銲線之長度不需因為終 結銲點之位置不同而增加，並可使該第一銲線23〇、該第 9 .1281245 三銲線260與相鄰之該些銲線27〇之間距加大，避免鲜線 接觸而導致線路短路之情形。 ~ %參閱第2、3圖’依據本發明之一具體實施例，該 &gt; 半導體晶片與基板之打線方法，包含：提供一基板210, 該基板210係具有複數個連接墊211以及一共用連接墊 212,接著，設置一半導體晶片22〇於該基板21〇上，該 半導體晶片220之一主動面221係至少具有一第一銲墊 • 223以及第一銲墊224，以打線形成一第一銲線23〇，該 第一銲線230係具有一第一起始銲點231以及一第一終結 銲點232，該第一起始銲點231係形成於該第一銲墊223 上，該第一終結銲點232係形成於該共用連接墊212上， 之後’以打線形成之一第一凸塊24 1設置於該第一終結銲 點232上，並壓銲於該第一終結銲點232，該第一凸塊24i 係用以增加該第一終結銲點232之鍵合強度，接著，再打 線形成一第二銲線250，該第二銲線250係具有一第二起 _ 始銲點251以及一第二終結銲點252,該第二起始銲點251 係形成於該第二銲墊224上，該第二終結銲點252係鍵合 於該第一凸塊2 41上，較佳地，該第一終結銲點2 3 2與該 第一^終結鲜點2 5 2係為垂直向對應。必要時，可再設置一 第二凸塊242於該第二終結銲點252上，並以打線形成一 第三銲線260，該第三銲線260之一第三起始銲點261係 形成於該半導體晶片220之一第三銲墊225,且該第三銲 線2 6 0之一第三終結鲜點2 6 2係鍵合於該第二凸塊2 4 2 上，藉由該第一凸塊241及該第二凸塊242之間隔縱向排 10 •1281245 列，以加強在其間之該第一終結銲點232與該第二終結辉 •點252鍵合於該共用連接墊212上之鍵合強度。 本發明之保護範圍當視後附之申請專利範圍戶斤界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 φ 第1圖：習知半導體晶片與基板之打線結構之上視圖。 第2圖：依據本發明之第一具體實施例，一種半導體晶片 與基板之打線結構之上視圖。 ，第3圖：依據本發明之第一具體實施例，該半導體晶片與 基板之打線結構之截面示意圖。 【主要元件符號說明】 111 連接塾 111a 共用連接墊 120 半導體晶片 121 主動面 122 銲墊 122a 第一銲塾 122b 第二銲墊 122c 第三銲墊 130 第一銲線 131 第一起始銲點 132 第一終結銲點 140 第二銲線 141 第二起始銲點 142 第二終結銲點 150 第三銲線 151 第三起始銲點 152 第二終結辉點 160 鲜線 210 基板 211 連接墊 212 共用連接墊 220 半導體晶片 221 主動面 222 鲜塾 223 第一銲墊 224 第二銲墊 225 第三銲墊 11 1281245 230 第一銲線 231 232 第一終結銲點 241 250 第二銲線 251 252 第二終結銲點 260 261 第三起始銲點 262 270 鲜線 第一起始銲點 第一凸塊 242 第二凸塊 第二起始鲜點 第三銲線 第三終結銲點 # 121281245 IX. Description of the Invention: [Technical Field] The present invention relates to a semi-conductor to avoid high-density Structure, line and short circuit. [Prior Art] At present, in the semiconductor packaging process, the volume requirements for the package are getting smaller and smaller, but the requirements for the function are. ^ 丨疋丨日加, to achieve the electrical wiring by the wire, 鲈舳\ Although the film is small, the line is complex... The number of pads/wires is increasing, and the difficulty of wire-making operations is increased. Therefore, if necessary, a connection pad is designed on the substrate for : Connecting a plurality of bonding wires to connect the wires. 'But when the distance between the connecting wires is too small, the wire bonding wires connected to the common connecting pads are in contact with the adjacent bonding wires, causing a short circuit of the product. As shown in FIG. 1 , in a conventional semiconductor package structure, a substrate has a plurality of connection pads m, and the connection pads 1U include a common connection 111a. The active surface 121 of the semiconductor wafer 120 has a plurality of Each of the pads 122 includes a first pad 122a, a second pad i22b and a third pad 122c. The first bonding wire 130 and the second bonding wire are respectively formed by wire bonding. 14〇 and a third bonding wire ι5〇 electrically connect the first bonding pad 122a, the second bonding pad 122b and the third bonding pad 122c to the common connection pad 111a. The first bonding wire 130 has a first starting pad 13 1 and a first ending pad 132. The first starting pad 131 is formed on the first pad 122a. The first termination pad 1281245 132 is formed in the middle of the common connection pad uu. One of the first bonding pads 141 of the second bonding wire 140 is formed on the second pad 12, and the second bonding wire 140 is one of the second bonding wires. A point 142 is formed at a position of the common connection pad 112 adjacent to the wafer 120, and a third bonding wire 151 is formed on the third bonding pad 122, the third bonding wire The second termination solder joint 152 is formed at a position away from the day wafer 12G of the common connection pad 112. The first termination solder joint 132, the second termination fresh spot 142, and the third termination solder joint 152 are horizontal. Linear arrangement. The plurality of bonding wires 1 60 are electrically connected to the remaining pads 丄 and the connecting pads 11 are linearly arranged because the first termination pads 132 , the second termination pads 142 and the third termination pads 152 are linearly arranged In the different positions of the common connection pad 111a, the length of the first bonding wire 13G, the second bonding wire and the third bonding wire 150 and the wire bonding method are adjusted according to the arranged position, especially the first welding The length of the wire 130 and the third wire 15〇 is long, and the first wire 13〇 and the third wire 15 are bent in a horizontal direction, which is easy to cause during the mold sealing. The wire and the third bonding wire 150 are in contact with the adjacent bonding wires 16 to cause a short circuit. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wire bonding structure between a semiconductor wafer and a substrate. A first bonding wire has a first starting solder joint and a first, ', ... zinc point, wherein the first start The solder joint is formed on one of the first pads of the semiconductor wafer, the first solder joint is formed on one of the common connection pads of the substrate, and the bump is disposed on the first termination solder joint, and the first surface is The first starting point is formed on one of the semiconductor wafers 71281245, the second solder joint is bonded to the bump to avoid the first bonding wire, The second bonding wire is too close to the adjacent bonding wire to cause a short circuit. A second object of the present invention is to provide a wire bonding structure between a semiconductor wafer and a substrate, wherein the first termination solder joint and the second termination solder joint are vertically aligned. The bump is formed by a wire and is pressed against the wire. The first termination point 'the second termination solder joint is bonded to the bump to strengthen the bonding strength between the first final φ junction and the second termination. According to the present invention, a wire bonding structure of a semiconductor wafer and a substrate mainly comprises a substrate, a semiconductor wafer, a first bonding wire, a second bonding wire, and a bump. The substrate has a common connection pad, the semiconductor wafer has at least a first pad and a second pad, the first bonding wire has a first starting pad and a first terminating pad, wherein the substrate a first initial solder joint is formed on the first solder pad. The first solder joint is formed on the common connection pad. The bump is disposed on the first termination solder joint, and the second # solder wire has a second starting solder joint and a second solder joint, wherein the second starting solder joint is formed on the second solder pad, and the second solder joint is bonded to the bump. [Embodiment] Referring to Figures 2 and 3, in a specific embodiment of the present invention, a wire bonding structure of a semiconductor wafer and a substrate mainly comprises a substrate 2, a semiconductor wafer 220, and a first bonding wire, 23 〇, a second bonding wire 25〇 and a first bump 241. The substrate 210 has a plurality of connection pads 211 and a common connection pad 212. The semiconductor wafer 22 is disposed on the substrate 21 〇 8 1281245. The semiconductor wafer 220 has an active surface 221 having an active surface 22i thereon. The plurality of pads 222, the at least one first pad 223, and the second pad 224, wherein the first pad 223 and the second pad 224 are adjacent pads. The plurality of bonding wires 270 are individually connected to the connecting pads 2 ι and the corresponding pads 222. The first bonding wires 230 have a first starting pad 231 and a first termination pad 232. The first start Solder joints are formed on the first pad 223, and the first termination pads 232 are formed on the common connection pad 212. The first bumps 241 are formed by wire bonding, and are disposed at the first end. Solder joint 232 is soldered to the first termination weld 'point 232. The second bonding wire 250 has a second starting pad 251 and a second ending pad 252. The second pad 251 is formed on the second pad 224. The second pad is formed. The 252 series is bonded to the first bump 241. As shown in FIG. 3, the first termination solder joint 232 and the second termination solder joint 252 are vertically aligned to increase the first termination solder joint 232. And the bonding strength of the second termination solder joint 252. In this embodiment, the first bump 242 and the second solder wire 26 are included, and the second bump 2 々 2 is not placed on the second termination pad 252. There is a second pad 225, and a third pad 261 is formed on the third pad 225. The third pad 260 is a third termination pad 262. Engaged on the second bump 242. The first termination solder joint 232 of the first fresh line 23, the second termination solder joint 252 of the second bonding wire 250, and the third termination solder joint 262 of the third bonding wire 260 are vertically aligned. The common connection pad 212, so that the length of the bonding wire does not need to be increased due to the position of the termination soldering point, and the first bonding wire 23〇, the 9.8121245 three bonding wire 260 and the adjacent ones can be The distance between the bonding wires 27〇 is increased to avoid the short circuit of the wires caused by the contact of the fresh wires. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Pad 212, and then a semiconductor wafer 22 is disposed on the substrate 21, and one active surface 221 of the semiconductor wafer 220 has at least a first pad 223 and a first pad 224 to form a first line a first bonding wire 231 and a first termination soldering point 232 formed on the first bonding pad 223, the first bonding wire 230 is formed on the first bonding pad 223, the first bonding wire 231 is formed on the first bonding pad 223. An end solder joint 232 is formed on the common connection pad 212, and then a first bump 24 1 is formed on the first termination solder joint 232 and is soldered to the first termination solder joint 232. The first bump 24i is used to increase the bonding strength of the first termination solder joint 232. Then, the second bonding wire 250 is formed by forming a second bonding wire 250. The second bonding wire 250 has a second starting soldering point. 251 and a second termination solder joint 252, the second initial solder joint 251 is formed in the first The second termination pad 252 is bonded to the first bump 241. Preferably, the first termination pad 2 3 2 and the first termination point 2 5 2 The system corresponds to the vertical direction. If necessary, a second bump 242 may be further disposed on the second termination pad 252, and a third bonding wire 260 is formed by wire bonding, and a third initial pad 261 of the third bonding wire 260 is formed. And a third bonding pad 225 of the semiconductor wafer 220, and the third bonding wire 2 6 2 is bonded to the second bump 2 4 2 by the third bonding wire 260 A bump 241 and the second bump 242 are spaced apart from each other by a longitudinal row of 10 12812 45 columns to strengthen the first termination solder joint 232 and the second termination glow point 252 therebetween. Bonding strength. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are protected by the present invention. range. [Simple description of the drawing] φ Fig. 1 is a top view of a conventional wiring structure of a semiconductor wafer and a substrate. Fig. 2 is a top plan view showing a wiring structure of a semiconductor wafer and a substrate in accordance with a first embodiment of the present invention. Fig. 3 is a cross-sectional view showing the wiring structure of the semiconductor wafer and the substrate in accordance with the first embodiment of the present invention. [Main component symbol description] 111 connection port 111a common connection pad 120 semiconductor wafer 121 active surface 122 pad 122a first pad 122b second pad 122c third pad 130 first bonding wire 131 first starting pad 132 An end solder joint 140 a second bonding wire 141 a second starting soldering point 142 a second ending soldering point 150 a third bonding wire 151 a third starting soldering point 152 a second ending bright spot 160 fresh line 210 substrate 211 connection pad 212 sharing Connection pad 220 semiconductor wafer 221 active surface 222 fresh 223 first pad 224 second pad 225 third pad 11 1281245 230 first bond wire 231 232 first termination pad 241 250 second bond wire 251 252 second End solder joint 260 261 third start solder joint 262 270 fresh line first start solder joint first bump 242 second bump second start fresh point third bond line third end solder joint # 12

Claims (1)

1281245 十、申請專利範圍： 1、一種半導體晶片與基板之打線結構，包含 基板，其係具有一共用連接墊； 其至少具有—第 一半導體晶片，係設置於該基板上 一銲墊以及一第二銲墊； 第一銲線’其係具有-第-起始銲點以&amp;-第一終 結銲點/其中該第-起始銲點係形成於該第_鲜= 上，該第一終結銲點係形成於該共用連接墊上； 一第一凸塊，其係設置於該第一終結銲點上；以及 一第二銲線，其係具有一第二起始銲點以及一第二終 結銲點，其中該第二起始銲點係形成於該第二鲜塾 上，該第二終結銲點係鍵合於該第一凸塊。 2 如申請專利範圍第1項所述之半導體晶声與基板之打 線結構，其中該第一終結銲點與該第二終結銲點係為 垂直向對應。 ^ ' 如申請專利範圍第1項所述之半導體晶片與基板之打 線結構，其中該第一凸塊係由打線形成並壓銲於該第 一終結銲點。 4、如申請專利範圍第i項所述之半導體晶片與基板之打 線結構，其另包含有一第二凸塊，其係設置於該第二 終結銲點上。 5、如申請專利範圍第4項所述之半導體晶片與基板之打 線結構，其中該半導體晶片另具有一第三銲墊，且該 打線結構另包含有一第三銲線，其係具有一第三起如 13 1281245 銲點以及一第三終結銲點 成於該第三銲墊上，該第 凸塊上。 ，其中該第三起始銲點 二終結銲點係形成於該 係形 第二 6 之打 之銲 如申請專利範圍第1項所述之半導體晶片與基板 線結構，其中該第一銲墊與該第二銲墊係為：鄰 墊。 一種半導體晶片與基板之打線方法，包含： 提供一基板，該基板係具有一共用連接墊； °又置半導體晶片於該基板上，讀本墓雜曰 泛牛導體晶片係至少 具有一第一銲墊以及一第二銲墊； 打線形成一第一銲線，該第一銲線係具有一第一起始 銲點以及一第一終結銲點’其中該第一起始銲點係开; 成於該第一銲墊上，該第一終結銲點係形成用 連接墊上； ^ 設置一第一凸塊於該第一終結銲點上；以及 打線形成一第二銲線，該第二銲線係具有一第二起始 銲點以及一第二終結銲點’其中該第二起始銲點係开; 成於該第二銲墊上，該第二終結銲點係鍵合於該第一 凸塊。 8、 如申請專利範圍第7項所述之半導體晶片與基板之打 線方法，其中該第一終結銲點與該第二終結銲點係為 垂直向對應。 9、 如申請專利範圍第7項所述之半導體晶片與基板之打 線方法，其中該第一凸塊係由打線形成並壓銲於該第 14 1281245 一終結銲點。 ίο 11 如申請專利範圍第7項所述之半導體0aa&gt;(與基板之打 、、方去其另包含有：設置一第二凸塊於該第二牧社 銲點上。 '' m 如申請專利範圍第1。項所述之半導m與基板之 f線方法，其中該半導體晶片另具有一第三銲墊，且 β亥打線方法另包含有··打線形成-第三銲線，該第： 銲線係具有-第三起始銲點以及一第三終結銲點，其 中該第三起始銲點係形成於該第三銲墊上： 結銲點係形成於該第二凸塊上。 一、、、、 12、 如申請專利範圍第7 線方法，其中該第一 墊0 項所述之半導體晶片與基板之打 銲墊與該第二銲墊係為相鄰之銲 151281245 X. Patent Application Range: 1. A wire bonding structure of a semiconductor wafer and a substrate, comprising a substrate having a common connection pad; at least having a first semiconductor wafer, a solder pad disposed on the substrate, and a first a second bonding pad; the first bonding wire 'having a -first-initial soldering point to &amp;-first terminating soldering point / wherein the first-initial soldering point is formed on the first fresh== An end solder joint is formed on the common connection pad; a first bump is disposed on the first termination solder joint; and a second bonding wire has a second start solder joint and a second And terminating the solder joint, wherein the second starting solder joint is formed on the second fresh solder joint, and the second solder joint is bonded to the first bump. 2. The wiring structure of the semiconductor crystal and the substrate according to claim 1, wherein the first termination solder joint and the second termination solder joint are vertically aligned. The wiring structure of the semiconductor wafer and the substrate according to claim 1, wherein the first bump is formed by wire bonding and is pressure-bonded to the first termination solder joint. 4. The wiring structure of the semiconductor wafer and the substrate of claim i, further comprising a second bump disposed on the second termination pad. 5. The wire bonding structure of the semiconductor wafer and the substrate according to claim 4, wherein the semiconductor wafer further has a third bonding pad, and the wire bonding structure further comprises a third bonding wire, which has a third A 13 1281245 solder joint and a third termination solder joint are formed on the third solder bump. The third starting solder joint and the second solder joint are formed in the second semiconductor of the second embodiment, and the semiconductor wafer and the substrate line structure according to claim 1, wherein the first bonding pad and the first bonding pad are The second pad is: an adjacent pad. A method for bonding a semiconductor wafer to a substrate, comprising: providing a substrate having a common connection pad; and placing a semiconductor wafer on the substrate; the read tomb of the bull-cone conductor film has at least a first pad And a second bonding pad; the bonding wire forms a first bonding wire, the first bonding wire has a first starting soldering point and a first ending soldering point 'where the first starting soldering point is fastened; a first pad solder joint is formed on the connection pad; ^ a first bump is disposed on the first termination pad; and the wire is formed to form a second bond wire, the second wire has a first a second solder joint and a second solder joint, wherein the second solder joint is opened; and the second solder joint is bonded to the first bump. 8. The method of claim 4, wherein the first termination solder joint and the second termination solder joint are vertically aligned. 9. The method of claim 4, wherein the first bump is formed by wire bonding and is pressure bonded to the 141281245 termination solder joint. ο 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The f-wire method of the semiconducting m and the substrate according to the first aspect of the invention, wherein the semiconductor wafer further has a third bonding pad, and the β-wire bonding method further comprises: a wire forming-third bonding wire, The bonding wire has a third starting soldering point and a third ending soldering point, wherein the third starting soldering point is formed on the third bonding pad: a solder joint is formed on the second bump 1. The method of claim 7, wherein the solder pad of the semiconductor wafer and the substrate and the second pad of the first pad 0 are adjacent to each other.
TW094147742A 2005-12-30 2005-12-30 Wiring bonding structure between a semiconductor chip and a substrate and its method TWI281245B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2603929A4 (en) * 2010-08-10 2017-05-03 Cypress Semiconductor Corporation Stitch bump stacking design for overall package size reduction for multiple stack

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2603929A4 (en) * 2010-08-10 2017-05-03 Cypress Semiconductor Corporation Stitch bump stacking design for overall package size reduction for multiple stack

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