JP3824545B2 - Wiring board, semiconductor device using the same, and manufacturing method thereof - Google Patents

Wiring board, semiconductor device using the same, and manufacturing method thereof Download PDF

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Publication number
JP3824545B2
JP3824545B2 JP2002030182A JP2002030182A JP3824545B2 JP 3824545 B2 JP3824545 B2 JP 3824545B2 JP 2002030182 A JP2002030182 A JP 2002030182A JP 2002030182 A JP2002030182 A JP 2002030182A JP 3824545 B2 JP3824545 B2 JP 3824545B2
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Japan
Prior art keywords
semiconductor chip
semiconductor device
conductor
metal
wire
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Expired - Fee Related
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JP2002030182A
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Japanese (ja)
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JP2003234427A (en
Inventor
博昭 藤本
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2002030182A priority Critical patent/JP3824545B2/en
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Publication of JP3824545B2 publication Critical patent/JP3824545B2/en
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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、配線基板、それを用いた半導体装置、それらの製造方法に関するものである。
【０００２】
【従来の技術】
近年、電子機器の小型・高機能化を図るため、半導体パッケージの小型化やベアチップ実装が行われている。以下、図１０、図１１、図１２を用いて、従来の小型半導体パッケージであるＣＳＰについて説明する。まず図１０は、ＣＳＰの樹脂封止部の内部を透視状態で示した上面図である。
【０００３】
ここで、５３はインタポーザで、ガラスエポキシやポリイミドからなる回路基板を構成する。インタポーザ５３における半導体チップ５１の搭載面には複数の内部電極５４が列状に並んだ状態で設けられている。この内部電極５４と半導体チップ５１の電極５２とは、ボンディングワイヤ５５によって互いに電気的に接続されている。インタポーザ５３における半導体チップ５１の搭載面とは反対側の面には、図１１に示すように外部電極６１が設けられている。内部電極５４と外部電極６１とはスルーホール６４を介して電気的に接続されている。内部電極５４、外部電極６１、その他の導体配線は、Ｃｕで形成されている。内部電極５４の表面には、通常Ａｕめっきが施されている。
【０００４】
半導体チップ５１の電極５２とインタポーザ５３の内部電極５４とを接続するボンディングワイヤ５５はＡｕで形成されており、この接続部は封止樹脂で覆われている。ボンディングワイヤ５５と半導体チップ５１の電極５２との接合には通常ボールボンディング方式が用いられる。すなわちＡｕにて形成されたボンディングワイヤ５５の先端がボール状に形成されて電極５２の表面に接合される。また図１２に示すように、ボンディングワイヤ５５とインタポーザ５３の内部電極５４とは、このボンディングワイヤ５５の先端部が内部電極５４の表面で押しつぶされて、互いに接合される。
【０００５】
半導体チップ５１における電極５２どうしの配列のピッチは、上記のＡｕボール接合のために微細化が可能で、６０〜１２０μｍピッチ程度である。これに対し、インタポーザ５３の内部電極５４へのボンディングワイヤ５５の接合部は、Ａｕワイヤを押しつぶすためのキャピラリの先端部がこの接合部に直接接触することになる。そして、このキャピラリの先端部のサイズの影響を受けることで内部電極５４には１００μｍ幅程度のサイズが必要となり、このため内部電極５４どうしの配列ピッチは１４０μｍ程度になるのが一般的である。
【０００６】
【発明が解決しようとする課題】
しかしながら、前記従来の小型半導体パッケージによると、上述のようにインタポーザ５３の内部電極５４どうしのピッチ５８が大きいため、インタポーザ５３における内部電極５４を配置している部分の一辺長６７が大きくなる。その結果、半導体チップ５１からインタポーザ５３の端縁部までの距離６０が大きくなることで、パケージの小型化が困難であった。
【０００７】
そこで、本発明は、上記課題に鑑み、ボンディングワイヤとインタポーザの内部電極とにおける微細な接合を実現して、小型半導体パッケージを提供できるようにすることを目的とする。
【０００８】
【課題を解決するための手段】
上記課題を解決するために、請求項１に記載の本発明の配線基板は、回路基板を形成する絶縁部と、前記絶縁部により支持された導体配線と、前記導体配線を横切って前記導体配線の両側の前記絶縁部上の領域に亘り形成された金属突起とを有し、前記絶縁部の表面に凹凸が形成され、前記金属突起は、前記絶縁部に達するように形成されて前記凹凸にく いこんでいることを特徴とするものである。
【０００９】
これにより、金属突起は導体配線の表面のみならずその側面をも覆うため、導体配線のサイズが小さくても十分な接合強度を達成することが可能となる。また金属突起は絶縁部に達するように形成されて凹凸にくいこんでいるため、この金属突起の接合強度を十分に確保することができる。そして本発明によれば、この配線基板を用いて、半導体チップの電極とインタポーザの電極との接合を実現できるため、半導体の内部電極の微細化を容易に図ることができ、多ピンであっても超小型の半導体パッケージを得ることができる。
【００１０】
請求項２に記載の本発明の配線基板は、金属突起が、Ａｕ、Ｃｕ、Ａｌ、Ｐｂ−Ｓｎ、Ｓｎ−Ａｇ、Ａｕ−Ｓｎのいずれかにて形成されていることを特徴とするものである。
【００１１】
請求項３に記載の本発明の配線基板の製造方法は、回路基板の絶縁部上に形成された導体配線の一部において、金属線の先端部に形成した金属球を前記導体配線の表面および側面を覆ってこの導体配線に接合するように変形させるとともに、前記金属球を、前記絶縁部に達するように変形させてこの絶縁部の表面に形成された凹凸にくいこませ、次に前記導体配線に接合した金属球と金属線とを分離することで、前記導体配線上に金属突起を形成することを特徴とするものである。
【００１２】
請求項４に本発明の半導体装置は、上述の配線基板に半導体チップか搭載され、この半導体チップの電極と金属突起とが電気的に接続されていることを特徴とするものである。
【００１３】
請求項５に記載の本発明の半導体装置は、半導体チップの電極と金属突起とが金属細線によって接続されていることを特徴とするものである。
請求項６に記載の本発明の半導体装置は、複数の金属突起を有し、金属突起どうしの配列ピッチが半導体チップの電極の配列ピッチと同等以下であることを特徴とするものである。
【００１４】
請求項７に記載の本発明の半導体装置は、半導体チップの電極と金属突起とがフリップチップボンディング方式によって接続されていることを特徴とするものである。
【００１５】
請求項８に記載の本発明の半導体装置は、導体配線を有する回路基板に半導体チップが固定され、前記半導体チップの電極と前記回路基板の導体配線の一部とが金属細線で電気的に接続され、この導体配線と金属細線との接続部は、金属細線の先端の変形部が、前記導体配線の表面および側面を覆うとともに、前記金属細線の先端の変形部が、前記回路基板の絶縁部に達するように形成されて、この回路基板の絶縁部の表面に形成された凹凸にくいこんでいることを特徴とするものである。
【００１６】
請求項９に記載の本発明の半導体装置は、回路基板に複数の導体配線が形成され、この導体配線における金属細線との接続部分の配列ピッチが半導体チップの電極の配列ピッチと同等以下であることを特徴とするものである。
【００１７】
請求項１０に記載の本発明の半導体装置は、金属細線の先端の変形部がボール状に形成されていることを特徴とするものである。
請求項１１に記載の本発明の半導体装置の製造方法は、絶縁部上に導体配線を有する回路基板に半導体チップを固定する工程と、前記半導体チップの電極と前記導体配線の一部とを金属細線で接続して、前記金属細線の先端の変形部が、前記導体配線の表面および側面を覆うとともに、前記絶縁部に達してこの絶縁部に形成された凹凸にくいこむようにする工程と、を有することを特徴とするものである。
【００１８】
請求項１２に記載の本発明の半導体装置の製造方法は、回路基板に複数の導体配線を形成し、この導体配線における金属細線の先端の変形部との接続部分の配列ピッチを半導体チップの電極の配列ピッチと同等以下とすることを特徴とするものである。
【００１９】
請求項１３に記載の本発明の半導体装置の製造方法は、金属細線の先端の変形部をボール状に形成することを特徴とするものである。
【００２０】
【発明の実施の形態】
以下に、本発明の実施の形態の配線基板と、それを用いた半導体装置と、その製造方法とについて、図面を参照しながら説明する。
【００２１】
（実施の形態１）
図１は、本発明の実施の形態の配線基板としての部品搭載基板の上面図、図２はその断面図を示すものである。ここで、１は回路基板を形成する絶縁部としてのインタポーザで、ガラスエポキシ基板やポリイミド基板等により構成されている。インタポーザ１における一方の表面および他方の表面にそれぞれ設けられた内部電極２（導体配線）と外部電極４とは、スルーホール１０にて互いに電気的に接続されている。これら内部電極２と外部電極４とはＣｕで形成されており、通常その厚みは５〜３５μｍ程度である。内部電極２の表面には、Ｎｉ下地の上にＡｕめっきが施されている。
【００２２】
複数の内部電極２どうしの配列のピッチは、インタポーザ１に搭載される半導体チップ５の電極６のピッチと同等またはそれ以下になるようにされている。内部電極２の幅のサイズは、半導体チップ５の電極６のピッチが２０〜１００μｍ程度であるため、５〜４０μｍ程度とされている。このような内部電極２は、インタポーザ１のガラスエポキシ基板等に接着されたＣｕ箔をエッチングする方法や、めっき法などによって形成される。
【００２３】
３は金属突起としてのバンプで、図１、図２に示すように、内部電極２の一部分においてこの内部電極２の表面と側面とを覆って、インタポーザ１の絶縁部にまで達するように形成されている。このバンプ３の材料は、Ａｕ、Ｃｕ、はんだ、Ａｌ、Ａｇ、Ｓｎ−Ａｇ、Ａｕ−Ｓｎなどである。また、このバンプ３のサイズは、内部電極２の寸法およびその形成ピッチに合わせて決められている。すなわちバンプ３は、具体的には、その幅寸法が１０〜５０μｍ程度であるとともに、その厚みが１０〜５μｍ程度である。
【００２４】
バンプ３の形成方法としては、金属球を１個ずつ加熱加圧して内部電極２に接合する方法や、例えばガラス基板などにめっき等により形成したバンプ３を内部電極２の数だけ同時に一括接合する方法や、Ａｕワイヤとワイヤボンディングの技術を用いてＡｕボールを加熱加圧した状態で超音波などのエネルギーで接合し、そしてＡｕボールとＡｕワイヤとを切り離す方法などを用いることができる。このとき、バンプ３は、内部電極２の上面と接合することに加えて、その側面とも接合する。これにより、接合強度を確保することができる。また、図３に示すように、インタポーザ１の表面は通常、内部電極２との接着強度を上げるための微小な凹凸１１が形成されており、バンプ３はこの凹凸１１にも食い込ませることができ、これにより、さらにバンプ３と内部電極２の接合強度を上げることができる。また、図３に示すように、内部電極２をエッチングで形成し微細化する場合は、オーバーエッチングにより断面が三角形に近い状態になるが、この場合でも、バンプ３は内部電極２の側面と接合され、またインタポーザ１の絶縁部表面の凹凸にも食い込んでいるため、バンプ３の接合強度を十分に確保できる。
【００２５】
（実施の形態２）
次に、前述のように形成した部品搭載基板に半導体チップを実装した構造の例について、図４、図５、図６にもとづき説明する。図４、図５、図６において５は半導体チップ、６は半導体チップの電極、７は金属細線としてのボンディングワイヤである。
【００２６】
半導体チップ５の実装に際しては、まず、図４に示すように、半導体チップ５をインタポーザ１のほぼ中央に固着する。固着の方法としては、Ａｇペースト絶縁性樹脂で接着することなどが挙げられる。次に、ボンディングワイヤ７にて半導体チップ５の電極６とインタポーザ１の内部電極２を接続する。ボンディングワイヤ７はＡｕ、Ａｌ、Ｃｕなどで形成されており、その線径は５〜２０μｍ程度である。
【００２７】
接合方式としては、超音波熱圧着によるボールボンディング方式や超音波によるウエッヂボンディング方式などを用いる。ボールボンディング方式の場合は、ボンディングワイヤ７における半導体チップ５の電極６側の接合部をボール状にし、また内部電極２のバンプ３への接合はボンディングワイヤ７を押しつぶした状態とする。
【００２８】
このとき、内部電極２の配列ピッチは、半導体チップ５の電極６の配列ピッチと同等以下となるようにされているため、内部電極２の配列の１辺長は半導体チップ５の１辺長と同等以下となる。このためインタポーザ１の外形を小さくすることができ、半導体チップ５が多ピン構造であっても、そのパッケージを超小型に構成することができる。
【００２９】
半導体チップ５の電極６とインタポーザ２の内部電極２の接合方法として、前述したボンディングワイヤ７による方法以外に、図７に示すようなフリップチップボンディング方式を用いることもできる。すなわち、ボンディングワイヤを用いずに、半導体チップ５の電極６とインタポーザ２の内部電極２とを直接接合することもできる。８は、接合部を固定するための樹脂である。この場合の接合方法としては、異方性導電性樹脂接合方式、Ａｕ−Ａｌ拡散接合方式などを用いる。
【００３０】
（実施の形態３）
次に、本発明の実施の形態３について、図８、図９にもとづいて説明する。ここでは、図８に示すように、半導体チップ５はインタポーザ１のほぼ中央部に固着されている。固着の方法は、実施の形態２で示したものと同様である。半導体チップ５の電極６とインタポーザ１の電極２とは、ボンディングワイヤ７により接続されている。インタポーザ１の内部電極２の配列ピッチは、半導体チップ５の電極６の配列ピッチと比べて同等以下である。
【００３１】
ボンディングワイヤ７の接合に際しては、Ａｕボールボンディング方式を用い、Ａｕボール９の接合をインタポーザ１の内部電極２側とする。このとき、図９に詳細に示すように、ボンディングワイヤ７の先端部に形成された変形部としてのＡｕボール９は、インタポーザ１の内部電極２の上面と側面に接合されるとともに、インタポーザ１の絶縁部にも及ぶように形成される。
【００３２】
前述したインタポーザ１として、有機材料にて形成された基板を示したが、セラミック基板でも同様の作用効果を得ることができる。
【００３３】
【発明の効果】
以上のように本発明によれば、金属突起すなわちバンプや、金属細線の先端の変形部が、導体配線の表面のみならずその側面をも覆うため、導体配線のサイズが小さくても十分な接合強度を達成することができ、またバンプや金属細線の先端の変形部を絶縁部の表面の凹凸に食い込むように形成してさらなる接合強度を得ることができるので、半導体の内部電極の微細化を容易に図ることができ、多ピンであっても超小型の半導体パッケージを得ることができる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１における部品搭載基板の上面図
【図２】 図１の部品搭載基板の断面図
【図３】 図２におけるバンプ接合部の拡大断面図
【図４】 本発明の実施の形態２における半導体装置の上面図
【図５】 図４の半導体装置におけるバンプ接合部の拡大縦断面図
【図６】 図５のバンプ接合部の横断面図
【図７】 本発明の実施の形態２における他の半導体装置の断面図
【図８】 本発明の実施の形態３における半導体装置の上面図
【図９】 図８の半導体装置の断面図
【図１０】 従来例の半導体装置の上面図
【図１１】 図１０の半導体装置の要部の断面図
【図１２】 図１０および図１１の半導体装置における接続部の上面図
【符号の説明】
１ インタポーザ
２ 内部電極
３ バンプ
５ 半導体チップ
６ 電極
７ ボンディングワイヤ
９ Ａｕボール
１１ 凹凸[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board, a semiconductor device using the wiring board, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, in order to reduce the size and increase the functionality of electronic devices, semiconductor packages have been downsized and bare chip mounting has been performed. Hereinafter, a CSP which is a conventional small semiconductor package will be described with reference to FIGS. 10, 11, and 12. First, FIG. 10 is a top view showing the inside of the resin sealing portion of the CSP in a transparent state.
[0003]
Here, 53 is an interposer and constitutes a circuit board made of glass epoxy or polyimide. A plurality of internal electrodes 54 are provided in a row on the mounting surface of the semiconductor chip 51 in the interposer 53. The internal electrode 54 and the electrode 52 of the semiconductor chip 51 are electrically connected to each other by a bonding wire 55. An external electrode 61 is provided on the surface of the interposer 53 opposite to the mounting surface of the semiconductor chip 51 as shown in FIG. The internal electrode 54 and the external electrode 61 are electrically connected through a through hole 64. The internal electrode 54, the external electrode 61, and other conductor wiring are made of Cu. The surface of the internal electrode 54 is usually plated with Au.
[0004]
A bonding wire 55 that connects the electrode 52 of the semiconductor chip 51 and the internal electrode 54 of the interposer 53 is made of Au, and this connecting portion is covered with a sealing resin. A ball bonding method is usually used for bonding the bonding wire 55 and the electrode 52 of the semiconductor chip 51. That is, the tip of the bonding wire 55 formed of Au is formed in a ball shape and joined to the surface of the electrode 52. As shown in FIG. 12, the bonding wire 55 and the internal electrode 54 of the interposer 53 are joined to each other by crushing the tip of the bonding wire 55 on the surface of the internal electrode 54.
[0005]
The arrangement pitch of the electrodes 52 in the semiconductor chip 51 can be miniaturized for the above-mentioned Au ball bonding, and is about 60 to 120 μm. On the other hand, in the joint portion of the bonding wire 55 to the internal electrode 54 of the interposer 53, the tip portion of the capillary for crushing the Au wire is in direct contact with the joint portion. Due to the influence of the size of the tip of the capillary, the internal electrode 54 needs to have a width of about 100 μm. For this reason, the arrangement pitch between the internal electrodes 54 is generally about 140 μm.
[0006]
[Problems to be solved by the invention]
However, according to the conventional small semiconductor package, since the pitch 58 between the internal electrodes 54 of the interposer 53 is large as described above, the side length 67 of the portion of the interposer 53 where the internal electrodes 54 are arranged becomes large. As a result, the distance 60 from the semiconductor chip 51 to the end edge portion of the interposer 53 is increased, making it difficult to reduce the size of the package.
[0007]
Accordingly, an object of the present invention is to provide a small semiconductor package by realizing fine bonding between a bonding wire and an internal electrode of an interposer in view of the above problems.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the wiring board of the present invention described in claim 1 includes an insulating portion for forming a circuit board, a conductor wiring is supported by the insulating portion, the conductor wire across the conductor wire Metal protrusions formed over the region on the insulating part on both sides of the insulating part, and irregularities are formed on the surface of the insulating part , and the metal protrusions are formed so as to reach the insulating part. and it is characterized in that at Ku cast.
[0009]
As a result, the metal protrusions cover not only the surface of the conductor wiring but also the side surfaces thereof, so that sufficient bonding strength can be achieved even if the size of the conductor wiring is small. Further, since the metal protrusion is formed so as to reach the insulating portion and is not easily uneven, the bonding strength of the metal protrusion can be sufficiently ensured. According to the present invention, since this wiring board can be used to realize the bonding between the electrodes of the semiconductor chip and the electrodes of the interposer, the internal electrodes of the semiconductor can be easily miniaturized, and the number of pins can be increased. In addition, an ultra-small semiconductor package can be obtained.
[0010]
The wiring board of the present invention according to claim 2 is characterized in that the metal protrusion is formed of any one of Au, Cu, Al, Pb—Sn, Sn—Ag, and Au—Sn. is there.
[0011]
A method for manufacturing a wiring board of the present invention according to claim 3, Oite the part of the conductor wiring formed on an insulating portion of the circuit board, a metal ball formed on the tip of the metal wire of the conductor wire Rutotomoni is deformed so as to bond over the surface and the side to the conductor wiring, the metal ball, the deformed so as to reach the insulating portion by bite into the surface of the formed unevenness of the insulating portion, then A metal protrusion is formed on the conductor wiring by separating the metal sphere and the metal wire joined to the conductor wiring.
[0012]
According to a fourth aspect of the present invention, there is provided a semiconductor device according to the present invention, wherein a semiconductor chip is mounted on the above-described wiring board, and an electrode of the semiconductor chip and a metal protrusion are electrically connected.
[0013]
The semiconductor device of the present invention according to claim 5 is characterized in that the electrode of the semiconductor chip and the metal protrusion are connected by a thin metal wire.
A semiconductor device according to a sixth aspect of the present invention has a plurality of metal protrusions, and the arrangement pitch of the metal protrusions is equal to or less than the arrangement pitch of the electrodes of the semiconductor chip.
[0014]
A semiconductor device according to a seventh aspect of the present invention is characterized in that an electrode of a semiconductor chip and a metal protrusion are connected by a flip chip bonding method.
[0015]
In the semiconductor device according to the eighth aspect of the present invention, a semiconductor chip is fixed to a circuit board having conductor wiring, and an electrode of the semiconductor chip and a part of the conductor wiring of the circuit board are electrically connected by a thin metal wire. The connecting portion between the conductor wire and the fine metal wire is such that the deformed portion at the tip of the fine metal wire covers the surface and the side surface of the conductor wire, and the deformed portion at the tip of the fine metal wire is the insulating portion of the circuit board. It is characterized in that it is formed so as to reach the surface of the insulating portion of the circuit board and is not easily uneven .
[0016]
In the semiconductor device according to the ninth aspect of the present invention, a plurality of conductor wirings are formed on the circuit board, and the arrangement pitch of the connection portions of the conductor wirings with the fine metal wires is equal to or less than the arrangement pitch of the electrodes of the semiconductor chip. It is characterized by this.
[0017]
A semiconductor device according to a tenth aspect of the present invention is characterized in that the deformed portion at the tip of the fine metal wire is formed in a ball shape.
The method of manufacturing a semiconductor device of the present invention according to claim 11, the metal and fixing the semiconductor chip on a circuit substrate having a conductive wiring on the insulating portion, and a part of the conductor wiring and the electrodes of the semiconductor chip connected by thin lines, deformation of the tip of the metal thin wires, covers the surface and sides of the conductor wiring, the steps you to bite into the formed in the insulating portion reaches the insulating portion irregularities, the It is characterized by having.
[0018]
According to a semiconductor device manufacturing method of the present invention as set forth in claim 12 , a plurality of conductor wirings are formed on a circuit board, and the arrangement pitch of the connecting portions with the deformed portions at the tips of the thin metal wires in the conductor wirings is set as the electrode of the semiconductor chip. It is characterized by being equal to or less than the arrangement pitch.
[0019]
According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the deformed portion at the tip of the fine metal wire is formed in a ball shape.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a wiring board according to an embodiment of the present invention, a semiconductor device using the wiring board, and a manufacturing method thereof will be described with reference to the drawings.
[0021]
(Embodiment 1)
FIG. 1 is a top view of a component mounting board as a wiring board according to an embodiment of the present invention, and FIG. 2 is a sectional view thereof. Here, reference numeral 1 denotes an interposer as an insulating portion for forming a circuit board, which is composed of a glass epoxy board, a polyimide board, or the like. The internal electrode 2 (conductor wiring) and the external electrode 4 provided on one surface and the other surface of the interposer 1 are electrically connected to each other through a through hole 10. The internal electrode 2 and the external electrode 4 are made of Cu and usually have a thickness of about 5 to 35 μm. The surface of the internal electrode 2 is plated with Au on a Ni base.
[0022]
The pitch of the arrangement of the plurality of internal electrodes 2 is set to be equal to or less than the pitch of the electrodes 6 of the semiconductor chip 5 mounted on the interposer 1. The width of the internal electrode 2 is set to about 5 to 40 μm because the pitch of the electrodes 6 of the semiconductor chip 5 is about 20 to 100 μm. Such an internal electrode 2 is formed by a method of etching a Cu foil bonded to a glass epoxy substrate or the like of the interposer 1 or a plating method.
[0023]
Reference numeral 3 denotes a bump as a metal protrusion, which is formed so as to cover the surface and side surface of the internal electrode 2 and reach the insulating portion of the interposer 1 as shown in FIGS. 1 and 2. ing. The material of the bump 3 is Au, Cu, solder, Al, Ag, Sn—Ag, Au—Sn, or the like. The size of the bump 3 is determined in accordance with the dimensions of the internal electrodes 2 and the formation pitch thereof. That is, specifically, the bump 3 has a width dimension of about 10 to 50 μm and a thickness of about 10 to 5 μm.
[0024]
As a method of forming the bumps 3, a metal ball is heated and pressed one by one and bonded to the internal electrode 2. For example, the bumps 3 formed by plating or the like on a glass substrate or the like are simultaneously bonded together by the number of the internal electrodes 2. It is possible to use a method such as a method of bonding an Au ball with energy such as ultrasonic waves in a heated and pressurized state using an Au wire and wire bonding technique, and separating the Au ball and the Au wire. At this time, the bump 3 is bonded to the side surface in addition to bonding to the upper surface of the internal electrode 2. Thereby, joining strength can be secured. As shown in FIG. 3, the surface of the interposer 1 is usually provided with minute irregularities 11 for increasing the adhesive strength with the internal electrode 2, and the bumps 3 can bite into the irregularities 11. Thereby, the bonding strength between the bump 3 and the internal electrode 2 can be further increased. In addition, as shown in FIG. 3, when the internal electrode 2 is formed by etching and miniaturized, the cross-section is close to a triangle by over-etching. Even in this case, the bump 3 is bonded to the side surface of the internal electrode 2. In addition, since the unevenness of the surface of the insulating portion of the interposer 1 is also eroded, the bonding strength of the bumps 3 can be sufficiently ensured.
[0025]
(Embodiment 2)
Next, an example of a structure in which a semiconductor chip is mounted on the component mounting board formed as described above will be described with reference to FIGS. 4, 5, and 6. 4, 5, and 6, 5 is a semiconductor chip, 6 is an electrode of the semiconductor chip, and 7 is a bonding wire as a fine metal wire.
[0026]
When mounting the semiconductor chip 5, first, as shown in FIG. 4, the semiconductor chip 5 is fixed to substantially the center of the interposer 1. Examples of the fixing method include bonding with an Ag paste insulating resin. Next, the electrode 6 of the semiconductor chip 5 and the internal electrode 2 of the interposer 1 are connected by the bonding wire 7. The bonding wire 7 is made of Au, Al, Cu or the like, and its wire diameter is about 5 to 20 μm.
[0027]
As a bonding method, a ball bonding method using ultrasonic thermocompression bonding or a wedge bonding method using ultrasonic waves is used. In the case of the ball bonding method, the bonding portion of the bonding wire 7 on the side of the electrode 6 of the semiconductor chip 5 is made into a ball shape, and the bonding of the internal electrode 2 to the bump 3 is made by crushing the bonding wire 7.
[0028]
At this time, since the arrangement pitch of the internal electrodes 2 is equal to or less than the arrangement pitch of the electrodes 6 of the semiconductor chip 5, one side length of the arrangement of the internal electrodes 2 is one side length of the semiconductor chip 5. Less than or equal to Therefore, the outer shape of the interposer 1 can be reduced, and even if the semiconductor chip 5 has a multi-pin structure, the package can be configured to be ultra-small.
[0029]
As a method for bonding the electrode 6 of the semiconductor chip 5 and the internal electrode 2 of the interposer 2, a flip chip bonding method as shown in FIG. 7 can be used in addition to the method using the bonding wire 7 described above. That is, the electrode 6 of the semiconductor chip 5 and the internal electrode 2 of the interposer 2 can be directly bonded without using a bonding wire. 8 is resin for fixing a junction part. As a bonding method in this case, an anisotropic conductive resin bonding method, an Au—Al diffusion bonding method, or the like is used.
[0030]
(Embodiment 3)
Next, a third embodiment of the present invention will be described with reference to FIGS. Here, as shown in FIG. 8, the semiconductor chip 5 is fixed to substantially the center of the interposer 1. The fixing method is the same as that shown in the second embodiment. The electrode 6 of the semiconductor chip 5 and the electrode 2 of the interposer 1 are connected by a bonding wire 7. The arrangement pitch of the internal electrodes 2 of the interposer 1 is equal to or less than the arrangement pitch of the electrodes 6 of the semiconductor chip 5.
[0031]
When bonding the bonding wire 7, the Au ball bonding method is used, and the bonding of the Au ball 9 is set to the internal electrode 2 side of the interposer 1. At this time, as shown in detail in FIG. 9, the Au ball 9 as a deformed portion formed at the tip of the bonding wire 7 is joined to the upper surface and the side surface of the internal electrode 2 of the interposer 1 and the interposer 1. It is formed so as to extend to the insulating portion.
[0032]
Although a substrate formed of an organic material is shown as the interposer 1 described above, a similar effect can be obtained with a ceramic substrate.
[0033]
【The invention's effect】
As described above, according to the present invention, the metal protrusion, that is, the bump or the deformed portion at the tip of the thin metal wire covers not only the surface of the conductor wiring but also the side surface thereof. can achieve strength, also than the deformation of the tip of the bump and the metal thin wires can be obtained formed by further bonding strength bite into the irregularities in the surface of the insulating portion, miniaturization of the semiconductor of the internal electrodes Therefore, an ultra-small semiconductor package can be obtained even with a large number of pins.
[Brief description of the drawings]
1 is a top view of a component mounting board in Embodiment 1 of the present invention. FIG. 2 is a sectional view of the component mounting board in FIG. 1. FIG. 3 is an enlarged sectional view of a bump joint in FIG. 5 is a top view of the semiconductor device according to the second embodiment of the present invention. FIG. 5 is an enlarged vertical sectional view of the bump bonding portion in the semiconductor device of FIG. 4. FIG. 6 is a transverse sectional view of the bump bonding portion of FIG. FIG. 8 is a cross-sectional view of another semiconductor device according to the second embodiment of the present invention. FIG. 8 is a top view of the semiconductor device according to the third embodiment of the present invention. FIG. 9 is a cross-sectional view of the semiconductor device of FIG. FIG. 11 is a cross-sectional view of a main part of the semiconductor device in FIG. 10. FIG. 12 is a top view of a connecting portion in the semiconductor device in FIGS.
DESCRIPTION OF SYMBOLS 1 Interposer 2 Internal electrode 3 Bump 5 Semiconductor chip 6 Electrode 7 Bonding wire 9 Au ball 11 Unevenness

Claims (13)

回路基板を形成する絶縁部と、前記絶縁部により支持された導体配線と、前記導体配線を横切って前記導体配線の両側の前記絶縁部上の領域に亘り形成された金属突起とを有し、
前記絶縁部の表面に凹凸が形成され、前記金属突起は、前記絶縁部に達するように形成されて前記凹凸にくいこんでいることを特徴とする配線基板。It has an insulating portion for forming a circuit board, wherein the conductor wire which is supported by the insulating portion, and both sides of the metal protrusions formed over the region on the insulating portion of the conductor wire across the conductor wire,
Irregularities are formed on the surface of the insulating part, and the metal protrusion is formed so as to reach the insulating part and is hard to be uneven . 金属突起は、Ａｕ、Ｃｕ、Ａｌ、Ｐｂ−Ｓｎ、Ｓｎ−Ａｇ、Ａｕ−Ｓｎのいずれかにて形成されていることを特徴とする請求項１記載の配線基板。  The wiring board according to claim 1, wherein the metal protrusion is formed of any one of Au, Cu, Al, Pb-Sn, Sn-Ag, and Au-Sn. 回路基板の絶縁部上に形成された導体配線の一部において、金属線の先端部に形成した金属球を前記導体配線の表面および側面を覆ってこの導体配線に接合するように変形させるとともに、前記金属球を、前記絶縁部に達するように変形させてこの絶縁部の表面に形成された凹凸にくいこませ、次に前記導体配線に接合した金属球と金属線とを分離することで、前記導体配線上に金属突起を形成することを特徴とする配線基板の製造方法。 Oite the part of the conductor wiring formed on an insulating portion of the circuit board, is deformed so that metal balls formed at the tip of the metal wire over the surface and side surfaces of the conductor wiring is joined to the conductor interconnect The metal sphere is deformed so as to reach the insulating portion, and the unevenness formed on the surface of the insulating portion is hardened, and then the metal sphere bonded to the conductor wiring and the metal wire are separated. A method of manufacturing a wiring board, comprising forming a metal protrusion on the conductor wiring. 請求項１または２記載の配線基板に半導体チップか搭載され、この半導体チップの電極と金属突起とが電気的に接続されていることを特徴とする半導体装置。  3. A semiconductor device, wherein a semiconductor chip is mounted on the wiring substrate according to claim 1, and an electrode of the semiconductor chip and a metal protrusion are electrically connected. 半導体チップの電極と金属突起とが金属細線によって接続されていることを特徴とする請求項４記載の半導体装置。  5. The semiconductor device according to claim 4, wherein the electrode of the semiconductor chip and the metal protrusion are connected by a thin metal wire. 複数の金属突起を有し、金属突起どうしの配列ピッチが半導体チップの電極の配列ピッチと同等以下であることを特徴とする請求項４または５記載の半導体装置。  6. The semiconductor device according to claim 4, wherein the semiconductor device has a plurality of metal protrusions, and an arrangement pitch between the metal protrusions is equal to or less than an arrangement pitch of electrodes of the semiconductor chip. 半導体チップの電極と金属突起とがフリップチップボンディング方式によって接続されていることを特徴とする請求項４記載の半導体装置。  5. The semiconductor device according to claim 4, wherein the electrode of the semiconductor chip and the metal protrusion are connected by a flip chip bonding method. 導体配線を有する回路基板に半導体チップが固定され、前記半導体チップの電極と前記回路基板の導体配線の一部とが金属細線で電気的に接続され、この導体配線と金属細線との接続部は、金属細線の先端の変形部が、前記導体配線の表面および側面を覆うとともに、前記金属細線の先端の変形部が、前記回路基板の絶縁部に達するように形成されて、この回路基板の絶縁部の表面に形成された凹凸にくいこんでいることを特徴とする半導体装置。A semiconductor chip is fixed to a circuit board having conductor wiring, and an electrode of the semiconductor chip and a part of the conductor wiring of the circuit board are electrically connected by a thin metal wire, and a connection portion between the conductor wiring and the thin metal wire is The deformed portion at the tip of the thin metal wire covers the surface and the side surface of the conductor wiring, and the deformed portion at the tip of the fine metal wire is formed so as to reach the insulating portion of the circuit board. A semiconductor device characterized in that the unevenness formed on the surface of the portion is hard to be recessed . 回路基板に複数の導体配線が形成され、この導体配線における金属細線との接続部分の配列ピッチが半導体チップの電極の配列ピッチと同等以下であることを特徴とする請求項８記載の半導体装置。  9. The semiconductor device according to claim 8, wherein a plurality of conductor wirings are formed on the circuit board, and an arrangement pitch of connection portions of the conductor wirings with the fine metal wires is equal to or less than an arrangement pitch of the electrodes of the semiconductor chip. 金属細線の先端の変形部はボール状に形成されていることを特徴とする請求項８または９記載の半導体装置。  10. The semiconductor device according to claim 8, wherein the deformed portion at the tip of the thin metal wire is formed in a ball shape. 絶縁部上に導体配線を有する回路基板に半導体チップを固定する工程と、
前記半導体チップの電極と前記導体配線の一部とを金属細線で接続して、前記金属細線の先端の変形部が、前記導体配線の表面および側面を覆うとともに、前記絶縁部に達してこの絶縁部に形成された凹凸にくいこむようにする工程と、
を有することを特徴とする半導体装置の製造方法。Fixing a semiconductor chip to a circuit board having conductor wiring on an insulating portion;
The electrode of the semiconductor chip and a part of the conductor wiring are connected by a fine metal wire, and the deformed portion at the tip of the fine metal wire covers the surface and the side surface of the conductive wire, and reaches the insulating portion to achieve this insulation. a step you to bite into the formed irregularities parts,
A method for manufacturing a semiconductor device, comprising: 回路基板に複数の導体配線を形成し、この導体配線における金属細線の先端の変形部との接続部分の配列ピッチを半導体チップの電極の配列ピッチと同等以下とすることを特徴とする請求項１１記載の半導体装置の製造方法。  12. A plurality of conductor wirings are formed on a circuit board, and an arrangement pitch of connecting portions of the conductor wirings with a deformed portion at the tip of a thin metal wire is made equal to or less than an arrangement pitch of electrodes of a semiconductor chip. The manufacturing method of the semiconductor device of description. 金属細線の先端の変形部をボール状に形成することを特徴とする請求項１１または１２記載の半導体装置の製造方法。  13. The method of manufacturing a semiconductor device according to claim 11, wherein the deformed portion at the tip of the thin metal wire is formed in a ball shape.
JP2002030182A 2002-02-07 2002-02-07 Wiring board, semiconductor device using the same, and manufacturing method thereof Expired - Fee Related JP3824545B2 (en)

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