TW200903763A - Inter-connecting structure for semiconductor device package and method of the same - Google Patents

Inter-connecting structure for semiconductor device package and method of the same Download PDF

Info

Publication number
TW200903763A
TW200903763A TW096131727A TW96131727A TW200903763A TW 200903763 A TW200903763 A TW 200903763A TW 096131727 A TW096131727 A TW 096131727A TW 96131727 A TW96131727 A TW 96131727A TW 200903763 A TW200903763 A TW 200903763A
Authority
TW
Taiwan
Prior art keywords
substrate
die
semiconductor package
package structure
interconnect structure
Prior art date
Application number
TW096131727A
Other languages
English (en)
Other versions
TWI344199B (en
Inventor
Wen-Kun Yang
Diann-Fang Lin
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200903763A publication Critical patent/TW200903763A/zh
Application granted granted Critical
Publication of TWI344199B publication Critical patent/TWI344199B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Description

200903763 九、發明說明： 【發明所屬之技術領域】 本發明係有關—種晶圓級封裝_ 關於-種晶圓級封裝之内連線結構。 特別疋 【先前技術】 :半導體裝置領域中，褒置之密度持續增
鮮錫凸塊陣驗二上而^在覆晶接合方法中， 用銲錫化人二 。銲錫凸塊之形成係利 之=:4材料配置於銲錫罩幕層，以產生所需銲錫凸塊 曰曰粒封震之功能包含電源分配、訊號分配、散執、 = 由於半導體結構趨向複雜化，而-般傳統 =術，例如導線封裝、軟性封裝、剛性封裳技術，已益法 達成於晶粒上產生具有高密度元件之小型晶粒。 通常’BGA封裝提供高密度連線，其包含訊號路徑 傳統結構具有高阻抗以及不良散熱，因此導致較差散執能 力。隨著龍密度之增加，將内部^件產生之熱導出益、形 覆晶技術為已知電子訊號連接晶粒技術，晶粒主動面 朝下連接表面上複數之接觸墊（習知技術係位於旁側）。 ，訊連接位於覆晶之表面，凸塊包含錫球以及/或銅、金使 得其機械與電性連接於基板之上。位於增層後之錫球具有 凸塊高度約為50-100微米，晶粒反轉配置於基板表面，其 凸塊對準基板之接觸墊，如第一圖所示。若為錫球，其將 200903763 被焊於基板接合塾上，錫接合成本不高，但當基於熱機械 應力所導致毁損或孔洞時，其會增加阻抗。此外，錫球為 錫合金組成，以鉛為基礎之材質將因為環保意識且會產生 有毒物質之釋放而不再受到歡迎。一般，填充材質被用以 降低介於晶片與基板間熱膨脹所產生之熱應力。 再者，由於一般封裝技術必須先將晶圓上之晶粒分割 為個別晶粒，再將晶粒分別封裝，因此上述技術之製程^ ^分費時。因為晶粒封裝技術與積體電路之發展有密切關 聯，因此封裝技術對於電子元件之尺寸要求越來越高。基 於上述之理由，現今之封裝技術已逐漸趨向採用球閘陣列 封裝（繼）、覆晶球閘陣列封裝、晶片尺寸封裝、晶圓級 封裝之技術。應可理解「晶圓級封裝（WLp)」指晶圓上所 有封裝及父互連接結構，如同其他製程步驟，係於切割為 :固別晶粒之前進行。一般而言，在完成所有配裝製程：封 扃製程之後，由具有複數半導體晶粒之晶圓中將個別半導 <體封裝分離。上述晶圓級封裝具有極小之尺寸及良好之電 性。 美國專利號第6,271,469號所揭露之具有增層（bmid =layer)之封裝結構便遇到上述熱膨脹係數不匹配之問 題如第一圖所示。此電子封裝包含晶粒102 ’具有主動 面。封裝穋體112配置於晶粒1〇2肖遭。其中所述之封裝 膠，至夕具有—表面大致上與晶粒主動表面相當平整。第 ;丨電層118配置於封裝膠體112與晶粒1〇2之上。至少 導電層124配置於第-介電層118之上。導電層124連 200903763 接日日粒之主動面。第二 別形成於晶粒102之上 126中以利於耦合導線 以及錫球13 8。 二介電層126以及第三介電層Π6分 上。介層穿孔132形成於第二介電層 象124。接合墊134連接介層穿孔132 上述技術牽涉過多堆疊增層形成於晶粒表面上。其不 ”而要平坦化增層步驟，更須高精度之光微影設備以完成 封裝步驟，但其也易於毀損晶粒表面。主要在於欠缺緩衝 層界於晶粒與錫球間，因此此架構造成低 問題。 非又 因此’本發明提供一種具有内連結構之覆晶結構已克 服上述問題以提供較佳可靠度。 【發明内容】 月之目的係在於提供一種擴散式晶圓級封裝 (fan-out WLP)，装 1 古他 a、^ 、一有低成本、面良率以及良好熱膨脹係 數匹配。 本發明之另一目的係在於提供一種封裝之内連線結 構，以增進可靠度與減小裝置之體積。 人.f發明揭露-種半導體封裝結構之内連線結構，包 3 · 一基& ’具有預先製作之導線於其中；-晶粒，且有 接觸塾P動表面…黏合材質，將該晶粒黏合於該基板 二中°亥基板包含通孔貫穿該基板以及該黏合材質； 電材質填充於該通孔以利於連接該接觸墊以及該導線。 “ 〇 3核^黏膠位於該晶粒背面與該黏合材質上，以及導 電凸塊耦合該導線；支撐基板位於該核心黏膠之上。導體 200903763 層位^亥核心黏膠及/或該晶粒背面之上。其中該導體層包 3銅箔、濺鍍或電鍍之銅/鎳/金合金。其中更包含斜頂結 構之封膜單元，位於該晶粒以及該黏合材質之上，斜頂結 構之角度約為水平面起30_6〇度。其中該封膜單元為液: 化合物或封膠化合物。 “ 一種形成半導體封裝之内連線結構之方法，包含： 提供一基板具有電路或導線位於其中； r 形成黏合材質於其上； 以微對位之置放裝置將晶粒配置於該 以覆晶方式配置； 上 形成核心黏膠於該晶粒背面，於填入該晶粒週遭空隙； 形成通孔於該基板以曝露接觸墊； 以物理氣相沉積或化學氣相沉積製作金屬種子層於該 接觸墊上； 形成光阻於該晶粒之上； I 卩電鍍製私製作導電材質於該通孔中，以形成該内連 線結構並與該接觸塾搞合。 更包含熱處理該黏合材質；在曝露出金屬墊之後包含 清潔該金屬塾。其中該金屬導電包含Ti/Cu，Cu/Au，
Cu/Ni/Au或Sn/Ag/Cu。完成内連結構後更包含去除光阻 以及回蝕刻該金屬層。 【實施方式】 本發明將配合其較佳實施例與後附之圖式詳述於下。 應可理解，本發明中之較佳實施例係僅用以說明，而非用 200903763 以限定本發明。此外，除文中之較佳實施例外，本發明亦 可廣泛應用於其他實施例，並且本發明並不限定於任何實 施例，而應視後附之申請專利範圍而定。 本發明揭露一種半導體封裝之結構，包含基板、導線、 以及金屬内連線結構，如第三圖所示。 第三圖係為本發明基板100之截面，基板1〇〇可以為 金屬、玻璃、陶竟、塑膠、PCB或PI。厚度約為4〇_7〇 微米。可為多層結構基板，晶粒1〇5藉由黏著材質黏 於其上，黏著材質110其具有彈性以吸收熱應力。黏著材 質110得只覆蓋晶粒大小之區域。内連線結構丨15回填形 成於基板100内之通孔，得藉由雷射鑽孔製作。内連線結 構115耦合到晶片之預定接觸金屬墊1〇2，其材質可為鋁 墊、銅墊或其他金屬，其係於形成增層後製作。導線 配至於基板之底部或上部表面’且輕合到内連線結構 115。導電凸塊125耦合至導線12〇之末端。 v. 第三圖所示，導線120形成於基板底下（或内部）。例 如，導、線120以金、銅、銅鎳或類似材質組成。可以藉由 電鍍技術、塗佈絲刻方法製作。銅電錢程序持續進^直 到所遇之厚度。導㈣〇延伸出承載晶粒之區域，、核心黏 膠層咖e Paste material)! 3〇 ’例如彈性核心黏膠層係填充 且覆蓋晶粒、基板或黏著材f 11〇。可以藉由樹脂、化合 物、梦膠或環氧樹脂構成。 參閱第四圖，其顯示另一實施例，支揮基板135貼附 於核心黏膠層（core paste matedal) 13〇，以提供封裝體之支 200903763 。、另例為導體層140塗佈或覆蓋於核心黏膠層i 3 〇上 作為散熱器。可以藉由銀㈣合銅箱薄片製作、_技術、 電鍍銅7鎳/金製作導體層140,如第五圖所示。 參閱第六圖，封膜單元145係利用液態化合物或封膠 化合物取代核心黏勝層13〇。曰曰曰粒高度約& 微米， 自^膜單70 145至晶粒表面尺寸大約30-100微米。基板與 姑者材質厚度合計大約40_議微米。因此整 度約為大請-彻微米。值得注意者係為封膜單元14旱5 具有斜頂，傾斜結構之角度θ約為3g_6q《，進而提供較 佳之散熱路徑。 參閱第七圖，基板（圓或矩形）100具有電路形成於其 内，黏合材質（較好為具有彈性以吸收熱應力，基於熱膨服 係數介於基板與H粒不匹配問題）UG ’塗佈於基板，隨 之熱處理該黏合材質11Q。晶粒1G5以微對準裝置置放於 基板⑽之上。下一步驟為自晶粒背面印刷或塗佈核心黏 膠層130。導體層140 一般則是則是利用面板壓合技術 (panel bonding)使其與晶粒背面相互結合。隨之熱處理以 形成“panei wafer”，如第七圖所示。下一步驟為使用雷 射穿孔技術鑿穿通孔（亦可於面板壓合前實施），以及彤成 金屬種子層，隨後㈣光阻形成通孔及連接至基板電路。 隨後去除光阻後，使用電鍍及蝕刻種子層以利於製作内連 結構115。需注意者金屬墊可為鋁墊或其他金屬墊，通孔 區域非為製作凸塊之區域’參第八圖以及第九圖。 隨後，凸塊置於基板之上，且加以紅外線熱流步驟以 200903763 製作傳輸終端結構’如第十圖所示。執行面板級（Panel level) 測試以及切割所述（PI)基板以及核心黏膠層以分離個別單 第十一圖係為根據本發明之内連線結構之一實施例， 其包含晶粒105，具有金屬接觸墊1〇2位於主動表面，黏 合材質110位於晶粒105底面，具有預製電路之基板1〇〇 =以承載晶粒105，以及通孔115形成於基板内，導電材 質經由通孔結構115耦合至晶粒1〇5之金屬接觸墊1〇2以 聯繫基板電路。 本發明提供簡單之製程，無需傳統增層結構於 她心❹（增層意謂電路，其預先製作於基板以預防在 增層過程中損壞晶片）。且本發明無須對準玉具，對準圖案 ，常位於基板表面於製作電路過程中。晶粒主動面貼附於 二板每性黏著層’本發明無須底部填充材質，且本發明具 =路之PI基板採大面積面板。且本發明採用簡易塗佈乾 而非溼式光阻，以形成導電材質於通孔區域。晶 粒可被封裝於其中’只需開孔金屬電區域，因此主動表面 極薄(無須錫球高度，：晶上率，且封裝體之尺寸 於錫球高度因素ϋ 非㈣而不會受限 本發明也藉由採用强料卖 力，以提供高可#。填層做為緩衝層以釋放應 強化機械力。其顯示於基 ：)王覆蓋通孔’以 前增層技術截秋不n a: 無熱應力衝擊，其與目 支统、、不同。介於ΡΙ基板與 11 200903763 係數相當，其消除熱問題， 明有效克服熱管理問題。 因此，相較於傳統技術，本發 本毛明以較佳實施例說明如上 發明所主張之專利權利矿圖甘“…並非用以限疋本 • ，〜 圍。其專利保護範圍當視後附之 者，在不脫離太直： 。凡熟悉此領域之技藝 均屬於本二t: 或範圍内’所作之更動或潤飾， 屬於本毛月所揭示精神下所完成之等效改變或設計 應包含在下述之申請專利範圍内。 【圖式簡單說明】 第一圖係為根據先前技術之剖面示意圖。 第二圖係為根據先前技術之剖面示意圖。 第二圖係為根據本發明之剖面示意圖。 第四圖係為根據本發明之剖面示意圖。 第五圖係為根據本發明之剖面示意圖。 第六圖係為根據本發明之示意圖。 第七至十圖係為根據本發明之製程示意圖。 第十一圖係為根據本發明之内連結構剖面示意圖。 【主要元件符號說明】 先前技術 晶粒102、封裝膠體112、第一介電層118、導電層124、 第二介電層126、介層穿孔132、接合墊135、第三介 電層136、錫球138 本發明 基板100、晶粒105、黏著材質11 〇、内連結構11 $、 12 200903763 導線120、導電凸塊125、核心黏膠130、支撐基板135、 導體層140、封膜單元145 f 13

Claims (1)

  1. 200903763 十、申請專利範圍： 1. 一種半導體封裝結構之内連線結構，包含： 一基板，具有預先製作之導線於其中； 一晶粒，具有接觸墊於主動表面； 一黏合材質，將該晶粒黏合於該基板之上，其 中該基板包含通孔貫穿該基板以及該黏合材 質； 導電材質填充於該通孔以利於連接該接觸墊 以及該導線。 2. 如請求項 1所述之半導體封裝結構之内連線 結構，更包含核心黏膠位於該晶粒與該黏合材 質上，以及包含導電凸塊耦合該導線。 3. 如請求項 2所述之半導體封裝結構之内連線 結構，更包含支撐基板位於該核心黏膠之上。 4. 如請求項 2所述之半導體封裝結構之内連線 結構，更包含導體層位於該核心黏膠之上。 5. 如請求項 4所述之半導體封裝結構之内連線 結構，其中該導體層包含銅箔、濺鍍或電鍍之 銅/鎳/金合金。 14 200903763 6. 如請求項 1所述之半導體封裝結構之内連線 結構，其中更包含斜頂結構之封膜單元，位於 該晶粒、以及該黏合材質之上。 7. 如請求項 6所述之半導體封裝結構之内連線 結構，其中更包含斜頂結構之角度約為3 0 - 6 0 度。 8. 如請求項 6所述之半導體封裝結構之内連線 結構，其中該封膜單元包含液態化合物或封膠 化合物。 9. 一種形成半導體封裝結構之内連線結構之方 法，包含： 提供一基板具有電路於其中； 形成黏合材質於該基板之上； 以微對位之置放裝置將晶粒配置於該黏合材 質之上，以覆晶方式配置； 形成核心黏膠於該晶粒背面，與填入該晶粒週 遭空隙； 形成通孔於該基板以暴露接觸墊； 以物理氣相沉積或化學氣相沉積製作金屬種 子層於該接觸墊上； 形成光阻於該晶粒之上； 15 200903763 以電鍍製程製作金屬導體於該通孔中，以形成 該内連線結構與該接觸墊耦合。 10. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法，更包含熱處理該黏合材質。 11. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法，更包含在曝露金屬墊之後清 / 潔該金屬墊。 12. 如請求項 9所述之形成半導體封裝結構之内 連線結構之方法，其中該金屬種子層包含 Ti/Cu, Cu/Au, Cu/Ni/Au 或 Sn/Ag/Cu。 13.如請求項 9所述之形成半導體封裝結構之内 連線結構之方法，更包含去除光阻以及回蝕刻 該金屬層。 16
TW096131727A 2007-07-06 2007-08-27 Inter-connecting structure for semiconductor device package and method of the same TWI344199B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/773,993 US20090008777A1 (en) 2007-07-06 2007-07-06 Inter-connecting structure for semiconductor device package and method of the same

Publications (2)

Publication Number Publication Date
TW200903763A true TW200903763A (en) 2009-01-16
TWI344199B TWI344199B (en) 2011-06-21

Family

ID=40092772

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096131727A TWI344199B (en) 2007-07-06 2007-08-27 Inter-connecting structure for semiconductor device package and method of the same

Country Status (7)

Country Link
US (1) US20090008777A1 (zh)
JP (1) JP2009033153A (zh)
KR (1) KR20090004775A (zh)
CN (1) CN101339928B (zh)
DE (1) DE102008031358A1 (zh)
SG (1) SG148987A1 (zh)
TW (1) TWI344199B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8446243B2 (en) * 2008-10-31 2013-05-21 Infineon Technologies Austria Ag Method of constructing inductors and transformers
TW201131705A (en) * 2010-03-03 2011-09-16 Advanced Chip Eng Tech Inc Conductor package structure and method of the same
US20130214418A1 (en) * 2012-01-12 2013-08-22 King Dragon International Inc. Semiconductor Device Package with Slanting Structures
US20130181227A1 (en) * 2012-01-12 2013-07-18 King Dragon International Inc. LED Package with Slanting Structure and Method of the Same
CN102867759B (zh) * 2012-08-17 2015-04-29 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
TWI492344B (zh) * 2013-04-09 2015-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9331038B2 (en) 2013-08-29 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor interconnect structure
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069407A (en) * 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6569712B2 (en) * 2001-10-19 2003-05-27 Via Technologies, Inc. Structure of a ball-grid array package substrate and processes for producing thereof
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US20040088855A1 (en) * 2002-11-11 2004-05-13 Salman Akram Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
US7309622B2 (en) * 2005-02-14 2007-12-18 Stats Chippac Ltd. Integrated circuit package system with heat sink
US20070096285A1 (en) * 2005-11-02 2007-05-03 Chin-Tien Chiu Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor die

Also Published As

Publication number Publication date
JP2009033153A (ja) 2009-02-12
TWI344199B (en) 2011-06-21
KR20090004775A (ko) 2009-01-12
DE102008031358A1 (de) 2009-01-08
SG148987A1 (en) 2009-01-29
CN101339928A (zh) 2009-01-07
US20090008777A1 (en) 2009-01-08
CN101339928B (zh) 2011-04-06

Similar Documents

Publication Publication Date Title
TW200903763A (en) Inter-connecting structure for semiconductor device package and method of the same
TWI402939B (zh) 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法
TWI298531B (en) Bump structure
TWI533412B (zh) 半導體元件封裝結構及其形成方法
TW594958B (en) Semiconductor device and manufacturing method thereof
US6744122B1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
TWI374531B (en) Inter-connecting structure for semiconductor device package and method of the same
TWI460844B (zh) 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法
TW200828564A (en) Multi-chip package structure and method of forming the same
JP5942823B2 (ja) 電子部品装置の製造方法、電子部品装置及び電子装置
TW200830502A (en) Structure of super thin chip scale package and method of the same
TW201013858A (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP2003249601A (ja) 半導体装置用基板及びその製造方法及び半導体パッケージ
JP3687435B2 (ja) 半導体チップおよびその製造方法、半導体装置、コンピュータ、回路基板ならびに電子機器
TW200843055A (en) Semiconductor device package to improve functions of heat sink and ground shield
JP2008218926A (ja) 半導体装置及びその製造方法
TW200939428A (en) Multi-chip package structure and method of fabricating the same
WO2018171099A1 (zh) 集成有功率传输芯片的封装结构的封装方法
TW200830524A (en) RF module package
CN107104090B (zh) 重新布线层、具有所述重新布线层的封装结构及制备方法
TW201121015A (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
TW200837915A (en) Semiconductor device package
CN114975242B (zh) 一种2.5d封装结构的制备方法
JP6319013B2 (ja) 電子装置及び電子装置の製造方法