WO2018171099A1 - 集成有功率传输芯片的封装结构的封装方法 - Google Patents

集成有功率传输芯片的封装结构的封装方法 Download PDF

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WO2018171099A1
WO2018171099A1 PCT/CN2017/095406 CN2017095406W WO2018171099A1 WO 2018171099 A1 WO2018171099 A1 WO 2018171099A1 CN 2017095406 W CN2017095406 W CN 2017095406W WO 2018171099 A1 WO2018171099 A1 WO 2018171099A1
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chip
power transmission
power
layer
transmission chip
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PCT/CN2017/095406
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English (en)
French (fr)
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林章申
林正忠
何志宏
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中芯长电半导体（江阴）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the invention belongs to the technical field of semiconductor packaging, and relates to a packaging method of a package structure integrated with a power transmission chip.
  • Power transfer systems are required for all computing and communication systems.
  • the power transfer system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power transfer system determines the power loss of the down-conversion, and the number of power transfer rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power transmission tracks requires copying more power transmission components, which will increase the number of components, increase the size of the board, increase the number of layers of the board, increase the system size, cost and weight.
  • an object of the present invention is to provide a packaging method of a package structure integrated with a power transmission chip for solving the problem of low power transmission efficiency and available voltage of different voltage tracks in the existing power transmission system. Less problem.
  • the present invention provides a packaging method of a package structure integrated with a power transmission chip, the package structure including an electrical chip and a power transmission chip connected under the power chip;
  • the power transmission chip is configured to convert a voltage of the external power source into a plurality of voltages required by the power chip, and provide a plurality of power supply tracks that are connected to the power chip;
  • the packaging method includes the following steps:
  • An active component and a passive component of the power transmission chip are placed on the adhesion layer, wherein the active component and the passive component have one side of the pad in contact with the adhesion layer;
  • a conductive portion of the rewiring layer is connected to the conductive pillar and the pad to achieve the An electrical connection between the active component and the passive component, and providing a plurality of power supply tracks that are connected to the power chip;
  • a plurality of second bump structures connected to the conductive pillars are formed on a surface of the plastic sealing layer on a side opposite to the pads.
  • the voltage of the external power source is higher than the voltage required by the power chip.
  • the active component comprises a controller and a buck converter
  • the passive component comprises a capacitor, an inductor and a resistor.
  • the method further includes filling the gap between the power chip and the wiring layer by using an underfill. a step, and a step of wrapping the surrounding electrical chip with a molding material.
  • the rewiring layer includes a dielectric layer and at least one metal wiring and at least one layer of conductive plugs formed in the dielectric layer; the metal wiring is implemented by the conductive plug An electrical connection of the active component, the passive component, and the conductive pillar, and when a plurality of metal wirings are formed in the dielectric layer, the interlayer electrical connection is realized by the conductive plug between the multiple metal wirings.
  • the first bump structure comprises microbumps.
  • the second bump structure comprises a ball grid array solder ball.
  • the power chip is an application specific integrated circuit.
  • the method of forming the plastic seal layer includes any one or more of compression molding, transfer molding, liquid sealing molding, vacuum lamination, and spin coating.
  • the method of forming the through hole includes any one or more of laser drilling, mechanical drilling, reactive ion etching, and nano imprinting.
  • the method of forming the conductive pillars comprises one or more of electroplating, electroless plating, silk screen printing, wire bonding.
  • the present invention provides a new packaging method in which a three-dimensional chip stacking technology is used to integrate a power chip and a power transfer chip in a package structure, which has the following beneficial effects:
  • the power-on chip may be an Application Specific Integrated Circuit (ASIC).
  • ASIC Application Specific Integrated Circuit
  • the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the power transmission chip which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • FIG. 1 is a process flow diagram showing a packaging method of a package structure integrated with a power transmission chip of the present invention.
  • FIG. 2 is a schematic view showing a carrier for a package method of a package structure integrated with a power transmission chip of the present invention.
  • FIG. 3 is a schematic view showing an encapsulation method of a package structure integrated with a power transmission chip of the present invention forming an adhesion layer on the carrier.
  • FIG. 4 is a schematic diagram showing a packaging method of a power transmission chip-integrated package structure of the present invention, in which an active component and a passive component of the power transmission chip are placed on the adhesion layer.
  • FIG. 5 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a plastic seal layer on the adhesion layer.
  • FIG. 6 is a schematic view showing the encapsulation method of the package structure integrated with the power transmission chip of the present invention for removing the carrier and the adhesion layer.
  • FIG. 7 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a conductive pillar in the plastic seal layer.
  • FIG. 8 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a rewiring layer of the power transmission chip.
  • FIG. 9 shows a packaging method of a package structure integrated with a power transmission chip of the present invention through a plurality of first bump structures
  • the power chip is connected to the rewiring layer, and a schematic diagram of the gap between the power chip and the wiring layer is filled by an underfill.
  • FIG. 10 is a schematic view showing a packaging method of a package structure integrated with a power transmission chip of the present invention, which is wrapped around a periphery of the power chip by a molding material.
  • FIG. 11 is a schematic view showing a packaging method of a package structure integrated with a power transmission chip of the present invention, and forming a plurality of second bump structures connected to the conductive pillars.
  • the invention provides a packaging method of a package structure integrated with a power transmission chip.
  • the package structure includes an electrical chip 5 and a power transmission chip 3 connected under the power chip 5 .
  • the power transmission chip 3 is configured to convert a voltage of an external power source into the power chip. 5 required multiple voltages, and providing a plurality of power supply tracks that are connected to the power chip 5.
  • the packaging method of the present invention utilizes the power transmission chip 3 as an active 2.5D interposer, and integrates the power chip 5 on an active 2.5D interposer through microbumps or other bump structures to obtain a three-dimensional stacked chip structure.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which can eliminate parasitic resistance on the package substrate, thereby improving power transmission efficiency, improving power control response time, and improving fidelity.
  • the power transmission chip includes an active component 301, a passive component 302, a plastic encapsulation layer 304, a conductive pillar 305, and a rewiring layer 306.
  • FIG. 1 is a process flow diagram of a packaging method of a package structure integrated with a power transmission chip according to the present invention, including the following steps:
  • S6 forming a rewiring layer of the power transmission chip on a surface of the plastic sealing layer on the same side as the pad; and electrically connecting the conductive portion of the rewiring layer to the conductive pillar and the pad to realize Electrical connection between the active component and the passive component, and providing a plurality of power supply tracks that are connected to the power chip;
  • step S1 is performed: a carrier 1 is provided, and an adhesion layer 2 is formed on the carrier 1.
  • the material of the carrier may be selected from one or more of glass, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 1 may be of a flat type, for example, a glass circular plate having a certain thickness.
  • the adhesive layer 2 functions to adhere and fix the components placed thereon, and when the carrier 1 is subsequently removed, the adhesive layer 2 is also removed.
  • the adhesive layer 2 may be a UV tape or a thermal material, wherein the UV tape may have a reduced adhesive strength under illumination of a specific wavelength, so that the carrier is easily peeled off. When the hot material is heated at a certain temperature, the adhesion strength is lowered, so that the carrier is easily peeled off.
  • the adhesive layer 2 can also be combined with a UV adhesive and a thermal material.
  • step S2 is performed to place the active component 301 and the passive component 302 of the power transmission chip 3 on the adhesion layer 2, wherein the active component 301 and the passive component 302 One side having the pad 303 is in contact with the adhesion layer.
  • one side of the active element 301 having the pad 303 is referred to as a front side, and the other side opposite thereto is referred to as a back side.
  • the passive component 302. the active component 301 and the passive component 302 are placed face down on the adhesive layer 2 so as to be adhered and fixed to the carrier.
  • a Die Attach Film (DFA) is attached to the back surface of the wafer including a plurality of Dies, or the adhesive film is not attached, and then dicing to obtain a plurality of independent dies (ie, The active component 301 or the passive component 302) is then picked up and placed on the adhesive layer 2 to temporarily fix the die on the carrier 1.
  • the adhesive film may be a UV film, and the use of a specific wavelength of light/heating of the film after cutting the wafer may reduce the adhesion strength of the film, so that the chip is easily removed from the film.
  • the function of the power transmission chip 3 is to convert the voltage of the external power source into a plurality of voltages required by the power chip 5, and provide a plurality of power supply tracks that are connected to the power chip 5.
  • the voltage of the external power source is higher than the voltage required by the power chip, and the voltage of the external power source is hereinafter referred to as a high voltage, and the voltage required for the power chip is a low voltage.
  • the active component 301 includes a controller and a buck converter;
  • the passive component 302 includes a capacitor 3021, an inductor 3021, and a resistor (not shown).
  • the buck converter can be converted into tens of thousands of low voltages by high voltage, and the low voltage can form a plurality of power supply tracks through the subsequently formed conductive pillars and rewiring layers, and is formed by subsequent The first bump structure is docked with the top power chip.
  • step S3 is performed: forming the active component 301 and the passive element on the adhesion layer 2
  • the plastic seal layer 304 of the member 302 and the plastic seal layer are ground to thin the plastic seal layer.
  • the method of forming the plastic sealing layer 304 includes any one or more of compression molding, transfer molding, liquid sealing molding, vacuum lamination, spin coating, or other suitable methods.
  • the molding material includes suitable materials such as epoxy resin, liquid thermosetting epoxy resin, and plastic.
  • the plastic sealing layer is thinned until the back surface of the active component and the passive component is exposed. Since the active component and the passive component have no pads on the back side, a certain thickness of the molding material may be retained on the back side of the active component and the passive component, and the scope of protection of the present invention should not be unduly limited herein.
  • the grinding process can employ a mechanical grinding process, a chemical polishing process, an etching process, any combination thereof, and/or the like.
  • step S4 is performed to remove the carrier 1 and the adhesion layer 2 to expose the pad 303.
  • the carrier 1 may be removed by one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, and mechanical peeling; preferably, in the embodiment, the adhesive layer 2 may be removed by The carrier 1 was peeled off.
  • step S5 is performed: forming a plurality of through holes penetrating the plastic sealing layer up and down, and filling the through holes with a conductive material to obtain a conductive pillar 305.
  • the Through Active-interposer Via may be fabricated by any one or more of laser drilling, mechanical drilling, reactive ion etching, nanoimprinting, or other suitable methods.
  • the via fill material can be solder or copper.
  • the TAV fill can be formed by any one or more of electroplating, electroless plating, silk screen printing, wire bonding, or other suitable metal deposition process.
  • step S6 is performed to form a rewiring layer 306 of the power transmission chip 3 on the same side of the molding layer 304 as the pad 303; a conductive portion of the rewiring layer 306.
  • the conductive pillar 305 and the pad 303 are connected to realize electrical connection between the active component 301 and the passive component 302, and a plurality of power supply tracks that are connected to the power chip 5 are provided.
  • the rewiring layer includes a dielectric layer 3061 and at least one metal connection 3062 and at least one layer of conductive plugs 3063 formed in the dielectric layer; the metal connection 3062 passes through the conductive plug 3063 Electrical connection with the active component 301, the passive component 302, and the conductive pillar 305 is achieved, and when the multilayer metal wiring 3062 is formed in the dielectric layer 3061, the multilayer metal wiring 3062 passes between The conductive plugs 3063 implement interlayer electrical connections.
  • the material of the metal wiring 3062 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wiring 3062 may be a Cu wire, and the seed layer of the Cu wire may be a Ti/Cu layer.
  • the method of forming the metal wiring 182 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • a through hole may be formed in the dielectric layer 3061 by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting, or other suitable opening method, and then the through hole
  • the conductive plug 3063 can be formed by filling a metal material; the material of the conductive plug 3063 can be solder or Cu, and the filling method can be electrolytic plating, electroless plating, screen printing, wire bonding or other suitable in the through hole. A method of filling a conductive material.
  • step S7 is performed to connect the power chip 5 and the rewiring layer through a plurality of first bump structures 4 to realize docking of the power chip 5 and the plurality of power supply tracks. .
  • the power chip includes, but is not limited to, an ASIC Die.
  • the first bump structure 4 may adopt a mico-bump or other suitable bump structure.
  • the power chip 5 may be soldered to the rewiring layer 306 via a plurality of first bump structures 4 by processes such as ultrasonic bonding, thermocompression bonding, or conventional reflow soldering.
  • the method further includes filling the power chip 5 and the wiring layer 306 with an underfill.
  • the step of the gap is simply the meaning of underfill.
  • the conventional definition is to use a chemical glue (the main component is epoxy resin) to underfill the chip.
  • the bottom of the chip has a large gap (generally covering 80). Filled more than %) to achieve the purpose of reinforcement and enhance the drop resistance of the package structure.
  • the underfill method may be a capillary underfill or a Molding UnderFill (MUF).
  • capillary filling is the use of capillary action to make the glue flow rapidly through the bottom of the chip, and the minimum space for capillary flow is 10um. This also meets the minimum electrical characteristics between the pad and the solder ball in the soldering process, because the glue does not flow through the gap below 4um, thus ensuring the electrical safety characteristics of the soldering process.
  • a step of wrapping the periphery of the power chip 5 by a molding material 7 is also included.
  • step S8 is performed to form a plurality of second bump structures 8 connected to the conductive pillars on a surface of the plastic sealing layer on the side opposite to the pads.
  • the second bump structure includes a Ball Grid Array (BGA) solder ball.
  • BGA Ball Grid Array
  • the package structure may be combined with the package substrate by using the second bump structure, and the package substrate may be a printed circuit board (PCB) or other suitable package.
  • An external power supply voltage can be applied to the power transmission chip through the package substrate, and converted into a plurality of voltages required by the power chip by the power transmission chip, and the converted voltage is further passed through the power transmission chip A plurality of power supply tracks are applied to the power chip. Since the package structure of the present invention integrates a power transmission chip including passive components, parasitic resistance on a package substrate such as a PCB can be eliminated, thereby improving power transmission efficiency, improving response time of power control, and improving fidelity.
  • the present invention provides a new packaging method for integrating a power chip and a power transmission chip into a package structure using a three-dimensional chip stacking technology, which has the following beneficial effects: (1) using an existing active device Components and passive components Forming an active 2.5D interposer, and then integrating the power chip on the active 2.5D interposer through microbumps or other bump structures to obtain a three-dimensional stacked structure; wherein the power chip may be an application specific integrated circuit ( Application Specific Integrated Circuit (ASIC). (2) In the three-dimensional stack structure, the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • ASIC Application Specific Integrated Circuit
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • (6) Improves fidelity by reducing voltage drop and noise, thereby improving response time. Better fidelity performance improvements are achieved due to the need for less design margin. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种集成有功率传输芯片的封装结构的封装方法，封装结构包括用电芯片（5）及连接于用电芯片（5）下方的功率传输芯片（3）；功率传输芯片（3）用于将外部电源的电压转换成用电芯片（5）所需的多个电压，并提供多条对接用电芯片（5）的供电轨道。利用功率传输芯片（3）作为有源2.5D中介板，通过微凸块或其它凸块结构将用电芯片（5）集成在有源2.5D中介板上，得到三维堆叠芯片结构。整个***电路板的功率传输***由功率传输芯片（3）实现，可以消除封装基板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。

Description

集成有功率传输芯片的封装结构的封装方法 技术领域
本发明属于半导体封装技术领域，涉及一种集成有功率传输芯片的封装结构的封装方法。
背景技术
所有的计算和通信***都需要功率传输***。功率传输***会将电源的高电压转换成***中离散器件所需的许多不同的低电压。功率传输***的效率决定了向下转换的电力损失，而功率传输轨数决定了可支持的离散电压供应或器件的数量。
目前的功率传输技术面临着如下挑战：
一、随着工艺节点的收缩，器件电压减小，功率传输的效率会随之降低，使功率消耗更大。
二、添加更多的功率传输轨道需要复制更多的功率传输组件，会增加元件数量、增大电路板尺寸、增加电路板的层数、加大***体积、成本和重量。
三、由于再布线层的线距、线宽的限制，需要增加封装尺寸。
因此，如何提高功率传输效率，增加不同电压轨道的可用数量，已成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种集成有功率传输芯片的封装结构的封装方法，用于解决现有功率传输***的功率传输效率低，不同电压轨道的可用数量少的问题。
为实现上述目的及其他相关目的，本发明提供一种集成有功率传输芯片的封装结构的封装方法，所述封装结构包括用电芯片及连接于所述用电芯片下方的功率传输芯片；所述功率传输芯片用于将外部电源的电压转换成所述用电芯片所需的多个电压，并提供多条对接所述用电芯片的供电轨道；所述封装方法包括如下步骤：
提供一载体，并在所述载体上形成粘附层；
将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上，其中，所述有源元件及无源元件具有焊盘的一面与所述粘附层接触；
在所述粘附层上形成覆盖所述有源元件与无源元件的塑封层，并对所述塑封层进行研磨，以减薄所述塑封层；
去除所述载体及粘附层，暴露出所述焊盘；
形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱；
在所述塑封层与所述焊盘相同一侧的表面上形成所述功率传输芯片的再布线层；所述再布线层的导电部分与所述导电柱及所述焊盘连接，实现所述有源元件与无源元件之间的电连接，并提供多条对接所述用电芯片的供电轨道；
通过多个第一凸块结构将所述用电芯片与所述再布线层连接，实现所述用电芯片与多条所述供电轨道的对接；
在所述塑封层与所述焊盘相对一侧的表面上形成多个与所述导电柱连接的第二凸块结构。
可选地，所述外部电源的电压高于所述用电芯片所需的电压。
可选地，所述有源元件包括控制器及降压变换器；所述无源元件包括电容、电感和电阻。
可选地，通过多个第一凸块结构将所述用电芯片与所述再布线层连接之后，还包括通过底部填充胶填满所述用电芯片与所述在布线层之间间隙的步骤，以及通过塑封材料将所述用电芯片周围包裹的步骤。
可选地，所述再布线层包括介电层及形成于所述介电层中的至少一层金属连线及至少一层导电栓；所述金属连线通过所述导电栓实现与所述有源元件、无源元件及导电柱的电连接，且当所述介电层中形成有多层金属连线时，多层金属连线之间通过所述导电栓实现层间电连接。
可选地，所述第一凸块结构包括微凸块。
可选地，所述第二凸块结构包括球栅阵列焊球。
可选地，所述用电芯片为专用集成电路。
可选地，形成所述塑封层的方法包括压缩成型、传递模塑、液封成型、真空层压、旋涂中的任意一种或多种。
可选地，形成所述通孔的方法包括激光打孔、机械钻孔、反应离子刻蚀、纳米压印中的任意一种或多种。
可选地，形成所述导电柱的方法包括电镀、化学镀、丝印、引线键合中的一种或多种。
如上所述，本发明提供了一种新的封装方法，使用三维芯片堆叠技术将用电芯片与功率传输芯片集成在一个封装结构内，具有以下有益效果：
(1)采用现有的有源元件和无源元件形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(Application Specific Integrated Circuit，简称ASIC)。
(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题。
(3)整个***电路板的功率传输***由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容器(CAP(3T))，电感(L(2T))和电阻，从而消除了***板上所有的无源元件。
(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片。
(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间。
(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。
附图说明
图1显示为本发明的集成有功率传输芯片的封装结构的封装方法的工艺流程图。
图2显示为本发明的集成有功率传输芯片的封装结构的封装方法提供一载体的示意图。
图3显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述载体上形成粘附层的示意图。
图4显示为本发明的集成有功率传输芯片的封装结构的封装方法将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上的示意图。
图5显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述粘附层上形成塑封层的示意图。
图6显示为本发明的集成有功率传输芯片的封装结构的封装方法去除所述载体及粘附层的示意图。
图7显示为本发明的集成有功率传输芯片的封装结构的封装方法在所述塑封层中形成导电柱的示意图。
图8显示为本发明的集成有功率传输芯片的封装结构的封装方法形成所述功率传输芯片的再布线层的示意图。
图9显示为本发明的集成有功率传输芯片的封装结构的封装方法通过多个第一凸块结构 将所述用电芯片与所述再布线层连接，并通过底部填充胶填满所述用电芯片与所述在布线层之间间隙的示意图。
图10显示为本发明的集成有功率传输芯片的封装结构的封装方法通过塑封材料将所述用电芯片周围包裹的示意图。
图11显示为本发明的集成有功率传输芯片的封装结构的封装方法形成多个与所述导电柱连接的第二凸块结构的示意图。
元件标号说明
S1～S8                步骤
1                     载体
2                     粘附层
3                     功率传输芯片
301                   有源元件
302                   无源元件
3021                  电容
3022                  电感
303                   焊盘
304                   塑封层
305                   导电柱
306                   再布线层
3061                  介电层
3062                  金属连线
3063                  导电栓
4                     第一凸块结构
5                     用电芯片
6                     底部填充胶
7                     塑封材料
8                     第二凸块结构
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露 的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图11。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
本发明提供一种集成有功率传输芯片的封装结构的封装方法。请参阅图11，所述封装结构包括用电芯片5及连接于所述用电芯片5下方的功率传输芯片3；所述功率传输芯片3用于将外部电源的电压转换成所述用电芯片5所需的多个电压，并提供多条对接所述用电芯片5的供电轨道。本发明的封装方法利用所述功率传输芯片3作为有源2.5D中介板，通过微凸块或其它凸块结构将用电芯片5集成在有源2.5D中介板上，得到三维堆叠芯片结构。整个***电路板的功率传输***由所述功率传输芯片实现，可以消除封装基板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。
本实施例中，所述功率传输芯片包括有源元件301、无源元件302、塑封层304、导电柱305以及再布线层306。
请参阅图1，显示为本发明的集成有功率传输芯片的封装结构的封装方法的工艺流程图，包括如下步骤：
S1：提供一载体，并在所述载体上形成粘附层；
S2：将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上，其中，所述有源元件及无源元件具有焊盘的一面与所述粘附层接触；
S3：在所述粘附层上形成覆盖所述有源元件与无源元件的塑封层，并对所述塑封层进行研磨，以减薄所述塑封层；
S4：去除所述载体及粘附层，暴露出所述焊盘；
S5：形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱；
S6：在所述塑封层与所述焊盘相同一侧的表面上形成所述功率传输芯片的再布线层；所述再布线层的导电部分与所述导电柱及所述焊盘连接，实现所述有源元件与无源元件之间的电连接，并提供多条对接所述用电芯片的供电轨道；
S7：通过多个第一凸块结构将所述用电芯片与所述再布线层连接，实现所述用电芯片与 多条所述供电轨道的对接；
S8：在所述塑封层与所述焊盘相对一侧的表面上形成多个与所述导电柱连接的第二凸块结构。
首先请参阅图2及图3，执行步骤S1：提供一载体1，并在所述载体1上形成粘附层2。
具体的，所述载体的材料可以选自玻璃、硅、氧化硅、金属或陶瓷中的一种或多种，或其他类似物。所述载体1可以为平板型，例如为具有一定厚度的玻璃圆形平板。
具体的，所述粘附层2的作用是粘附固定放置于其上的元件，后续去除所述载体1时，所述粘附层2也一并被去除。
作为示例，所述粘附层2可以是UV胶带或热材料，其中，所述UV胶带在特定波长的光照下，粘附强度会降低，使得载体易于剥离。所述热材料在一定加热温度下，粘附强度会降低，使得载体易于剥离。当然，所述粘附层2也可以采用UV胶与热材料的结合。
然后请参阅图4，执行步骤S2：将所述功率传输芯片3的有源元件301与无源元件302放置于所述粘附层2上，其中，所述有源元件301及无源元件302具有焊盘303的一面与所述粘附层接触。
通常，所述有源元件301具有焊盘303的一面称之为正面，与之相对的另一面称之为背面。对于所述无源元件302，也是如此。本实施例中，是将有源元件301及无源元件302正面朝下放置于所述粘附层2上，从而粘贴固定于所述载体上。
具体的，首先在包含多个裸片(Die)的晶片背面贴上粘片膜(Die Attach Film，简写DFA)，或者不贴粘片膜，然后划片得到多个独立的裸片(即所述有源元件301或无源元件302)，接着拾取裸片，放置于所述粘附层2上，使所述裸片临时固定于所述载体1上。粘片膜可以是UV膜，在切割晶片后采用特定波长的光照/对膜加热可以降低膜的粘附强度，使得芯片很容易从膜上取下。
具体的，所述功率传输芯片3的作用是将外部电源的电压转换成所述用电芯片5所需的多个电压，并提供多条对接所述用电芯片5的供电轨道。作为示例，所述外部电源的电压高于所述用电芯片所需的电压，以下将称外部电源的电压为高电压，称用电芯片所需的电压为低电压。
作为示例，所述有源元件301包括控制器及降压变换器；所述无源元件302包括电容3021、电感3021和电阻(未图示)。在所述功率传输芯片中，降压变换器可以高电压变换为成千上万的低电压，这些低电压可通过后续形成的导电柱、再布线层构成多个供电轨道，并通过后续形成的第一凸块结构与顶部用电芯片对接。
接着请参阅图5，执行步骤S3：在所述粘附层2上形成覆盖所述有源元件301与无源元 件302的塑封层304，并对所述塑封层进行研磨，以减薄所述塑封层。
具体的，形成所述塑封层304的方法包括压缩成型、传递模塑、液封成型、真空层压、旋涂中的任意一种或多种，或其它适宜的方法。塑封材料包括环氧类树脂、液体型热固性环氧树脂、塑料等合适的材料。
本实施例中，在形成所述塑封层之后，减薄所述塑封层直至露出所述有源元件及无源元件的背面。由于所述有源元件及无源元件的背面没有焊盘，也可以在有源元件及无源元件的背面保留一定厚度的塑封材料，此处不应过分限制本发明的保护范围。
作为示例，研磨过程可以采用机械研磨工艺、化学抛光工艺、蚀刻工艺、其任意组合和/或类似工艺。
再请参阅图6，执行步骤S4：去除所述载体1及粘附层2，暴露出所述焊盘303。
具体的，可以采用机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种去除所述载体1；优选地，本实施例中，可以通过去除所述粘附层2以剥离所述载体1。
再请参阅图7，执行步骤S5：形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱305。
具体的，所述通孔(Through Active-interposer Via，简称TAV)可以通过激光打孔、机械钻孔、反应离子刻蚀、纳米压印中的任意一种或多种，或其他适宜的方法制作。通孔填充材料可以是焊料或铜。TAV填充可通过电镀、化学镀、丝印、引线键合中的任意一种或多种，或其他合适的金属沉积工艺形成。
再请参阅图8，执行步骤S6：在所述塑封层304与所述焊盘303相同一侧的表面上形成所述功率传输芯片3的再布线层306；所述再布线层306的导电部分与所述导电柱305及所述焊盘303连接，实现所述有源元件301与无源元件302之间的电连接，并提供多条对接所述用电芯片5的供电轨道。
具体的，所述再布线层包括介电层3061及形成于所述介电层中的至少一层金属连线3062及至少一层导电栓3063；所述金属连线3062通过所述导电栓3063实现与所述有源元件301、无源元件302及导电柱305的电连接，且当所述介电层3061中形成有多层金属连线3062时，多层金属连线3062之间通过所述导电栓3063实现层间电连接。
作为示例，所述金属连线3062的材料包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。例如，所述金属连线3062可以为Cu线，制作Cu线的种子层可以为Ti/Cu层。形成所述金属连线182的方法可以包括电解镀、化学镀、丝网印刷中的一种或多种，或其他适合的金属沉积工艺。可以先通过激光钻孔、机械钻孔、反应离子刻蚀、纳米压印或其他适合的开孔方法在所述介电层3061内形成通孔，然后再所述通孔 内填充金属材料即可形成所述导电栓3063；所述导电栓3063的材料可以为焊料或Cu，填充方法可以为电解镀、化学镀、丝网印刷、引线键合或其他适合在通孔中填充导电材料的方法。
再请参阅图9，执行步骤S7：通过多个第一凸块结构4将所述用电芯片5与所述再布线层连接，实现所述用电芯片5与多条所述供电轨道的对接。
具体的，所述用电芯片包括但不限于专用集成电路裸芯(ASIC Die)。所述第一凸块结构4可以采用微凸块(mico-bump)或其他合适的凸块结构。
作为示例，可以采用超声键合、热压键合或普通的回流焊等工艺将所述用电芯片5经由多个第一凸块结构4焊接于所述再布线层306上。
本实施例中，通过多个第一凸块结构将所述用电芯片与所述再布线层连接之后，还包括通过底部填充胶填满所述用电芯片5与所述在布线层306之间间隙的步骤。底部填充胶简单来说就是底部填充之义，常规定义是一种用化学胶水(主要成份是环氧树脂)对芯片进行底部填充，利用加热的固化形式，将芯片底部空隙大面积(一般覆盖80％以上)填满，从而达到加固的目的，增强封装结构的抗跌落性能。
作为示例，底部填充方法可以为毛细填充(capillary underfill)或成型填充(Molding UnderFill，简称MUF)。其中，毛细填充是利用毛细作用使得胶水迅速流过芯片底部，其毛细流动的最小空间是10um。这也符合了焊接工艺中焊盘和焊锡球之间的最低电气特性要求，因为胶水是不会流过低于4um的间隙，所以保障了焊接工艺的电气安全特性。
再请参阅图10，还包括通过塑封材料7将所述用电芯片5周围包裹的步骤。
最后请参阅图11，执行步骤S8：在所述塑封层与所述焊盘相对一侧的表面上形成多个与所述导电柱连接的第二凸块结构8。
作为示例，所述第二凸块结构包括球栅阵列(Ball Grid Array，BGA)焊球。
具体的，所述封装结构可以通过所述第二凸块结构与封装基板结合，所述封装基板可以是PCB板(Printed Circuit Board，印制电路板)或其它合适的封装件。外部电源电压可以通过所述封装基板施加到所述功率传输芯片上，并通过所述功率传输芯片转换成用电芯片所需的多个电压，这些转换后的电压进而通过所述功率传输芯片中的多条供电轨道施加到用电芯片上。本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高功率传输效率，改善功率控制的响应时间，提高保真度。
综上所述，本发明提供了一种新的封装方法，使用三维芯片堆叠技术将用电芯片与功率传输芯片集成在一个封装结构内，具有以下有益效果：(1)采用现有的有源元件和无源元件 形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(Application Specific Integrated Circuit，简称ASIC)。(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题。(3)整个***电路板的功率传输***由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容器(CAP(3T))，电感(L(2T))和电阻，从而消除了***板上所有的无源元件。(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片。(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间。(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种集成有功率传输芯片的封装结构的封装方法，其特征在于，所述封装结构包括用电芯片及连接于所述用电芯片下方的功率传输芯片；所述功率传输芯片用于将外部电源的电压转换成所述用电芯片所需的多个电压，并提供多条对接所述用电芯片的供电轨道；所述封装方法包括如下步骤：
    提供一载体，并在所述载体上形成粘附层；
    将所述功率传输芯片的有源元件与无源元件放置于所述粘附层上，其中，所述有源元件及无源元件具有焊盘的一面与所述粘附层接触；
    在所述粘附层上形成覆盖所述有源元件与无源元件的塑封层，并对所述塑封层进行研磨，以减薄所述塑封层；
    去除所述载体及粘附层，暴露出所述焊盘；
    形成多个上下贯穿所述塑封层的通孔，并在所述通孔中填充导电材料，得到导电柱；
    在所述塑封层与所述焊盘相同一侧的表面上形成所述功率传输芯片的再布线层；所述再布线层的导电部分与所述导电柱及所述焊盘连接，实现所述有源元件与无源元件之间的电连接，并提供多条对接所述用电芯片的供电轨道；
    通过多个第一凸块结构将所述用电芯片与所述再布线层连接，实现所述用电芯片与多条所述供电轨道的对接；
    在所述塑封层与所述焊盘相对一侧的表面上形成多个与所述导电柱连接的第二凸块结构。
  2. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：所述外部电源的电压高于所述用电芯片所需的电压。
  3. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：所述有源元件包括控制器及降压变换器；所述无源元件包括电容、电感和电阻。
  4. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：通过多个第一凸块结构将所述用电芯片与所述再布线层连接之后，还包括通过底部填充胶填满所述用电芯片底部与所述在布线层之间间隙的步骤，以及通过塑封材料将所述用电芯片周围包裹的步骤。
  5. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：所述再布线层包括介电层及形成于所述介电层中的至少一层金属连线及至少一层导电栓；所述金属连线通过所述导电栓实现与所述有源元件、无源元件及导电柱的电连接，且当所述介电层中形成有多层金属连线时，多层金属连线之间通过所述导电栓实现层间电连接。
  6. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：所述第一凸块结构包括微凸块；所述第二凸块结构包括球栅阵列焊球。
  7. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：所述用电芯片为专用集成电路。
  8. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：形成所述塑封层的方法包括压缩成型、传递模塑、液封成型、真空层压、旋涂中的任意一种或多种。
  9. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：形成所述通孔的方法包括激光打孔、机械钻孔、反应离子刻蚀、纳米压印中的任意一种或多种。
  10. 根据权利要求1所述的集成有功率传输芯片的封装结构的封装方法，其特征在于：形成所述导电柱的方法包括电镀、化学镀、丝印、引线键合中的一种或多种。
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