200845082 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種場發射器，尤指一種以共平面成型 之陰極板結構。 【先前技術】 近年來，平面顯示器（Flat Panel Display)由於具有 輕與薄的特色，甚至在晝質上的解析度與及亮度的表現更 勝於傳統電視，而且廣泛運用在不同尺寸的顯示需要求上 ，小至手機螢幕，大至戶外的廣告看板，皆可看到平面顯 示器的應用，使得平面顯示器在市場上蔚為風潮。 因此各種不同類型的平面顯示器遂不斷在市場上推 出，包括液晶顯示器（LCD )、電漿顯示器（PDP )、有 機發光二極體顯示器（0LED)及場發射型顯示器（FED ) 等；特別是場發射型顯示器（FED )，係為近年來新興發 展的平面顯示器種類之一，其原理係利用内部結構所設置 之陰極電子發射源產生電子束，以撞擊所對應之螢光層以 產生亮光。 習知技術三極結構之場發射型顯示器係包括一陽極板 及一陰極板以及一位於陰陽極板間的閘極層，其中該閘極 層係提供一電位而汲引該陰極板產生電子，再由該陽極導 電層提供一高電位，以提供電子之加速動能，以撞擊該陽 極板而產生亮光。 然而前述習知結構上雖可提供該場發射型顯示器正常 的發光作用，不過由於閘極層的設計係直接設於該陰極板 5 200845082 與陽極板之間，且鄰接於該陰極板所設置的射極上 該陰極板在製作上較為繁複且成本高；因此，^成 技術為了降低成本且改善前述結構製作上的缺失^知 -種射極與祕設於共平面上的陰極結構，如出 職891320號，改變習知利用層疊方式所構成的陰極結j， 不但在製程上較為簡易，且更可降低其製作成本。α 而前述以共平面結構設計將射極與間極成形於 板上’具有降低成本及減化製程等優點，但對:二 平方向汲引射極產生電子的電場卻造成影響；由7 面電場的向量直接影響該場發射電子的量及方向，、°表 電位的條件下，射極與閘極的間隔越大目： J場的強度就相對越小，造成射極的電子產生效= 直接影響到該場發射器的發光效果。 一 雖然射極與關卿錢_可利料導體製程縮減 ，m以下，但相對會提高其製作成本，且在相同電位 的十月況下，由於射極與閘極間隔過小，在兩電場交互夺燮 :搞使射極所釋放的部分自由電子受閘極吸引無法加速； 膜製程’雖可降㈣m /机現象’右利用厚 ㈣a 降&成本制極與閘極的間隔會受 印製面板的準確性而必須保持在 J =與閘極結構的平坦性或是材料燒結後而變形:2 閘】 = 而為了彌補此種製程所造成射極與 朽’則必須提高陽極板的電位以得到陽 陰極板較大的電場強度；因此，不管選擇哪一種！y 6 200845082 程，皆會有運用在陰極板共平面結構上的缺失出現，勢必 要尋求新的解決方式來解決。 【發明内容】 針對上述之缺失，本發明之主要目的在於提供一種以 介電層改變電場分佈之場發射顯示器之平面發射式陰極結 構5措由在共平面設置相互對應且分離之射極層及閘極層 所形成之間隔内設置一介電層’以改變射極層與閘極層之 / 電場分布狀態，同時亦因共平面結構可直接製作於陰極基 板上，以降低該製程成本。 為達成上述之目的，本發明係主要提供一種場發射顯 示器之平面發射式陰極結構，該陰極板係具有一陰極基板 ，於該陰極基板上設有複數陰極單元，該陰極單元係包括 一射極層、一閘極層及一介電層，其中該射極層與閘極層 係共平面設置於陰極基板上，且相互對應分離並形成一間 隔，另該介電層係設於該射極層與閘極層所形成之間隔中 〔 ，且分別與該射極層與閘極層形成間隙而不鄰接，以形成 該陰極板之共平面結構。 【實施方式】 茲將本發明之内容配合圖式來加以說明： 請參閱第一圖，係為本發明之結構剖視圖。如圖所示 ，該陰極板1係具有一陰極基板11 ’於該陰極基板11上設 有複數陰極單元12，以共同對應一陽極，各陰極單元12係 包括一射極層121、一閘極層122、一介電層123及陰極 導電層124，其中該射極層121及閘極層122係以共平面 7 200845082 方式設置於該陰極基板11上，且該射極層121及閘極層 122分別電性連接陰極導電層124，以作為導電之路徑， 並該射極層121及閘極層122於該陰極基板11相互分離對 應並形成一間隔125，於本實施例中該射極層121與閘極 層122之間隔125係保持於50// m，又，該射極層121及 閘極層122之於該陰極基板11上之厚度係介於1 // m〜25 β m 〇 另該介電層123係設置於該射極層121與閘極層122 間所形成之間隔125内，以共平面方式與射極層121及閘 極層122同設於該陰極基板11上，同時該介電層123與相 鄰之射極層121及閘極層122分別保持一定之間隙，且介 電層123不與該射極層121或閘極層122相接，其中該間 隙係保持介於5〜15/z m，而該介電層123於本實施例中係 由含玻璃成份之材料所構成，如玻璃膠，且該材料係為介 電常數為7或以上之絕緣材料，又，該介電層123之厚度 係為該射極層121厚度之0.5倍至1.5倍，如本實施例中 之圖式所示，該介電層123之厚度係大於該射極層121及 閘極層122厚度，或如第二圖之圖式所示，該介電層123 之厚度係小於該射極層121及閘極層122厚度。 請參閱第三圖（A )〜（B )，係為本發明之電場分 佈比較圖。比較圖（A )及圖（B )，係在有無介電層 123之情況下其電場之分佈，於圖（A )中該電場分佈係 集中於該射極層121及閘極層122所形成之間隔125内， 造成射極層121所產生之電子無法完全射向所對應之陽極 8 200845082 ，而造成漏電流現象；另該圖（B )中，可看出該於射極 層121及閘極層122所形成之間隔125内設置該介電層 123，該間隔125之密度則降低，致使該射極層121之電 子被汲引出後，可順利被陽極所具有之電位吸引而撞擊陽 極，因此，經由介電層123以共平面結構設於該射極層 121及閘極層122間，除了簡化該陰極板1之製程外，該 介電層123更可作為射極層121及閘極層122間之阻隔， 改變射極層121及閘極層122間之電場分布密度，以阻隔 由射極層121之電子往閘極層122移動，降低其陰極板1 上之漏電流現象；另外，配合參閱第三圖（C )〜（D ) ，設置不同介電常數之介電層123，如本實施例第三圖圖 (D )中所設之介電層123介電常數係大於第三圖圖（C )中之介電層123介電常數，致使圖（D )中鄰近射極 121之電場分布密度大於圖（C )中鄰近射極121之電場 分布密度。 因此，配合第三圖（B)〜（D)及第四圖，在該不 同介電常數之介電層123影響下，改變射極層121及閘極 層122電場分佈密度，如第四圖所示，在施加相同電壓於 該閘極層122時，在介電常數越大之介電層123影響下， 該射極層121所釋放之電流越大。 惟以上所述之實施方式，是為較佳之實施實例，當不 能以此限定本發明實施範圍，若依本發明申請專利範圍及 說明書内容所作之等效變化或修飾，皆應屬本發明下述之 專利涵蓋範圍。 9 200845082 【圖式簡單說明】 第一圖、係為本發明之結構剖視圖。 第二圖、係為本發明之另一實施例結構剖視圖。 第三圖（A )〜（D )、係為本發明之電場分佈示意圖 第四圖、係為本發明之射極釋放電流與閘極電壓曲線圖 【主要元件符號說明】 陰極板1 陰極基板11 陰極單元12 射極層121 閘極層122 介電層123 陰極導電層124 間隔125200845082 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a field emitter, and more particularly to a cathode plate structure formed by coplanar molding. [Prior Art] In recent years, Flat Panel Display has more light and thin features, even better resolution and brightness in enamel than traditional TV, and is widely used in different sizes of display needs. From the small screen to the mobile phone screen, as far as the outdoor advertising billboards, you can see the application of flat panel display, making the flat panel display in the market. Therefore, various types of flat panel displays are constantly being introduced in the market, including liquid crystal displays (LCDs), plasma display units (PDPs), organic light emitting diode displays (0LEDs), and field emission type displays (FEDs); Emission-type display (FED) is one of the emerging types of flat-panel displays in recent years. Its principle is to generate an electron beam by using a cathode electron emission source provided by an internal structure to strike a corresponding phosphor layer to generate bright light. A field emission display of a conventional three-pole structure includes an anode plate and a cathode plate and a gate layer between the anode and cathode plates, wherein the gate layer provides a potential to induce the cathode plate to generate electrons, and then A high potential is provided by the anode conductive layer to provide accelerated kinetic energy of the electrons to strike the anode plate to produce bright light. However, the conventional structure can provide the normal illumination function of the field emission type display, but the design of the gate layer is directly disposed between the cathode plate 5 200845082 and the anode plate, and is adjacent to the cathode plate. The cathode plate on the emitter is complicated and costly in production; therefore, in order to reduce the cost and improve the fabrication of the aforementioned structure, the emitter and the cathode structure secreted on the coplanar surface, such as the job No. 891320, changing the conventional cathode junction j formed by the lamination method, is not only simple in the process, but also reduces the manufacturing cost. α, and the above-mentioned coplanar structure designing the emitter and the interpole on the board has the advantages of reducing cost and reducing the process, but affecting the electric field of the electron generated by the bismuth emitter in the second plane; The vector directly affects the amount and direction of the electrons emitted by the field. Under the condition of the potential of the meter, the interval between the emitter and the gate is larger. The intensity of the J field is relatively small, causing the electrons of the emitter to be effective. Affects the illuminating effect of the field emitter. Although the emitter and Guan Qing money _ can benefit the conductor process reduction, m below, but will increase its production cost, and in the same potential of the month, due to the emitter and gate spacing is too small, in the two electric field interaction Capture: The part of the free electrons released by the emitter can not be accelerated by the gate; the film process can be lowered (4) m / machine phenomenon 'right use thick (four) a drop & The accuracy of the panel must be maintained at J = flatness of the gate structure or deformation of the material after sintering: 2 gates = = and in order to compensate for the emitter and decay caused by such a process, the potential of the anode plate must be increased. The larger electric field strength of the anode and cathode plates is obtained; therefore, no matter which one is chosen! y 6 200845082 Cheng, there will be a lack of use in the coplanar structure of the cathode plate, it is necessary to find a new solution to solve. SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies, the main object of the present invention is to provide a planar emission cathode structure of a field emission display in which a dielectric layer is changed by a dielectric layer, and to provide mutually corresponding and separate emitter layers in a coplanar plane. A dielectric layer is disposed in the interval formed by the gate layer to change the electric field distribution state of the emitter layer and the gate layer, and is also directly formed on the cathode substrate due to the coplanar structure to reduce the process cost. In order to achieve the above object, the present invention mainly provides a planar emission cathode structure of a field emission display, the cathode plate having a cathode substrate on which a plurality of cathode units are disposed, the cathode unit including an emitter a layer, a gate layer and a dielectric layer, wherein the emitter layer and the gate layer are coplanarly disposed on the cathode substrate, and are separated from each other to form a space, and the dielectric layer is disposed on the emitter The layer and the gate layer are formed in a space [and respectively form a gap with the emitter layer and the gate layer without abutting to form a coplanar structure of the cathode plate. [Embodiment] The contents of the present invention will be described with reference to the drawings: Please refer to the first drawing, which is a cross-sectional view of the structure of the present invention. As shown in the figure, the cathode plate 1 has a cathode substrate 11' on which a plurality of cathode units 12 are disposed to collectively correspond to an anode. Each cathode unit 12 includes an emitter layer 121 and a gate. The layer 122, the dielectric layer 123 and the cathode conductive layer 124, wherein the emitter layer 121 and the gate layer 122 are disposed on the cathode substrate 11 in a manner of a coplanar plane 7 200845082, and the emitter layer 121 and the gate layer The cathode conductive layer 124 is electrically connected to the cathode conductive layer 124 as a conductive path, and the emitter layer 121 and the gate layer 122 are separated from each other on the cathode substrate 11 to form a space 125. In this embodiment, the emitter layer is formed. The gap between the 121 and the gate layer 122 is maintained at 50/m. Further, the thickness of the emitter layer 121 and the gate layer 122 on the cathode substrate 11 is between 1 // m and 25 β m. The dielectric layer 123 is disposed in the space 125 formed between the emitter layer 121 and the gate layer 122, and is disposed on the cathode substrate 11 in a coplanar manner with the emitter layer 121 and the gate layer 122. At the same time, the dielectric layer 123 and the adjacent emitter layer 121 and the gate layer 122 respectively maintain a certain gap, and dielectric 123 is not connected to the emitter layer 121 or the gate layer 122, wherein the gap is maintained at 5 to 15/zm, and the dielectric layer 123 is composed of a material containing a glass component in the embodiment. For example, the glass paste, and the material is an insulating material having a dielectric constant of 7 or more, and the thickness of the dielectric layer 123 is 0.5 to 1.5 times the thickness of the emitter layer 121, as in the embodiment. The thickness of the dielectric layer 123 is greater than the thickness of the emitter layer 121 and the gate layer 122, or as shown in the second diagram, the thickness of the dielectric layer 123 is smaller than the emitter layer. 121 and the thickness of the gate layer 122. Please refer to the third figures (A) to (B) for comparing the electric field distribution of the present invention. Comparing the graphs (A) and (B), the electric field distribution is in the presence or absence of the dielectric layer 123. In the graph (A), the electric field distribution is concentrated on the emitter layer 121 and the gate layer 122. In the interval 125, the electrons generated by the emitter layer 121 cannot be completely directed to the corresponding anode 8 200845082, which causes leakage current; in the figure (B), the emitter layer 121 and the gate can be seen. The dielectric layer 123 is disposed in the interval 125 formed by the pole layer 122. The density of the spacer 125 is lowered, so that the electrons of the emitter layer 121 are attracted by the anode and then hit the anode. Therefore, the dielectric layer 123 is disposed between the emitter layer 121 and the gate layer 122 via the dielectric layer 123. In addition to simplifying the process of the cathode plate 1, the dielectric layer 123 can serve as the emitter layer 121 and the gate. The barrier between the layers 122 changes the electric field distribution density between the emitter layer 121 and the gate layer 122 to block the movement of the electrons from the emitter layer 121 toward the gate layer 122, thereby reducing the leakage current on the cathode plate 1; , with reference to the third figure (C) ~ (D), set the different dielectric constants The dielectric layer 123, as shown in the third diagram (D) of the embodiment, has a dielectric constant greater than the dielectric constant of the dielectric layer 123 in the third diagram (C), resulting in a diagram (D). The electric field distribution density of the adjacent adjacent emitter 121 is greater than the electric field distribution density of the adjacent emitter 121 in Fig. (C). Therefore, in conjunction with the third (B) to (D) and fourth figures, the electric field distribution density of the emitter layer 121 and the gate layer 122 is changed under the influence of the dielectric layer 123 of different dielectric constants, as shown in the fourth figure. As shown, when the same voltage is applied to the gate layer 122, the current discharged by the emitter layer 121 is greater under the influence of the dielectric layer 123 having a larger dielectric constant. However, the embodiments described above are preferred embodiments, and the scope of the invention is not limited thereto, and equivalent changes or modifications made in accordance with the scope of the invention and the contents of the specification should be The scope of patent coverage. 9 200845082 [Simple description of the drawings] The first figure is a cross-sectional view of the structure of the present invention. The second drawing is a cross-sectional view showing another embodiment of the present invention. The third diagrams (A) to (D) are the fourth diagram of the electric field distribution diagram of the present invention, which is the graph of the emitter discharge current and the gate voltage of the present invention. [Main component symbol description] Cathode plate 1 Cathode substrate 11 Cathode unit 12 emitter layer 121 gate layer 122 dielectric layer 123 cathode conductive layer 124 interval 125