TW200828778A - High precision oscillator with self-calibration functions and method of calibration thereof - Google Patents
High precision oscillator with self-calibration functions and method of calibration thereof Download PDFInfo
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200828778 九、發明說明: 【發明所屬之技術領域】 本發明係關於振盪器(0scillator)的技術領域,尤指— 種具有自校準功能的高精度振盪器及校準方法。 【先前技術】200828778 IX. Description of the Invention: [Technical Field] The present invention relates to the technical field of oscillators, and more particularly to a high-precision oscillator and a calibration method having a self-calibration function. [Prior Art]
10 15 習知的振盪電路係在封裝振盪器的積體電路外,以外 加的電阻及電容來調整振盪電路的振盪頻率。利用外加的 電阻及電容的彳式然可以獲得較佳準韻的振盤頻 率,但由外加的電阻及電容會增加積體電路封裝的腳位 (PA^D)、振盛電路的面積、及電阻及電容成本,而使得整個 振後電路的成本大為提高。 為解決外加電阻及電容所產生成本提高的問題,另一 種習^技術係將電阻及電容與振魅實作(卿丨⑽咖)在同 们曰日片(die)内。然而此種方法將受到半導體製程的影 曰’同-晶圓(Wafer)上不同地方的晶片㈣會產生不同的 =頻率,並且«頻率容易隨溫度變化,造成振盈器裝 尸:準之困難口此可知’習知振盪器裝置及振盪器裝置 杈準方法仍存有諸多之缺失而有予以改進之必要。 【發明内容】 本發明之一目的係在提供一番 ^ ^ .. ^ ^ ^ ^ U種具有自杈準功能的高精 度振盈态及权準方法,可解氺鬥 解/夫同一晶圓上不同地方的晶¥ 20 200828778 !f=同的振盡頻率的問題,並且可避免振盪頻率容易 ρ逍溫度變化的問題。 、 易 於产目的係在提供—種具有自校準功能的高 /月又準方法’俾以有效提高《器之精確度。 、據本發明之—特色’本發明係提出—種具有自 功月匕的南精度振盪器,其具有_校準模式及—工作 =精^器包括一頻率偵測襄置、一邏輯控制裝置、 弟 負料匯流排、一笛一 +TT 4么口口 置。該頻率偵測裝置之第一:一數位控制振盡裝 豆… 罘輸入端接收一頻率參考訊號, 乐輸人端接收—除頻訊號,該頻率侧裝置比較該頻 #考頻率訊號及該除頻訊號之頻率 1 號:其中,該指示訊號具有-第—狀態及—第二狀 邏輯控制裝置具有N位元之輸出琿,並連接至該頻率偵測穿 置1邏輯控制裝置依據該指示訊號以設定該輸出淳之二 15 一 /弟資料匯流排耦ί接於該位元輸出埠;該第一 切換器㈣於—第—資料匯流排,用以對該第-資料匯流 ㈣號,行傳輸或阻隔;該數位㈣振盪裝置純於該第 -切換器,經由該第一切換器及該第一資料匯流排而耦接 於該Ν位元輸出埠,該數位控制振盪裝置依據該顺元之輸 出埠^值,以產生一時序訊號;其中,當該高精度振盪器 2於杈準模式時,該第一切換器為開啟狀態,用以傳輸該 第—貝料匯流排訊號,該數位控制振i裝置依據該Ν位元之 輸=埠之值,以產生該時序訊號,該頻率偵測裝置比較該 ㉙率茶考頻率訊號及該除頻訊號之頻率,以產生該指示訊 20 200828778 號,該邏輯控制裝置依序依據該指示訊號以分別設定該輸 出埠之第(N-1 )位元至第〇位元之值。 依據本發明之另一特色,本發明係提出一種高精度振10 15 The conventional oscillator circuit is external to the integrated circuit of the package oscillator, and the additional resistor and capacitor are used to adjust the oscillation frequency of the oscillator circuit. The use of external resistors and capacitors can achieve better vibrating frequency, but the added resistors and capacitors increase the footprint of the integrated circuit package (PA^D), the area of the vibrating circuit, and The cost of resistors and capacitors increases the cost of the entire post-resonance circuit. In order to solve the problem of increasing the cost of external resistors and capacitors, another technique is to use the resistors and capacitors in the same way as the vibrating (Qi (10) coffee). However, this method will be affected by the semiconductor process. The wafers in different places on the wafer (four) will produce different = frequency, and the frequency is easy to change with temperature, causing the vibrator to be corpse: the difficulty It can be seen that the conventional oscillator device and the oscillator device standard method still have many defects and are necessary for improvement. SUMMARY OF THE INVENTION One object of the present invention is to provide a high-precision vibration state and a weighting method with self-aligning functions, which can solve the same wafer. On the different places of the crystal ¥ 20 200828778 ! f = the same problem of the vibration frequency, and can avoid the problem that the oscillation frequency is easy to change the temperature. The purpose of production is to provide a high-month and quasi-method with self-calibration function to effectively improve the accuracy of the device. According to the present invention, the present invention proposes a south precision oscillator having a self-powered moon, which has a calibration mode and a work = a frequency detection device, a logic control device, The younger brothers are in contact with the bus, one flute and one TT 4. The first of the frequency detecting devices: a digital control to vibrate the bean... The input terminal receives a frequency reference signal, and the input end receives the frequency signal, and the frequency side device compares the frequency # test frequency signal and the division The frequency of the frequency signal No. 1: wherein the indication signal has a -first state and - the second logic control device has an N-bit output port, and is connected to the frequency detection piercing 1 logic control device according to the indication signal The first switch (4) is connected to the data stream bus for transmitting the first data sink (four) number, and the first switch (4) is connected to the bit data output line. Alternatively, the digital (4) oscillating device is coupled to the first bit switch via the first switch and the first data bus, and the digitally controlled oscillating device is configured according to the sigmoid Outputting a value of 埠^ to generate a timing signal; wherein, when the high-precision oscillator 2 is in the calibration mode, the first switch is in an on state for transmitting the first-bay material bus signal, the digital control The vibration device is based on the device The value of the input = 埠 is used to generate the timing signal, and the frequency detecting device compares the frequency of the 29-chat tea test frequency signal and the frequency-divided signal to generate the indication signal 20 200828778, the logic control device sequentially The value of the (N-1)th to the third bit of the output port is respectively set according to the indication signal. According to another feature of the present invention, the present invention provides a high precision vibration
盡m之自;k準方法’其係用以設定—數位控制振盪裝置之N 5位元控制字組,該數位控制振盈裝置依據該1^位元控制字組 以產生-時序訊號’該自校準方法包括:⑷執行該振蓋器 之電路初始化,以將N位元控制字組之每—位元初始化為 (B)設定該雜元控制字組之f (N_〇位元為i ;⑹比 較該數位控制振盪裝置產生的時序訊號與一頻率參考訊號 Π)之頻率·’(D)當該時序訊號頻率小於該頻率參考訊號之頻率 時,設定該N位元控制字組之第(叫)位元為〇,當該時序 «頻率非小於該頻率參考訊號之頻率時,以該ν位元控 制字組之第(Ν-1)位元為!;⑻重覆步驟⑻至步驟⑼, 以依序設定該N位元控制字組之第(N_2)位元至第〇位元。 15 【實施方式】The k-method is used to set the N 5 bit control block of the digitally controlled oscillating device, and the digital control oscillating device controls the block according to the 1 ^ bit to generate a - timing signal The self-calibration method includes: (4) performing circuit initialization of the vibrator to initialize each bit of the N-bit control block to (B) setting the f of the miscellaneous control block (N_〇 bit is i (6) comparing the frequency of the timing signal generated by the digitally controlled oscillating device with a frequency reference signal ·), '(D), when the frequency of the timing signal is less than the frequency of the frequency reference signal, setting the number of the N-bit control block The (called) bit is 〇. When the timing «frequency is not less than the frequency of the frequency reference signal, the (Ν-1) bit of the block is controlled by the ν bit! (8) Repeat steps (8) through (9) to sequentially set the (N_2)th to the third bit of the N-bit control block. 15 [Embodiment]
圖1係本發明之具有自校準功能的高精度振盈器的方 l圖’其中,該高精度振m有—校準模式及一工作模 式,該校準模式制以校準該振i器之輸出訊號clk〇ut 的頻率。該振包括-頻率仙裝置11G、—邏輯控制東 置⑴、-第-資料匯流排12G、_第—切換器125、一触 控制振盥裝置130、一除頻裝置135、一第二切換器⑹、一 :己憶體裝置145、一第二資料匯流排15〇、一第三切換哭 °、一第四切換器160、及-工作模式選擇裝置170/ 20 200828778 該頻率偵測裝置U0之第一輸入端U1接收一頻率參考 訊號REF—CLK ’其第二輸入端! ! 2接收一除頻訊號cIk—div。 該頻率债測裝置11 〇比較該頻率參考訊號ref—clk的頻率 及該除頻訊號clk_div之頻率,以產生一指示訊號 Indicator ’其中,該指示訊號Indicat〇r具有一第一狀態(〇) 及一第二狀態(1),該第一狀態⑼用以指示該除頻訊號 elk—div之頻率小於該頻率參考訊號ref_clk的頻率,該第u1 is a schematic diagram of a high-precision vibrator of the present invention having a self-calibration function, wherein the high-precision oscillator has a calibration mode and an operation mode, and the calibration mode is configured to calibrate an output signal of the oscillator. The frequency of clk〇ut. The vibration includes a frequency device 11G, a logic control east (1), a - data bus 12G, a _-switch 125, a one-touch control device 130, a frequency dividing device 135, a second switch (6), one: the memory device 145, a second data bus 15 〇, a third switching cry, a fourth switch 160, and - working mode selection device 170 / 20 200828778 the frequency detecting device U0 The first input terminal U1 receives a frequency reference signal REF_CLK 'the second input terminal thereof! ! 2 Receive a de-frequency signal cIk-div. The frequency debt measuring device 11 compares the frequency of the frequency reference signal ref_clk and the frequency of the frequency dividing signal clk_div to generate an indication signal Indicator, wherein the indication signal Indicat〇r has a first state (〇) and a second state (1), the first state (9) is used to indicate that the frequency of the frequency-divided signal elk-div is less than the frequency of the frequency reference signal ref_clk, the u
10 15 二狀態⑴心指㈣除頻訊號elk_div之頻率沒有小於該 率參考訊號REF—CLK的頻率。 〇、 該邏輯控制裝置115具有N位元之輪出埠U5i以輪出^ ,元控制字組,並連接至該頻率❹】裝置m。該邏輯控制 裝置115依據該指示訊號Indicat〇r以設定該輸出埠11 $ 1之— 位兀值。當該指示訊號Indicat〇r為第一狀態⑼時,表示該 除頻訊號elk—d1V之頻率小於該頻率參考訊號咖咖的二 率’而設定該N位元控制字組之第i位元為Q。當該指示訊號 涵⑽沉為第二狀態⑴時,表示該除頻訊號Clk dlv之頻^ 沒有小於該頻率參考訊號REF一CLK的頻率時,設定該^位 元控制字組之第i位元為丨。其中,1為〇〜(Nq)的整數^ 當該高精度減1處純準料時,該邏奸.置 U5輸出-低電位⑼❿吻訊號。當該高精度振i器處於 工作杈式式時’該邏輯控制裝置115輸出—為10 15 Two states (1) The heart (4) The frequency of the de-interference signal elk_div is not less than the frequency of the reference signal REF_CLK.逻辑, the logic control device 115 has an N-bit wheel 埠U5i to rotate the NAND element, and is connected to the frequency 装置 device m. The logic control device 115 sets the value of the output 埠11$1 according to the indication signal Indicat〇r. When the indication signal Indicat〇r is in the first state (9), indicating that the frequency of the frequency-divided signal elk_d1V is less than the second rate of the frequency reference signal, the i-th bit of the N-bit control block is set to Q. When the indication signal culvert (10) sinks to the second state (1), it indicates that the frequency of the frequency-divided signal Clk dlv is not less than the frequency of the frequency reference signal REF_CLK, and the i-th bit of the control bit group is set. Why? Among them, 1 is an integer of 〇~(Nq)^ When the high precision is reduced by 1 pure material, the file is set to U5 output-low potential (9) ❿ kiss signal. When the high-precision vibrator is in the working mode, the logic control device 115 outputs -
Ready訊號。 20 200828778 、Λ第資料匯’瓜排12〇稱接於該;Ν位元輸出埠1151,用 以傳輸第一資料匯流排訊號至該數位控制振盪裝置或 記憶體裝置145。 忒第一切換斋125耦接於該第一資料匯流排12〇,用以 5將該第—資料匯流排120至該該數位控制振盪裝置丨30的訊 號進行傳輸或阻隔。 /數位^工制振Μ I置13〇輕接於該第一切換器125,經 • ’务切換器125及该第一資料匯流排120而编接於該Ν 位凡輸出埠Π51。該數位控制振盪裝置13〇依據該枓位元之 1〇控制字組之值,以產生一時序訊號clock。 該除頻裝置135耦接於該數位控制振盪裝置13〇,以將 違日寸序訊號clock除頻,俾產生該除頻訊號clk_div。 當该咼精度振盪器處於校準模式時,該第一切換器125 為開啟狀態,用以傳輸該第一資料匯流排12〇訊號。該數位 15控制振盪裝置130依據該N位元控制字組之值,以產生該時 序訊號clock。該頻率偵測裝置110比較該頻率參考訊號 _ REF-CLK及该除頻訊號elk—div之頻率以產生該指示訊號Ready signal. 20 200828778 Λ 资料 资料 ’ 瓜 瓜 瓜 瓜 瓜 瓜 瓜 Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν 埠 埠 埠 埠 埠 埠 埠 埠 埠 埠 埠 埠 埠 埠The first switch 125 is coupled to the first data bus 12 for transmitting or blocking the signal of the first data bus 120 to the digital control oscillator 30. The digital camera 13 is lightly connected to the first switch 125, and is connected to the output port 51 via the switch 220 and the first data bus 120. The digitally controlled oscillating device 13 controls the value of the block according to the 枓 bit of the 枓 bit to generate a timing signal clock. The frequency dividing device 135 is coupled to the digitally controlled oscillating device 13A to divide the frequency of the clock signal clock to generate the frequency dividing signal clk_div. When the 咼 precision oscillator is in the calibration mode, the first switch 125 is in an on state for transmitting the first data bus 12 signal. The digit 15 controls the oscillating device 130 to control the value of the block according to the N bit to generate the timing signal clock. The frequency detecting device 110 compares the frequency of the frequency reference signal _ REF-CLK and the frequency-dividing signal elk-div to generate the indication signal.
Indicator,該邏輯控制裝置115依據該指示訊號Indicat〇r而 分別設定該控制字組之第(N—i)位元至第〇位元之值。 20 當该咼精度振盪器處於工作模式時,該第一切換器125 為關閉狀態,用以阻隔該第一資料匯流排12〇訊號傳輸至該 數位控制振盪裝置130。 200828778 該第二切換器165耦接於該第一資料匯流排12〇,用以 傳輸或阻隔該第-資料匯流排m之訊號至該記憶體裝置 H5,該記憶體裝置145耦接於該第二切換器丨65。 當該高精度振盪器處於校準模式時,該第二切換器165 為開啟狀態’依序將該控制字組之第⑻)位元至第。位 兀之好別寫人該記憶體裝置145巾。#該高精度振盪器處 於=作挺.式時,該第:切換器165為關閉狀態,以阻隔該第 貝料匯流排120訊號寫入該記憶體裝置145中。 該第二資料匯流排15〇耦接於該數位控制振盪裝置⑽ 及f。己體&置145之間。該第三切換器i軸接於該記憶 體裝置145,用以傳輸或阻隔該記憶體裝置145之輸出訊號 至δ亥數位控制振盈裝置13 0。 10Indicators, the logic control device 115 respectively sets the values of the (N-i)th to the third bits of the control block according to the indication signal Indicat〇r. When the 咼 precision oscillator is in the working mode, the first switch 125 is in an off state for blocking the transmission of the first data bus 12 signal to the digitally controlled oscillating device 130. The second switch 165 is coupled to the first data bus 12 〇 for transmitting or blocking the signal of the first data bus m to the memory device H5. The memory device 145 is coupled to the first The second switch 丨65. When the high precision oscillator is in the calibration mode, the second switch 165 is in the on state' sequentially (8) bits of the control block to the first. It is good to write a memory device 145 towel. When the high-precision oscillator is in the mode, the switch 165 is turned off to block the signal of the first bus bar 120 from being written into the memory device 145. The second data bus 15 is coupled to the digitally controlled oscillating device (10) and f. Between the body & 145. The third switch i is coupled to the memory device 145 for transmitting or blocking the output signal of the memory device 145 to the alpha-digital control vibration device 130. 10
當該高精度振蘯器處於校準模式時,該第三切換器14〇 為關閉狀態,以阻隔該記憶體裝置145之輸出訊號經由第二 貧料匯,排15〇而傳送至該數位控制錄裝置13G。當該高 精度振盪器處於工作模式時,該第三切換器140為開啟狀 態,以將該記憶體裝置145之輸出訊號經由第二資料匯流排 150而傳送至該數位控制振盪裝置13〇。 名作模式選擇裝置170的第一輸入端連接至該邏輯 控制裝置!15,以接收該邏輯控㈣置115輸出的Readyifi 破該作核式選擇裝置170的第二輸入端接收一模式選擇 訊號MODE。當該高精度振1器處於校準模式時,該邏輯控 制裝置115輸出的Ready訊號及該模式選擇訊號m〇_為 低電位⑼’故該第四切換器⑽為關閉狀態、。當該高精度振 20 200828778 ^ 盪器處於工作模式時,該邏輯控制裝置115輸出的Ready訊 號或該模式選擇訊號MODE為高電位(1)時,該第四切換器 160則為開啟狀態。 該第四切換器160耦接於該數位控制振盪裝置130,用 5 以傳輸或阻隔該數位控制振盪裝置130之該時序訊號 clock。當該高精度振盪器處於校準模式時,該第四切換器 160為關閉狀態,以阻隔該數位控制振盪裝置130所輸出之 該時序訊號clock傳送至該高精度振盪器之輸出訊號 φ CLKOUT 〇 10 當該高精度振盪器處於工作模式時,該第四切換器160 為開啟狀態,以傳輸該數位控制振盪裝置130所輸出之該時 序訊號clock傳送至該高精度振盪器之輸出訊號CLKOUT。 當該高精度振盪器處於校準模式時,該邏輯控制裝置 115輸出低電位(0)之Ready訊號,且一模式選擇訊號MODE 15 為低電位(0)。此時,該第一切換器125及第二切換器165為 開啟狀態,第三切換器140及第四切換器160為關閉狀態。 φ ’當該高精度振盪器處於工作模式時,該邏輯控制裝置115輸 出高電位(1)之Ready訊號以及該模式選擇訊號MODE為高 電位(1)。此時,該第一切換器125及第二切換器165為關閉 20 狀態,第三切換器140及第四切換器160為開啟狀態。 圖2係本發明之具有自校準功能的高精度振盪器的校 準流程圖。其係用以設定一數位控制振盪裝置之N位元控制 字組,該數位控制振盪裝置依據該N位元控制字組以產生一 時序訊號。首先,於步驟S210,執行該振盪器之電路初始 π 200828778 • 化,以將N位元控制字組之每一位元初始化為〇。於步驟 S220,設定執行次數Κ為Ν-1。於步驟S230,設定該Ν位元 控制字組之第Κ位元為1。 於步驟S240,比較該數位控制振盪裝置產生的時序訊 5 號clock與一頻率參考訊號REF_CLK之頻率。當該時序訊號 clock頻率小於該頻率參考訊號REF_CLK之頻率時,執行步 驟S260,否則,執行步驟S250。When the high-precision vibrator is in the calibration mode, the third switch 14 is turned off, so that the output signal blocking the memory device 145 is transmitted to the digital control record via the second lean pool. Device 13G. When the high-precision oscillator is in the active mode, the third switch 140 is turned on to transmit the output signal of the memory device 145 to the digitally controlled oscillating device 13 via the second data bus 150. The first input of the master mode selection device 170 is coupled to the logic control device! 15. The second input of the Readyfi device that receives the output of the logic control (four) 115 outputs a mode selection signal MODE. When the high-precision vibrator is in the calibration mode, the Ready signal output by the logic control unit 115 and the mode selection signal m〇_ are low (9)', so that the fourth switch (10) is in the off state. When the high-precision oscillator 20 200828778 is in the active mode, when the Ready signal output by the logic control device 115 or the mode selection signal MODE is high (1), the fourth switch 160 is in an on state. The fourth switch 160 is coupled to the digitally controlled oscillating device 130 for transmitting or blocking the timing signal clock of the digitally controlled oscillating device 130. When the high-precision oscillator is in the calibration mode, the fourth switch 160 is in an off state to block the output of the timing signal clock output by the digitally controlled oscillating device 130 to the output signal φ CLKOUT 〇10 of the high-precision oscillator. When the high-precision oscillator is in the operating mode, the fourth switch 160 is turned on, and the timing signal clock output by the digital-controlled oscillator 130 is transmitted to the output signal CLKOUT of the high-precision oscillator. When the high precision oscillator is in the calibration mode, the logic control device 115 outputs a Ready signal of low potential (0), and a mode selection signal MODE 15 is low (0). At this time, the first switch 125 and the second switch 165 are in an on state, and the third switch 140 and the fourth switch 160 are in an off state. φ ′ When the high-precision oscillator is in the operation mode, the logic control unit 115 outputs the Ready signal of the high potential (1) and the mode selection signal MODE is high (1). At this time, the first switch 125 and the second switch 165 are in the off state 20, and the third switch 140 and the fourth switch 160 are in the on state. Fig. 2 is a calibration flow chart of the high precision oscillator with self-calibration function of the present invention. It is used to set a N-bit control block of a digitally controlled oscillating device, and the digital control oscillating device controls the block according to the N-bit to generate a timing signal. First, in step S210, the circuit of the oscillator is initially initialized π 200828778 to initialize each bit of the N-bit control block to 〇. In step S220, the number of executions is set to Ν-1. In step S230, the third bit of the unit control word group is set to 1. In step S240, the frequency of the timing signal No. 5 clock and the frequency reference signal REF_CLK generated by the digitally controlled oscillating device is compared. When the timing signal clock frequency is less than the frequency of the frequency reference signal REF_CLK, step S260 is performed; otherwise, step S250 is performed.
於步驟S260中,判定該時序訊號clock頻率小於該頻率 _ 參考訊號REF_CLK之頻率時,設定該N位元控制字組之第K 10 位元為〇。於步驟S250中,判定該時序訊號clock頻率非小於 該頻率參考訊號REF_CLK之頻率時,設定該N位元控制字 組之第(N-1)位元為1。 於步驟S270中,將執行次數K減1。於步驟S280中,判 斷執行次數K是否小於0,若是,表示已經對N位元控制字 15 組設定完成,故執行步驟S290。若否,執行步驟S230。藉 此,重覆步驟S230至步驟S280,以依序設定該N位元控制字 φ 組之第N-2至第0位元。於步驟S290中,儲存該N位元控制字 組。 圖3係本發明之具有自校準功能的高精度振盪器的頻 20 率調整示意圖。其中,該頻率參考訊號REF_CLK的頻率為 6MHz,範圍設定為(-30% )〜(+30% ),該N位元控制字 組為8位元,該數位控制振盪裝置130的頻率步階(Frequency Step)為 0_028MHZ(=6Mx60%/128)。亦即,只要調整該 N 位 12 200828778 兀控制字組的位兀數目,即可調整該數位控制振盪裝置13〇 的頻率步階,而獲得高精度之振盪器。 由上述說明可知,本發明利用漸進方法,逐步求出該 N位元控制字組,利用本發明技術,只要調整該N位元控制 5字組位元數目,即可調整該數位控制振盪裝置130的頻率步 階’而獲得一高精度之振盪器’同時可解決同一晶圓上不 同地方的晶片會産生不同的振盪頻率的問題,並且可避免 振Μ頻率容易隨溫度變化的問題。 ♦ i述實施例僅係為了方便說明而舉例而已,本發明所 10主張之權利範圍自應以申請專利範圍所述為準,而非僅限 於上述實施例。 义 圖式簡單說明】 圖1係本發明之具有自校準汾台匕& 15 塊圖 另目杈+功此的南精度振盪器的方 程圖 圖2係本發明之具有自校準功能的高精度振i器的流 圖3係本發明之具有自校栗Λ ^ 玄… 仪+功月匕的鬲精度振盡哭的相 率調整示意圖。 1的的頻 20 【主要元件符號說明】 頻率偵測裝置 UQ 第一資料匯流排 ι2〇 25 數位控制振盪裝置130 邏輯控制裝置 第一切換器 除頻裝置 115 125 135 13 200828778 第二切換器 165 記憶體裝置 145 第二資料匯流排 150 第三切換器 140 第四切換器 160 工作模式選擇裝置 170 第一輸入端 111 第二輸入端 112 馨 14In step S260, when it is determined that the timing signal clock frequency is less than the frequency of the frequency_reference signal REF_CLK, the K10th bit of the N-bit control block is set to 〇. In step S250, when it is determined that the timing signal clock frequency is not less than the frequency of the frequency reference signal REF_CLK, the (N-1)th bit of the N-bit control block is set to 1. In step S270, the number of executions K is decremented by one. In step S280, it is judged whether or not the number of executions K is less than 0. If so, it indicates that the setting of the N-bit control word 15 group has been completed, and therefore step S290 is executed. If no, step S230 is performed. By this, step S230 to step S280 are repeated to sequentially set the N-2th to 0th bits of the N-bit control word φ group. In step S290, the N-bit control block is stored. Fig. 3 is a schematic diagram showing the frequency 20 rate adjustment of the high precision oscillator with self-calibration function of the present invention. The frequency reference signal REF_CLK has a frequency of 6 MHz, the range is set to (-30%)~(+30%), and the N-bit control block is 8-bit, and the digit controls the frequency step of the oscillating device 130 ( Frequency Step) is 0_028MHZ (=6Mx60%/128). That is, as long as the number of bits of the N bit 12 200828778 兀 control block is adjusted, the frequency step of the digitally controlled oscillating device 13 即可 can be adjusted to obtain a high-precision oscillator. As can be seen from the above description, the present invention uses the progressive method to gradually find the N-bit control block. By using the technique of the present invention, the digital-controlled oscillating device 130 can be adjusted by adjusting the number of N-bit control 5-bit bits. The frequency step 'and obtain a high-precision oscillator' can also solve the problem that the wafers in different places on the same wafer will have different oscillation frequencies, and the vibration frequency can be easily changed with temperature. The present invention is exemplified for the convenience of the description, and the scope of the claims of the present invention is determined by the scope of the patent application, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an equation diagram of a south precision oscillator having a self-calibrating platform and a 15 block diagram of the present invention. FIG. 2 is a high precision of the self-calibration function of the present invention. The flow diagram 3 of the vibrating device is a schematic diagram of the phase rate adjustment of the invention with the self-calibrating Λ 玄 玄 仪 仪 功 功 功 功 功 功 功 功 功 功 。 。 。 。 。 。 。 Frequency of 1 [Description of main component symbols] Frequency detecting device UQ First data bus ι2〇25 Digitally controlled oscillating device 130 Logic control device First switcher frequency dividing device 115 125 135 13 200828778 Second switch 165 Memory Body device 145 second data bus 150 150th switch 140 fourth switch 160 working mode selection device 170 first input terminal 111 second input terminal 112
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