TW200707418A - DSV control apparatus and DSV control method - Google Patents
DSV control apparatus and DSV control methodInfo
- Publication number
- TW200707418A TW200707418A TW095125775A TW95125775A TW200707418A TW 200707418 A TW200707418 A TW 200707418A TW 095125775 A TW095125775 A TW 095125775A TW 95125775 A TW95125775 A TW 95125775A TW 200707418 A TW200707418 A TW 200707418A
- Authority
- TW
- Taiwan
- Prior art keywords
- dsv
- control
- dsv control
- control block
- accumulated value
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
- G11B2020/1457—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof wherein DC control is performed by calculating a digital sum value [DSV]
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc-Dc Converters (AREA)
- Rectifiers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005228235A JP4601512B2 (ja) | 2005-08-05 | 2005-08-05 | Dsv制御装置およびdsv制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200707418A true TW200707418A (en) | 2007-02-16 |
TWI318398B TWI318398B (en) | 2009-12-11 |
Family
ID=37700166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095125775A TWI318398B (en) | 2005-08-05 | 2006-07-14 | Dsv control apparatus and dsv control method |
Country Status (4)
Country | Link |
---|---|
US (1) | US7321320B2 (zh) |
JP (1) | JP4601512B2 (zh) |
CN (1) | CN100570729C (zh) |
TW (1) | TWI318398B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20070005563A (ko) * | 2004-01-19 | 2007-01-10 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 보조 정보신호의 채널 데이터 스트림 내의 삽입 |
ATE422698T1 (de) * | 2004-10-20 | 2009-02-15 | Koninkl Philips Electronics Nv | Verfahren und vorrichtung zur einbettung eines sekundären signals in einen primärdatenbitstrom auf einer optischen platte |
JP2008288674A (ja) * | 2007-05-15 | 2008-11-27 | Renesas Technology Corp | 変調装置 |
KR101082650B1 (ko) * | 2009-01-21 | 2011-11-14 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 및 그 동작 방법 |
JP2011091700A (ja) * | 2009-10-23 | 2011-05-06 | Sony Corp | データ復調装置および方法、並びにプログラム |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3722180B2 (ja) * | 1997-12-12 | 2005-11-30 | ソニー株式会社 | 変調装置および方法、並びに記録媒体 |
JP3985173B2 (ja) | 1998-05-29 | 2007-10-03 | ソニー株式会社 | 変調装置および方法、復調装置および方法、並びにデータ格納媒体 |
JP4138227B2 (ja) * | 2000-06-29 | 2008-08-27 | 富士通株式会社 | データ記録方法およびデータ記録装置並びに光記録媒体 |
JP3692974B2 (ja) * | 2001-07-02 | 2005-09-07 | 日本ビクター株式会社 | 符号化方法、符号化装置、記録媒体及びプログラム |
JP4132804B2 (ja) | 2001-12-11 | 2008-08-13 | ソニー株式会社 | 変調装置および方法、記録媒体、並びにプログラム |
JP4024711B2 (ja) * | 2003-04-23 | 2007-12-19 | シャープ株式会社 | 変調装置、変調方法 |
JP2006236447A (ja) * | 2005-02-23 | 2006-09-07 | Fujitsu Ltd | Dsv調整ビットの決定方法及びdsv調整ビットの決定装置 |
US7142135B1 (en) * | 2005-09-06 | 2006-11-28 | Media Tek Inc. | Modulation methods and systems |
-
2005
- 2005-08-05 JP JP2005228235A patent/JP4601512B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-14 TW TW095125775A patent/TWI318398B/zh not_active IP Right Cessation
- 2006-08-02 US US11/497,260 patent/US7321320B2/en not_active Expired - Fee Related
- 2006-08-04 CN CNB2006101084461A patent/CN100570729C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100570729C (zh) | 2009-12-16 |
US7321320B2 (en) | 2008-01-22 |
JP2007042250A (ja) | 2007-02-15 |
JP4601512B2 (ja) | 2010-12-22 |
CN1909099A (zh) | 2007-02-07 |
US20070030193A1 (en) | 2007-02-08 |
TWI318398B (en) | 2009-12-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |