TW200601420A - Method of forming strained Si/SiGe on insulator with silicon germanium buffer - Google Patents

Method of forming strained Si/SiGe on insulator with silicon germanium buffer

Info

Publication number
TW200601420A
TW200601420A TW094118434A TW94118434A TW200601420A TW 200601420 A TW200601420 A TW 200601420A TW 094118434 A TW094118434 A TW 094118434A TW 94118434 A TW94118434 A TW 94118434A TW 200601420 A TW200601420 A TW 200601420A
Authority
TW
Taiwan
Prior art keywords
sige
layer
strained
insulator
silicon germanium
Prior art date
Application number
TW094118434A
Other languages
English (en)
Other versions
TWI348200B (en
Inventor
Hua-Jie Chen
Stephen W Bedell
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200601420A publication Critical patent/TW200601420A/zh
Application granted granted Critical
Publication of TWI348200B publication Critical patent/TWI348200B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
TW094118434A 2004-06-29 2005-06-03 Method of forming strained si/sige on insulator with silicon germanium buffer TWI348200B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/710,255 US6893936B1 (en) 2004-06-29 2004-06-29 Method of Forming strained SI/SIGE on insulator with silicon germanium buffer

Publications (2)

Publication Number Publication Date
TW200601420A true TW200601420A (en) 2006-01-01
TWI348200B TWI348200B (en) 2011-09-01

Family

ID=34573464

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118434A TWI348200B (en) 2004-06-29 2005-06-03 Method of forming strained si/sige on insulator with silicon germanium buffer

Country Status (7)

Country Link
US (1) US6893936B1 (zh)
EP (1) EP1779422A4 (zh)
JP (1) JP2008505482A (zh)
KR (1) KR20070032649A (zh)
CN (1) CN1954421A (zh)
TW (1) TWI348200B (zh)
WO (1) WO2006011912A1 (zh)

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US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
DE102004062290A1 (de) * 2004-12-23 2006-07-06 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterchips
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US20070010070A1 (en) * 2005-07-05 2007-01-11 International Business Machines Corporation Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers
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TWI439684B (zh) * 2005-07-06 2014-06-01 Nanometrics Inc 具自晶圓或其他工件特定材料層所發射光致發光信號優先偵測之光致發光成像
US20070008526A1 (en) * 2005-07-08 2007-01-11 Andrzej Buczkowski Apparatus and method for non-contact assessment of a constituent in semiconductor workpieces
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
DE102005051332B4 (de) * 2005-10-25 2007-08-30 Infineon Technologies Ag Halbleitersubstrat, Halbleiterchip, Halbleiterbauteil und Verfahren zur Herstellung eines Halbleiterbauteils
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
US7656049B2 (en) 2005-12-22 2010-02-02 Micron Technology, Inc. CMOS device with asymmetric gate strain
US20070176119A1 (en) * 2006-01-30 2007-08-02 Accent Optical Technologies, Inc. Apparatuses and methods for analyzing semiconductor workpieces
US7494856B2 (en) * 2006-03-30 2009-02-24 Freescale Semiconductor, Inc. Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
DE102006019934B4 (de) 2006-04-28 2009-10-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Ausbildung eines Feldeffekttransistors
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
CN100447950C (zh) * 2007-01-26 2008-12-31 厦门大学 低位错密度锗硅虚衬底的制备方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
CN102498542B (zh) 2009-09-04 2016-05-11 住友化学株式会社 半导体基板、场效应晶体管、集成电路和半导体基板的制造方法
CN101882624B (zh) 2010-06-29 2011-09-14 清华大学 在绝缘衬底上形成有高Ge应变层的结构及形成方法
CN102315246B (zh) * 2010-06-30 2013-03-13 中国科学院上海硅酸盐研究所 一种弛豫SiGe虚拟衬底及其制备方法
TW201311842A (zh) * 2011-08-01 2013-03-16 Basf Se 一種製造半導體裝置的方法，其包含在具有３．０至５．５之ｐＨ值之ＣＭＰ組成物的存在下化學機械拋光元素鍺及／或Ｓｉ１－ｘＧｅｘ材料
CN102427068B (zh) * 2011-12-02 2014-06-18 中国科学院上海微***与信息技术研究所 单片集成具有晶格失配的晶体模板及其制作方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微***与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微***与信息技术研究所 一种制备goi的方法
TWI457985B (zh) * 2011-12-22 2014-10-21 Nat Inst Chung Shan Science & Technology Semiconductor structure with stress absorbing buffer layer and manufacturing method thereof
US8518807B1 (en) 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
KR101381056B1 (ko) * 2012-11-29 2014-04-14 주식회사 시지트로닉스 Ⅲ-질화계 에피층이 성장된 반도체 기판 및 그 방법
US9716176B2 (en) * 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
US9343303B2 (en) * 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
WO2016109502A1 (en) * 2014-12-31 2016-07-07 Sunedison Semiconductor Limited Preparation of silicon-germanium-on-insulator structures
KR102257423B1 (ko) 2015-01-23 2021-05-31 삼성전자주식회사 반도체 기판 및 이를 포함하는 반도체 장치
WO2016196060A1 (en) * 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
CN114000120B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于cvd法的应变金刚石生长掺杂方法
CN114000121B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于mbe法的应变金刚石生长掺杂方法及外延结构

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US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6603156B2 (en) 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
FR2842349B1 (fr) * 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
US6812116B2 (en) * 2002-12-13 2004-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Also Published As

Publication number Publication date
CN1954421A (zh) 2007-04-25
TWI348200B (en) 2011-09-01
WO2006011912A1 (en) 2006-02-02
KR20070032649A (ko) 2007-03-22
JP2008505482A (ja) 2008-02-21
US6893936B1 (en) 2005-05-17
EP1779422A1 (en) 2007-05-02
EP1779422A4 (en) 2007-08-01

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