FR2893446B1 - TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE - Google Patents

TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE

Info

Publication number
FR2893446B1
FR2893446B1 FR0511600A FR0511600A FR2893446B1 FR 2893446 B1 FR2893446 B1 FR 2893446B1 FR 0511600 A FR0511600 A FR 0511600A FR 0511600 A FR0511600 A FR 0511600A FR 2893446 B1 FR2893446 B1 FR 2893446B1
Authority
FR
France
Prior art keywords
segment
layer treatment
treatment
layer
segment layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0511600A
Other languages
English (en)
Other versions
FR2893446A1 (fr
Inventor
Cecile Delattre
Nicolas Daval
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0511600A priority Critical patent/FR2893446B1/fr
Priority to US11/356,927 priority patent/US20070111474A1/en
Priority to PCT/EP2006/068420 priority patent/WO2007057381A1/fr
Publication of FR2893446A1 publication Critical patent/FR2893446A1/fr
Application granted granted Critical
Publication of FR2893446B1 publication Critical patent/FR2893446B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
FR0511600A 2005-11-16 2005-11-16 TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE Expired - Fee Related FR2893446B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0511600A FR2893446B1 (fr) 2005-11-16 2005-11-16 TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
US11/356,927 US20070111474A1 (en) 2005-11-16 2006-02-16 Treating a SiGe layer for selective etching
PCT/EP2006/068420 WO2007057381A1 (fr) 2005-11-16 2006-11-14 Traitement d'une couche de sige pour realiser une erosion selective

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0511600A FR2893446B1 (fr) 2005-11-16 2005-11-16 TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE

Publications (2)

Publication Number Publication Date
FR2893446A1 FR2893446A1 (fr) 2007-05-18
FR2893446B1 true FR2893446B1 (fr) 2008-02-15

Family

ID=36699067

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0511600A Expired - Fee Related FR2893446B1 (fr) 2005-11-16 2005-11-16 TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE

Country Status (3)

Country Link
US (1) US20070111474A1 (fr)
FR (1) FR2893446B1 (fr)
WO (1) WO2007057381A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4413580B2 (ja) * 2003-11-04 2010-02-10 株式会社東芝 素子形成用基板の製造方法
DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
FR2950082B1 (fr) * 2009-09-14 2011-10-14 Commissariat Energie Atomique Procede de recristallisation d'une couche
CN103311172A (zh) * 2012-03-16 2013-09-18 中芯国际集成电路制造(上海)有限公司 Soi衬底的形成方法
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10541172B2 (en) 2016-08-24 2020-01-21 International Business Machines Corporation Semiconductor device with reduced contact resistance
US9799618B1 (en) 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
KR20180068591A (ko) 2016-12-14 2018-06-22 삼성전자주식회사 식각용 조성물 및 이를 이용한 반도체 장치 제조 방법
US10930793B2 (en) * 2017-04-21 2021-02-23 International Business Machines Corporation Bottom channel isolation in nanosheet transistors
KR102653665B1 (ko) 2018-09-07 2024-04-04 삼성전자주식회사 식각 조성물 및 이를 이용한 반도체 소자의 제조 방법
SG11202105578RA (en) 2018-12-03 2021-06-29 Fujifilm Electronic Materials Usa Inc Etching compositions

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
US6750130B1 (en) * 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6602613B1 (en) * 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6900094B2 (en) * 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
KR100442105B1 (ko) * 2001-12-03 2004-07-27 삼성전자주식회사 소이형 기판 형성 방법
US6642536B1 (en) * 2001-12-17 2003-11-04 Advanced Micro Devices, Inc. Hybrid silicon on insulator/bulk strained silicon technology
US7042570B2 (en) * 2002-01-25 2006-05-09 The Regents Of The University Of California Porous thin film time-varying reflectivity analysis of samples
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
KR100459440B1 (ko) * 2002-11-29 2004-12-03 엘지전자 주식회사 충전지 및 충전지의 충전방법과 전원공급방법
FR2849715B1 (fr) * 2003-01-07 2007-03-09 Soitec Silicon On Insulator Recyclage d'une plaquette comprenant une structure multicouches apres prelevement d'une couche mince
KR100672933B1 (ko) * 2003-06-04 2007-01-23 삼성전자주식회사 세정 용액 및 이를 이용한 반도체 소자의 세정 방법
JP4700324B2 (ja) * 2003-12-25 2011-06-15 シルトロニック・ジャパン株式会社 半導体基板の製造方法
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US6893936B1 (en) * 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche

Also Published As

Publication number Publication date
FR2893446A1 (fr) 2007-05-18
US20070111474A1 (en) 2007-05-17
WO2007057381A1 (fr) 2007-05-24

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Legal Events

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ST Notification of lapse

Effective date: 20100730