TW200541425A

TW200541425A - Mounting structure of bumpless chip

Info

Publication number: TW200541425A
Application number: TW93116066A
Authority: TW
Inventors: Yeong-Ching Chao; John Liu; Y J Lee
Original assignee: Chipmos Technologies Inc; Chipmos Technologies Bermuda
Priority date: 2004-06-04
Filing date: 2004-06-04
Publication date: 2005-12-16
Also published as: TWI246381B

Abstract

A mounting structure of bumpless chip mainly comprises a substrate, a chip and an ACF (anisotropic conductive film). The chip has an active surface. A plurality of bonding pads are formed on the active surface lack of bumps. The ACF is disposed on the active surface of the chip and covers the bonding pads. The ACF contains a plurality of hard metal particles. When the chip is attached to a surface of the substrate, some of the hard metal particles penetrate the bonding pads of the chip and are electrically connected to the connecting pads of the substrate. Thus the chip can be bumpless boned under low temperature, especially for connection of the optical-electrical chip.

Description

200541425 五、發明說明（1) 【發明所屬之技術領域】本發明係有關於一種晶片之無凸塊結合構造，特別係有關於"種如影像感測晶片專光電晶片之無凸塊結合構造。【先前技術】習知半導體或各式晶片係具有凸塊，以覆晶結合至一基板，目前在影像感測器或光電電子產品之封裝構造中，亦常見在一影像感測晶片具有光作動區之一主動面上製作出凸塊，再覆晶結合至該基板，例如中華民國專利公告第 5 6 6 0 6 7號「C Μ 0 S / C C D影像感測器封裝法」係揭示有一種習知影像感測器之結合構造，請參閱第1圖，該影像感測器丨_ 之凸塊結合構造100係包含一PCB電路基板110、一影像感測器晶片120及一玻璃封蓋130，該PCB電路基板11〇係具有一窗口 111及複數個内引腳1 1 2，該影像感測器晶片1 2〇之一主動面1 21係具有一感測區1 2 2及複數個銲墊1 2 3 , —鈍態層1 2 4係形成於該主動面1 21上，習知地，一凸塊下金屬層 125(under bump meta 1 izat ion, UBM)係以電鍍 (plating)或濺鍍（sputter )方式形成於該些銲墊123上，以利複數個凸塊141形成於一UBM層125上，利用覆晶技術將該影像感測器晶片1 2 0之該些凸塊141結合至該P C B電路籲基板11 0，該感測區1 22係朝向且對應於該窗口 1 π ,以一膠材142填充於該些凸塊141與該PCB電路基板110之間隙，該玻璃封蓋130係同樣以該膠材142黏結於該PCB電路基板 110，由於該些銲墊123上之該UBM層125係以電鍍或濺鐘方200541425 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a bump-free bonding structure of a wafer, and particularly relates to a bump-free bonding structure of an optoelectronic wafer such as an image sensing wafer. . [Previous technology] It is known that semiconductors or various types of wafers have bumps, which are bonded to a substrate by flip chip. At present, in the packaging structure of image sensors or optoelectronic products, it is also common for an image sensing chip to have light action. A bump is made on the active surface of one of the regions, and then flip-chip bonded to the substrate. For example, the Republic of China Patent Publication No. 5 6 0 6 7 "C M 0 S / CCD image sensor packaging method" has revealed a The combined structure of the conventional image sensor is shown in FIG. 1. The combined structure 100 of the image sensor 丨 _ includes a PCB circuit board 110, an image sensor chip 120, and a glass cover 130. The PCB circuit board 110 has a window 111 and a plurality of inner pins 1 12, and one of the image sensor wafers 120 has an active surface 1 21 having a sensing area 1 2 2 and a plurality of solders. A pad 1 2 3, a passive layer 1 2 4 is formed on the active surface 1 21. Conventionally, an under bump meta layer 125 (UBM) is plated or plated. A sputtering method is formed on the pads 123 to facilitate the formation of a plurality of bumps 141 on the pads 123. On the UBM layer 125, the bumps 141 of the image sensor wafer 120 are bonded to the PCB circuit substrate 110 using flip-chip technology, and the sensing area 1 22 is oriented and corresponds to the window 1 π An adhesive material 142 is used to fill the gap between the bumps 141 and the PCB circuit substrate 110, and the glass cover 130 is also bonded to the PCB circuit substrate 110 with the adhesive material 142. The UBM layer 125 is plated or sputtered.

200541425 五、發明說明（2) 式形成，且該些凸塊141係以蒸鑛（evaporation)或電鍵方式形成’容易污染至邊敏感之感測區1 2 2，而影響該影像感測Is晶片1 2 0之品質’又该影像感測器晶片1 2 〇於覆晶接合後，必需以該膠材142填充於該些凸塊丨41之間，以氣密該感測區1 2 2，然而該膠材1 4 2在填充過程具有良好流動性，會溢流而污染該感測區1 2 2，若填充量太少則無法達到氣密效果。【發明内容】本發明之主要目的係在於提供一種晶片之無凸塊結合構造，其係包含有一基板、一晶片及一異方性導電膠 (anisotropic conductive film, ACF)，該異方性導電勝· 係設於該晶片之一主動面而覆蓋該主動面上之複數個銲塾’該異方性導電膠係包含有複數個硬質金屬顆粒，當今晶片貼设於該基板，以該異方性導電膠之部分硬質金屬顆粒電性連接該晶片與該基板，不需要在該晶片之該些銲塾上製作一凸塊下金屬層與對應凸塊而覆晶接合於該基板，特別適合運用於光電晶片之無凸塊接合，可以避免在該凸塊下金屬層與該些凸塊之製作過程中污染該光電晶片之敏感之光作動區，而影響該光電晶片之品質。本發明之次一目的係在於提供一種晶片之無凸塊結合鲁構造二其中一異方性導電膠係包含有複數個硬質金屬顆粒，母一硬質金屬顆粒係具有複數個穿刺端，當一晶片貼設^基板，#分之該些硬質金屬顆粒係以該些穿刺端刺杆蛩上之一氧化層，以增進該硬質金屬200541425 V. Description of the invention (2), and the bumps 141 are formed by evaporation or electric bond method, which easily pollutes the sensitive area to the edge sensitive 1 2 2 and affects the image sensing Is chip. The quality of 1 2 0 'and the image sensor chip 1 2 0 must be filled with the glue 142 between the bumps 41 and 41 to seal the sensing area 1 2 2 after the flip chip bonding. However, the rubber material 1 4 2 has good fluidity during the filling process, and will overflow and pollute the sensing area 1 2 2. If the filling amount is too small, the airtight effect cannot be achieved. [Summary of the Invention] The main purpose of the present invention is to provide a bump-free bonding structure for a wafer, which includes a substrate, a wafer, and an anisotropic conductive film (ACF). · It is set on one of the active surfaces of the wafer and covers a plurality of welding pads on the active surface. 'The anisotropic conductive adhesive system contains a plurality of hard metal particles. Today, the wafer is attached to the substrate to the anisotropy. Part of the hard metal particles of the conductive adhesive are electrically connected to the wafer and the substrate. It is not necessary to make a metal layer under the bumps and corresponding bumps on the solder pads of the wafer to bond the wafer to the substrate. The bumpless bonding of the optoelectronic chip can avoid contaminating the sensitive light actuation area of the optoelectronic chip during the manufacturing process of the metal layer under the bumps and the bumps, thereby affecting the quality of the optoelectronic chip. A second object of the present invention is to provide a bumpless bonding structure of a wafer. One of the anisotropic conductive adhesive systems includes a plurality of hard metal particles, and the mother-hard metal particles system has a plurality of puncture ends. The substrate is attached, and the hard metal particles are divided into an oxide layer on the puncture rods to enhance the hard metal.

第8頁 200541425 五、發明說明（3) 顆粒之電性連接效果。本發明之再一目的係在於提供一構造，當一晶片貼設於一其一曰曰 …凸塊結合個硬質金屬顆粒電性連接^日」後導電膠係以複數連接墊，並以兮晷方日日片之複數個銲墊及該基板之片之-主動面及成，形成凸塊後再填充一膝體之製作步驟。了/去習知晶片先板、-曰Γ ^之Γ片之無凸塊結合構造，其係包含有一基板二片及J異方性導電膠（anisotropic conductive 二基板之該if板有—表面，複數個連接塾係形成孫/ 2 q ，該晶片係具有一主動面，複數個銲墊係形成於该主動面，一氧化層係形成於該些銲墊上，較佳地鄰銲墊之間隔係大於2 〇〇〆m，該異方性導電膠係設於該晶；ί之該主動面而覆蓋該些銲墊，該異方性導電膠係包含有複數個硬質金屬顆粒，較佳地，該些硬質金屬顆粒，，錄顆粒’每一硬質金屬顆粒係具有複數個穿刺端，當 ο亥日日片貼又於该基板之該表面，部分之該些硬質金屬顆粒係以該些穿刺端刺穿該些銲墊上之氧化層，而電性連接至該基板之連接墊。【實施方式】 # 參閱所附圖式，本發明將列舉以下之實施例說明。依本發明之第一具體實施例，一種晶片之無凸塊結合構造20 0，請參閱第2圖，其係包含有一基板210、一晶片 220 及一異方性導電膠23〇(anis〇tr〇pic conductivePage 8 200541425 V. Description of the invention (3) Electrical connection effect of particles. Another object of the present invention is to provide a structure. When a chip is attached to one by one ... the bumps are electrically connected with a hard metal particle, and the conductive adhesive is connected to the pad with a plurality of pads. The manufacturing steps of a plurality of solder pads of the Fangri-Ri film and the active surface of the sheet of the substrate, and forming a bump, and then filling a knee body. The structure of bump-free bonding of the first board of the wafer and the first board of Γ ^, which includes two substrates and an anisotropic conductive adhesive (the surface of the if board of the anisotropic conductive two substrates), A plurality of connection lines form a sun / 2q. The chip system has an active surface, a plurality of pads are formed on the active surface, and an oxide layer is formed on the pads, preferably a spacer system adjacent to the pads. Greater than 2000mm, the anisotropic conductive adhesive is provided on the crystal; the active surface covers the pads, and the anisotropic conductive adhesive contains a plurality of hard metal particles, preferably, The hard metal particles, the recording particles, each hard metal particle has a plurality of puncture ends, when the helium film is pasted on the surface of the substrate, some of the hard metal particles are with the puncture ends. The oxide layer on the solder pads is pierced and electrically connected to the connection pads of the substrate. [Embodiment] # With reference to the drawings, the present invention will enumerate the following embodiments. According to the first specific implementation of the present invention Example, a bumpless bonding structure of a wafer 200, see FIG. 2, which system includes a substrate 210, a chip 220 and an anisotropic conductive adhesive 23〇 (conductive anis〇tr〇pic

HH ιΙϋΗ 第9頁 200541425 五、發明說明（4) 以1111，人0『），該基板21()係選自於玻璃基板、軟性電路板、陶竞電路板與印刷電路板之其中之一，在本實施例中，該基板2 1 0係為一玻璃基板，該基板21 〇係具有一表面 21 1 ’複數個連接墊212係形成於該基板210之該表面21 1，較佳地，該晶片22 0係為一光電晶片，其係選自於影像感測（image sensor)晶片、LCOS(Liquid Crystal OnHH ιΙϋΗ Page 9 200541425 V. Description of the invention (4) According to 1111, person 0 "), the substrate 21 () is selected from one of a glass substrate, a flexible circuit board, a ceramic circuit board, and a printed circuit board. In this embodiment, the substrate 2 10 is a glass substrate, and the substrate 21 0 has a surface 21 1 ′. A plurality of connection pads 212 are formed on the surface 21 1 of the substrate 210. Preferably, the substrate 21 The chip 220 is a photoelectric chip, which is selected from the group consisting of an image sensor chip and LCOS (Liquid Crystal On).

Silicon,液晶矽基板）晶片、CM0S(c〇mplementary Metai Oxide Semiconductor，互補性氧化金屬半導體）晶片與〇〇)(〇18『忌6-(：〇11016(1〇6¥1〇6，電荷竊合元件感測器）晶片之其中之一，亦可為一般之積體電路晶片，在本實施例中’該晶片2 2 0係為一影像感測晶片，該晶片2 2 0係具有一主動面221，該晶片220之該主動面221係包含有一光作動區222，複數個銲墊223係形成於該主動面221且排列於該光作動區222之外周邊，每一相鄰銲墊223之間隔係大於 200 //m ’該晶片220之該主動面221上係形成有一鈍態層224 (passivation layer)，在本實施例中，該晶片220之該些銲墊223係為紹墊，一如氧化紹之氧化層223a係形成於該晶片220之該些銲墊223上。該異方性導電膠230係設於該晶片220之該主動面221 而覆蓋該些銲墊2 2 3，較佳地，該異方性導電膠2 3 〇係塗佈為回字形’以覆蓋該晶片220之該主動面221周邊而不污染該光作動區222，該異方性導電膠230係包含有複數個硬質金屬顆粒231，在本實施中，該些硬質金屬顆粒23ι係為高硬度之鎳顆粒，較佳地，每一硬質金屬顆粒231係具有複Silicon (liquid crystal silicon substrate) chip, CM0S (Complementary Metai Oxide Semiconductor) chip and 〇〇) (〇18 "Ji 6-(: 〇11016 (1 06 ¥ 1 06, charge stealing One of the integrated sensor chips can also be a general integrated circuit chip. In this embodiment, the chip 2 2 0 is an image sensing chip, and the chip 2 2 0 has an active chip. The surface 221, the active surface 221 of the wafer 220 includes a light active area 222, a plurality of pads 223 are formed on the active surface 221 and are arranged outside the light active area 222, and each adjacent pad 223 The interval is greater than 200 // m. A passive layer 224 is formed on the active surface 221 of the wafer 220. In this embodiment, the pads 223 of the wafer 220 are pads. An oxide layer 223a is formed on the bonding pads 223 of the wafer 220. The anisotropic conductive adhesive 230 is disposed on the active surface 221 of the wafer 220 and covers the bonding pads 2 2 3, Preferably, the anisotropic conductive adhesive 23 is coated in a zigzag shape to cover the wafer 220. The active surface 221 does not contaminate the photoactive region 222. The anisotropic conductive adhesive 230 includes a plurality of hard metal particles 231. In this embodiment, the hard metal particles 23 are high-hardness nickel particles. Preferably, each hard metal particle 231 has a complex

第10頁 200541425 五、發明說明（5) 數個穿刺端231a，該些穿刺端23 la係可依該些硬質金屬顆粒2 3 1之結晶型態不同而變化，當該晶片2 2 〇之該異方性導電膠230受一外力而黏結該主動面221與該基板21〇之該表面211 ’該異方性導電膠230係氣密該光作動區2 22於一密閉空間241，且該些硬質金屬顆粒231之該些穿刺端231&係因為該外力之作用而刺穿該氧化層2 23a，以電性連接該晶片220之該些銲墊223及該基板210之對應連接墊212。Page 10 200541425 V. Description of the invention (5) Several piercing ends 231a, the piercing ends 23 la can be changed according to the different crystal types of the hard metal particles 2 31, when the wafer 2 2 0 should be The anisotropic conductive adhesive 230 is bonded to the active surface 221 and the surface 211 of the substrate 21 by an external force. The anisotropic conductive adhesive 230 is air-tight, the light-acting region 2 22 is in a closed space 241, and the The piercing ends 231 of the hard metal particles 231 pierce the oxide layer 2 23a due to the external force to electrically connect the pads 223 of the wafer 220 and the corresponding connection pads 212 of the substrate 210.

該晶片220係以該異方性導電膠230之該些磲質佘屬顆粒231電性連接該基板21 〇之該些連接墊212，並以該異方性導電膠230膠體於該晶片220之該主動面221及該基板210 之該表面211之間形成該密閉空間241，該晶片之無凸塊結合構造200係同時以該異方性導電膠23〇達到電性連接及氣密之需求，可不需要習知在晶片上形成UBM層與凸塊之步驟，減少對光電晶片之光作動區之污染，並簡化先形成凸塊後再填充膠體之製作步驟。依本發明之第二具體實施例，請參閱第3圖，一種晶片之無凸塊結合構造3 〇〇係主要包含一基板3 j 〇、一晶片 320 及一異方性導電膠330 (anis〇tr〇pic conduct iveThe wafer 220 is electrically connected to the connection pads 212 of the substrate 21 with the base metal particles 231 of the anisotropic conductive adhesive 230, and the anisotropic conductive adhesive 230 is gelled on the wafer 220. The sealed space 241 is formed between the active surface 221 and the surface 211 of the substrate 210. The bumpless bonding structure 200 of the wafer simultaneously uses the anisotropic conductive adhesive 23 to achieve electrical connection and airtightness. The step of forming the UBM layer and the bumps on the wafer can be eliminated, reducing the pollution to the light active region of the optoelectronic wafer, and simplifying the manufacturing steps of forming the bumps and then filling the colloids. According to a second specific embodiment of the present invention, please refer to FIG. 3, a bumpless bonding structure 300 of a wafer mainly includes a substrate 3j, a wafer 320, and an anisotropic conductive adhesive 330 (anis. tr〇pic conduct ive

f 1 lm，ACF)，在本實施例中，該基板31〇係為一軟性電路板，该基板3 1〇係具有一第一表面311、一第二表面312及一貫通該基板310之該第一表面311與該第二表面312之窗口 313，複數個連接墊314係形成於該基板31()之該第一表面311且排列於該窗口313之周邊，在本實施例中，該晶片 320係為一影像感測晶片，該晶片32〇係具有一主動面f 1 lm, ACF). In this embodiment, the substrate 310 is a flexible circuit board. The substrate 310 has a first surface 311, a second surface 312, and a substrate penetrating the substrate 310. The window 313 of the first surface 311 and the second surface 312, and a plurality of connection pads 314 are formed on the first surface 311 of the substrate 31 () and arranged around the window 313. In this embodiment, the wafer The 320 series is an image sensing chip, and the 32 series has an active surface.

200541425 五 '發明說明（6) 321 ’該晶片320之該主動面321係包含有一光作動區322，複數個銲墊3 2 3係形成於該主動面3 2 1且排列於該光作動區 322之外周邊，每一相鄰銲墊323之間隔係大於2〇〇，該晶片32 0之該主動面321上係形成有一鈍態層324，在本實施例中’該晶片3 2 0之該些輝塾3 2 3係為雀呂塾，一如氧化在呂之氧化層323a係形成於該晶片320之該些銲塾323上。該異方性導電膠330係設於該晶片320之該主動面321 而覆蓋該些録塾3 2 3，較佳地，該異方性導電膠3 3 0係塗佈為回字形，以覆蓋該晶片320之該主動面321外周邊而不污染该光作動區3 2 2 ’該異方性導電膠3 3 0係包含有複數個硬質金屬顆粒3 31，在本實施例中，該些硬質金屬顆粒3 3 1係為高硬度之鎳顆粒，較佳地，每一硬質金屬顆粒33 1係具有複數個穿刺端331a，當該晶片320上之該異方性導電膠 330受一外力而黏結該主動面321與該基板310之該第一表面311，該光作動區322係朝向且對應於該基板3 10之該窗口 313，且該些硬質金屬顆粒331之該些穿刺端331a係因為該外力之作用而刺穿該氧化層32 3a，以電性連接該晶片 320之該些銲墊323與該基板310之對應連接墊314，在本實施例中，另結合有一透明蓋板340，其係以一黏膠351將該透明蓋板340黏結於該基板3 10之該第二表面312，該透明蓋板340與該晶片320之該主動面321係於該基板310之該窗口 313處形成一密閉空間352，該光作動區322係氣密於該密閉空間352。、該晶片320係以該異方性導電膠330之該些硬質金屬顆200541425 Five 'invention description (6) 321' The active surface 321 of the wafer 320 includes a light active area 322, and a plurality of pads 3 2 3 are formed on the active surface 3 2 1 and arranged in the light active area 322 At the outer periphery, the distance between each adjacent pad 323 is greater than 200. A passive layer 324 is formed on the active surface 321 of the wafer 32. In this embodiment, the wafer 3 2 0 These fluorenes 3 2 3 are lutes, and the oxide layer 323a, which is oxidized on lutes, is formed on the solder 323s of the wafer 320. The anisotropic conductive adhesive 330 is disposed on the active surface 321 of the wafer 320 to cover the recordings 3 2 3. Preferably, the anisotropic conductive adhesive 3 3 0 is coated in a zigzag shape to cover The outer periphery of the active surface 321 of the chip 320 does not contaminate the photoactive region 3 2 2 'The anisotropic conductive adhesive 3 3 0 contains a plurality of hard metal particles 3 31. In this embodiment, the hard The metal particles 3 3 1 are nickel particles of high hardness. Preferably, each hard metal particle 33 1 has a plurality of puncture ends 331 a. When the anisotropic conductive adhesive 330 on the wafer 320 is bonded by an external force, The active surface 321 and the first surface 311 of the substrate 310, the light actuation region 322 is oriented and corresponds to the window 313 of the substrate 310, and the puncture ends 331a of the hard metal particles 331 are due to the The external force penetrates the oxide layer 32 3a to electrically connect the solder pads 323 of the wafer 320 with the corresponding connection pads 314 of the substrate 310. In this embodiment, a transparent cover plate 340 is further incorporated, which An adhesive 351 is used to adhere the transparent cover 340 to the second surface 312 of the substrate 3 10. The transparent cover plate 340 of the wafer 320 based on the active surface 321 of the window 310 at the mouth of the substrate 313 is formed a closed space 352, the light-based active area 322 to the hermetically sealed space 352. The chip 320 is made of the hard metal particles of the anisotropic conductive adhesive 330

第12頁 200541425 五、發明說明（7) 粒331電性連接該基板31 〇之該些連接墊314，益以該異方性導電膠330膠體黏結該晶片32〇之該主動面321及該基板 310之該第一表面3U，該晶片之無凸塊結合構造3〇〇係同時以該異方性導電膠33〇達到電性連接及氣密之需求，可不，要習知在晶片上形成UBM層與凸塊之步驟，減少對光 ^晶片之光作動區之污染，並簡化先形成凸塊後再填充膠體之製作步驟。本發明之保護範圍當視後附之申請專利範圍所界定者圍内％ ί何热知此項技藝者，在不脫離本發明之精神和範之任何變化與修改，均屬於本發明之保護範圍。Page 12 200541425 V. Description of the invention (7) The particles 331 are electrically connected to the connection pads 314 of the substrate 31, and the anisotropic conductive adhesive 330 gel is used to bond the active surface 321 and the substrate of the wafer 32. The first surface 3U of 310, and the bump-free bonding structure 300 of the wafer simultaneously uses the anisotropic conductive adhesive 33 to achieve the electrical connection and air-tight requirements. However, it is necessary to be familiar with the formation of UBM on the wafer. The steps of layers and bumps reduce the pollution to the light active area of the light wafer, and simplify the manufacturing steps of forming bumps and then filling the colloids. The scope of protection of the present invention shall be determined by the scope of the scope of patent application attached below. Anyone who knows that this skill does not depart from the spirit and scope of the present invention belongs to the scope of protection of the present invention.

第13頁 200541425 圖式簡單說明【圖式簡單說明】第1 圖：習知影像感測器之凸塊結合構造之截面示意圖；第2 圖：依本發明之第一實施例，一種晶片之無凸塊結合構造之截面示意圖；及第3 圖：依本發明之第二實施例，一種晶片之無凸塊結合構造之截面示意圖。元件符號簡單說明： 1 00影像感測器之凸塊結合構造 110 PCB電路基板 111 窗口 112 内引腳 120 影像感測杰晶片 121 主動面 122 感測區 123 銲墊 124 鈍態層 125 UBM層 130 玻璃封蓋 141 凸塊 142 膠材 200 晶片之無凸塊結合構造 210 基板 211 表面 212 連接墊 220 晶片 221 主動面 222 光作動區 223 銲墊 223a 氧化層 224 鈍態層 230 異方性導電膠231 硬質金屬顆粒231a 穿刺端 241 密閉空間 300 晶片之無凸塊結合構造 310 基板 311 第一表面 312 第二表面 313 窗口 314 連接墊Page 13 200541425 Brief description of the drawings [Simplified description of the drawings] Figure 1: A schematic cross-sectional view of a conventional bump bonding structure of an image sensor; Figure 2: According to a first embodiment of the present invention, a chip has no A schematic cross-sectional view of a bump bonding structure; and FIG. 3 is a schematic cross-sectional view of a bumpless bonding structure of a wafer according to a second embodiment of the present invention. Brief description of component symbols: 1 00 bump combination structure of image sensor 110 PCB circuit board 111 window 112 inner pin 120 image sensor chip 121 active surface 122 sensing area 123 solder pad 124 passivation layer 125 UBM layer 130 Glass cover 141 Bump 142 Adhesive material 200 Wafer-free bonding structure of the substrate 210 Substrate 211 Surface 212 Connection pad 220 Wafer 221 Active surface 222 Photoactive region 223 Pad 223a Oxidation layer 224 Passive layer 230 Anisotropic conductive adhesive 231 Hard metal particles 231a Piercing end 241 Closed space 300 Bumpless structure of wafer 310 Substrate 311 First surface 312 Second surface 313 Window 314 Connection pad

第14頁 200541425_ 圖式簡單說明 320 晶片 321 主動面 322 323 銲墊 323a 氧化層 324 330 異方性導電膠331 硬質金屬顆粒331a 340 透明蓋板 351 黏膠 352 密閉空間光作動區鈍態層穿刺端Page 14 200541425_ Brief description of the diagram 320 Wafer 321 Active surface 322 323 Solder pad 323a Oxidation layer 324 330 Anisotropic conductive adhesive 331 Hard metal particles 331a 340 Transparent cover 351 Adhesive 352 Confined space Light active area Passive layer Piercing end

Claims

200541425 __ 六、申請專利範圍【申請專利範圍】 1、一種晶片之無凸塊結合構造’包含：一基板，其係具有一第一表面及一第二表面，複數個連接墊係形成於該基板之該第一表面； · 一晶片，其係設於該基板之該第一表面’該晶片係具 · 有一主動面，複數個銲墊係形成於該主動面，及一異方性導電膠（anisotropic conduct ive f i lm， ACF)，其係設於該晶片之該主動面而覆蓋該些銲墊，該異方性導電膠係包含有複數個硬質金屬顆粒，以電性連接該晶片之該些銲墊及該基板之對應連接墊。 2、如申請專利範圍第1項所述之晶片之無凸塊結合構造’其中每一硬質金屬顆粒係具有複數個穿刺端。 3、如申請專利範圍第1項所述之晶片之無凸塊結合構造’其中該些硬質金屬顆粒係為鎳顆粒。 4、如申請專利範圍第2項所述之晶片之無凸塊結合構造’其中一氧化層係形成於該晶片之該些銲整上。 5、如申請專利範圍第4項所述之晶片之無凸塊結合構造’其中部分該些硬質金屬顆粒之該些穿刺端係刺穿該氧化層。 6、如申請專利範圍第4項所述之晶片之無凸塊結合構造’其中該晶片之該些蛘墊係為I呂墊。 7、如申請專利範圍第1項所述之晶片之無凸塊結合構造’其中該晶片係為一光電晶片。 8、如申請專利範圍第7項所述之晶片之無凸塊結合構200541425 __ VI. Scope of patent application [Scope of patent application] 1. A bump-free bonding structure of a wafer includes: a substrate having a first surface and a second surface, and a plurality of connection pads are formed on the substrate The first surface; a wafer, which is provided on the first surface of the substrate; the wafer system has an active surface, a plurality of pads are formed on the active surface, and an anisotropic conductive adhesive ( anisotropic conduct ive fi lm (ACF), which is provided on the active surface of the chip to cover the pads, and the anisotropic conductive adhesive contains a plurality of hard metal particles to electrically connect the chips to the chip. A solder pad and a corresponding connection pad of the substrate. 2. The bump-free bonded structure of a wafer as described in item 1 of the scope of the patent application, wherein each hard metal particle has a plurality of puncture ends. 3. The bump-free bonded structure of the wafer as described in item 1 of the scope of the patent application, wherein the hard metal particles are nickel particles. 4. The bump-free bonding structure of the wafer as described in item 2 of the scope of the patent application, wherein an oxide layer is formed on the welds of the wafer. 5. The bump-free bonding structure of the wafer as described in item 4 of the scope of the patent application, wherein the piercing ends of some of the hard metal particles pierce the oxide layer. 6. The bumpless bonding structure of the wafer as described in item 4 of the scope of the patent application, wherein the pads of the wafer are I-lu pads. 7. The bumpless bonding structure of a wafer as described in item 1 of the scope of the patent application, wherein the wafer is a photovoltaic wafer. 8. The bumpless bonding structure of the wafer as described in item 7 of the scope of patent application

200541425 六、申請專利範圍造，其中該晶片之該主動面係包含有一光作動區，該些銲墊係排列於該光作動區之外周邊。 9、如申請專利範圍第8項所述之晶片之無凸塊結合構造’其中該異方性導電膠係塗佈為回字形，以覆蓋該些銲墊而不污染該光作動區。 10、如申請專利範圍第8項所述之晶片之無凸塊結合構造’其中該異方性導電膠係黏結該晶片之該主動面與該基板之該第一表面，並氣密該光作動區。200541425 6. The scope of the patent application, wherein the active surface of the wafer includes a light-acting area, and the pads are arranged outside the light-acting area. 9. The bump-free bonding structure of a wafer as described in item 8 of the scope of the patent application, wherein the anisotropic conductive adhesive is coated in a zigzag shape to cover the pads without contaminating the photo-action area. 10. The bump-free bonding structure of the wafer as described in item 8 of the scope of the patent application, wherein the anisotropic conductive adhesive is used to bond the active surface of the wafer and the first surface of the substrate, and hermetically actuate the light. Area.

11、如申請專利範圍第7項所述之晶片之無凸塊結合構 ie ’其中该晶片係選自於影像感測（image sens〇r)晶片、 LCOSaiquid Crystal On Silicon，液晶矽基板）晶片、 CMOS(Complementary Metal Oxide Semiconductor，互補性氧化金屬半導體）晶片與CCD(charge —c〇upled Device，電荷藕合元件感測器）晶片之其中之一。 1 2、如申請專利範圍第1項所述之晶片之無凸塊結合構造’其中該晶片之相鄰銲墊之間隔係大於2〇〇从m。 13、如申請專利範圍第1或8項所述之晶片之無凸塊結合構造’其中該基板係具有一窗口，其係貫通該基板之該第一表面與該第二表面。11. The bumpless bonding structure of the wafer as described in item 7 of the scope of the patent application, wherein the wafer is selected from an image sensing wafer, an LCOSaiquid Crystal On Silicon (liquid crystal silicon substrate) wafer, One of a CMOS (Complementary Metal Oxide Semiconductor) chip and a CCD (charge-coupled device) chip. 1 2. The bumpless bonding structure of a wafer as described in item 1 of the scope of the patent application, wherein the distance between adjacent pads of the wafer is greater than 200 to m. 13. The bump-free bonding structure of a wafer as described in item 1 or 8 of the scope of the patent application, wherein the substrate has a window that penetrates the first surface and the second surface of the substrate.

14、如申請專利範圍第丨3項所述之晶片之無凸塊結合構造’其中該晶片之該光作動區係朝向且對應於該基板之該窗口〇 15、如申請專利範圍第i 3項所述之晶片之無凸塊結合巧造，其中該基板之該些連接墊係棑列於該窗口之周邊。14. The bump-free bonding structure of the wafer as described in the scope of patent application No. 丨 3, wherein the light actuating area of the wafer is oriented and corresponds to the window of the substrate. The bump-free combination of the wafer is ingeniously made, wherein the connection pads of the substrate are lined up around the window.

第17頁 200541425Page 17 200541425

1 二範圍第13，所述之晶片之無凸塊結合構表面，、今—透明蓋板，其係結合於該基板之該第二一密閉i間盍板與該晶片之該主動面係於該窗口處形成 1 7 、七由《χ太、& °巧專利範圍第1 6項所述之晶片之無凸塊結合構 ^ ’其中該晶片之該光作動區係氣密於該密閉空間。 18 如申请專利範圍第1項所述之晶片之無凸塊結合構造’其中該基板係選自於玻璃基板、軟性電路板、陶瓷電路板與印刷電路板之其中之一。1 The second range of the 13th, the bumpless bonding structure surface of the wafer, the present-transparent cover plate, which is bonded to the second and hermetically sealed i-panel of the substrate and the active surface of the wafer is The bump-free bonding structure of the wafer as described in item 16 of the "Chi Tai, & ° Patent Range No. 16" is formed at the window ^ 'wherein the light-acting region of the wafer is hermetically sealed in the confined space . 18 The bump-free bonding structure of a wafer as described in item 1 of the scope of the patent application, wherein the substrate is selected from one of a glass substrate, a flexible circuit board, a ceramic circuit board, and a printed circuit board.

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