TW200509312A - Magnetoresistive random access memory device structures and methods for fabricating the same - Google Patents

Magnetoresistive random access memory device structures and methods for fabricating the same

Info

Publication number
TW200509312A
TW200509312A TW093110733A TW93110733A TW200509312A TW 200509312 A TW200509312 A TW 200509312A TW 093110733 A TW093110733 A TW 093110733A TW 93110733 A TW93110733 A TW 93110733A TW 200509312 A TW200509312 A TW 200509312A
Authority
TW
Taiwan
Prior art keywords
memory element
element device
fabricating
methods
memory device
Prior art date
Application number
TW093110733A
Other languages
Chinese (zh)
Other versions
TWI349980B (en
Inventor
Gregory Grynkewich
Mark Deherrera
Mark A Durlam
Clarence Tracy
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200509312A publication Critical patent/TW200509312A/en
Application granted granted Critical
Publication of TWI349980B publication Critical patent/TWI349980B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Abstract

A method for fabricating an MRAM device structure (10) includes providing a substrate (12) on which is formed a first transistor (14) and a second transistor (14). An operative memory element device (60) is formed in electrical contact with the first transistor (14). At least a portion of a false memory element device (58) is formed in electrical contact with the second transistor (14). A first dielectric layer (62) is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via (66) to the at least a portion of a false memory element device (58) and a second via (64) to the operative memory element device (60). An electrically conductive interconnect layer (68) is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device (58) to the operative memory element device (64).
TW093110733A 2003-04-16 2004-04-16 Magnetoresistive random access memory device structures and methods for fabricating the same TWI349980B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/417,851 US6784510B1 (en) 2003-04-16 2003-04-16 Magnetoresistive random access memory device structures

Publications (2)

Publication Number Publication Date
TW200509312A true TW200509312A (en) 2005-03-01
TWI349980B TWI349980B (en) 2011-10-01

Family

ID=32908347

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093110733A TWI349980B (en) 2003-04-16 2004-04-16 Magnetoresistive random access memory device structures and methods for fabricating the same

Country Status (6)

Country Link
US (2) US6784510B1 (en)
JP (1) JP2006523963A (en)
KR (1) KR101036722B1 (en)
CN (1) CN100449788C (en)
TW (1) TWI349980B (en)
WO (1) WO2004095459A2 (en)

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KR102399342B1 (en) * 2015-08-21 2022-05-19 삼성전자주식회사 Memory device and method for manufacturing the same
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US11469268B2 (en) * 2016-03-18 2022-10-11 Intel Corporation Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures
CN109713119A (en) * 2017-10-25 2019-05-03 上海磁宇信息科技有限公司 A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
CN109713120A (en) * 2017-10-25 2019-05-03 上海磁宇信息科技有限公司 A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line
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Also Published As

Publication number Publication date
US6890770B2 (en) 2005-05-10
CN1774816A (en) 2006-05-17
CN100449788C (en) 2009-01-07
KR20060009844A (en) 2006-02-01
US20040257902A1 (en) 2004-12-23
US6784510B1 (en) 2004-08-31
WO2004095459A2 (en) 2004-11-04
TWI349980B (en) 2011-10-01
JP2006523963A (en) 2006-10-19
WO2004095459A3 (en) 2005-03-24
KR101036722B1 (en) 2011-05-24

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