CN111863865B - Pseudo-magnetic tunnel junction unit - Google Patents
Pseudo-magnetic tunnel junction unit Download PDFInfo
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- CN111863865B CN111863865B CN201910334319.0A CN201910334319A CN111863865B CN 111863865 B CN111863865 B CN 111863865B CN 201910334319 A CN201910334319 A CN 201910334319A CN 111863865 B CN111863865 B CN 111863865B
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- 239000010410 layer Substances 0.000 claims abstract description 103
- 230000005291 magnetic effect Effects 0.000 claims abstract description 103
- 238000000034 method Methods 0.000 claims abstract description 36
- 230000002093 peripheral effect Effects 0.000 claims abstract description 29
- 230000008569 process Effects 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000012790 adhesive layer Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 4
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000007788 roughening Methods 0.000 claims abstract description 4
- 238000004528 spin coating Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- 229910019236 CoFeB Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 4
- 230000005415 magnetization Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
The pseudo magnetic tunnel junction unit of the invention deposits a layer of bottom electrode on the prepared complementary metal oxide semiconductor which is suitable for the magnetic random access memory, and planarizes the bottom electrode by adopting a chemical mechanical polishing method; sequentially depositing an adhesive layer and a photoresist layer on the bottom electrode by a spin coating method; exposing the peripheral circuit unit area; developing the peripheral circuit unit area, and removing the adhesive layer and the photoresist layer in the area; surface roughening is carried out on the bottom electrode of the peripheral circuit unit area; removing the adhesive layer and the photoresist layer of the magnetic tunnel junction region; sequentially depositing a pseudo magnetic tunnel junction reference layer, a barrier layer and a memory layer on a bottom electrode of a peripheral circuit unit area, sequentially depositing a magnetic tunnel junction reference layer, a barrier layer and a junction memory layer on the bottom electrode of the magnetic tunnel junction area, and depositing a hard mask layer on the magnetic tunnel junction memory layer and the pseudo magnetic tunnel junction memory layer; patterning of the magnetic tunnel junction and the pseudo magnetic tunnel junction is completed by adopting a photoetching process and an etching process.
Description
Technical Field
The present invention relates to the field of magnetic random access memory (MRAM, magnetic Radom Access Memory), and more particularly, to a pseudo magnetic tunnel junction cell (Dummy-Magnetic Tunnel Junction Unit) structure.
Background
In recent years, MRAM using a magnetic tunnel junction (MTJ, magnetic Tunnel Junction) has been considered as a future solid-state nonvolatile memory, which has characteristics of high-speed reading and writing, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer located in the middle; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
To be able to record information in such magnetoresistive elements, a writing method based on spin momentum transfer or spin transfer torque (STT, spin Transfer Torque) switching technology is proposed, such MRAM being called STT-MRAM. STT-MRAM is further divided into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM) depending on the direction of magnetic polarization, which have better performance. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the spin-polarized current to be injected for writing or switching operations is also smaller. Thus, this writing method can achieve both device miniaturization and current reduction.
The magnetic random access memory internal circuit includes two regions, namely a magnetic tunnel junction region (MTJArray area) and a peripheral circuit region (periherey). In the prior art (e.g., US20180277593A1, etc.), a magnetic tunnel junction region (MTJ Array area) and a surrounding circuit region (peripheral) are required to be manufactured using a plurality of photomasks (masks), respectively, and the magnetic tunnel film of the surrounding circuit region (peripheral) is removed by etching (etching) or Chemical Mechanical Polishing (CMP).
In the prior art, a Magnetic Tunnel Junction (MTJ) area and a surrounding circuit area (peripheral) are required to be manufactured by a plurality of photomasks (masks), which greatly increases the manufacturing cost and the process complexity. The magnetic tunnel film of the surrounding circuit area (perihery) needs to be removed, and the prior art adopts etching (etching) or Chemical Mechanical Polishing (CMP) to remove, and defects can be generated in the removing process, which can reduce the yield of products.
Disclosure of Invention
The invention provides a pseudo magnetic tunnel junction unit aiming at the problems and the defects existing in the prior art.
The invention solves the technical problems by the following technical proposal:
the invention provides a pseudo magnetic tunnel junction cell with excellent electrical conductivity, comprising the following steps:
step one: depositing a layer of bottom electrode on the manufactured CMOS substrate with the metal connecting wire through holes, which is suitable for the surface polishing of the magnetic random access memory, and flattening the bottom electrode by adopting a chemical mechanical polishing method;
step two: sequentially depositing an adhesive layer and a photoresist layer on the bottom electrode by a spin coating method;
step three: exposing a peripheral circuit region of the magnetic random access memory;
step four: developing the peripheral circuit region of the magnetic random access memory, and removing the adhesive layer and the photoresist layer in the region;
step five: surface roughening a bottom electrode of a peripheral circuit region of the magnetic random access memory;
step six: removing the bonding layer and the photoresist layer of the magnetic tunnel junction array region of the magnetic random access memory;
step seven: a physical vapor deposition process is adopted to deposit a magnetic tunnel junction material, namely a pseudo magnetic tunnel junction reference layer, a pseudo magnetic tunnel junction barrier layer and a pseudo magnetic tunnel junction memory layer are sequentially deposited on a bottom electrode of a peripheral circuit unit area of the magnetic random access memory by adopting the physical vapor deposition process, and a physical vapor deposition process is adopted to sequentially deposit the magnetic tunnel junction reference layer, the magnetic tunnel junction barrier layer, the magnetic tunnel junction memory layer and a hard mask layer on the bottom electrode of the magnetic tunnel junction area of the magnetic random access memory;
step eight: patterning of the magnetic tunnel junction and the pseudo magnetic tunnel junction is completed by adopting a photoetching process and an etching process.
The invention has the positive progress effects that:
the invention uses one photomask plate (mask) to complete the circuit connection of the magnetic tunnel junction region (MTJ Array area) and the surrounding circuit region (peripheral), thereby reducing the cost.
The invention does not use a Chemical Mechanical Polishing (CMP) method to remove the magnetic tunnel film (MTJ) of the peripheral circuit area (periherey), thereby reducing the defect generation and improving the yield.
Drawings
FIGS. 1 a-1 h are detailed step diagrams of a pseudo magnetic tunnel junction cell (Dummy-MTJ).
Fig. 2 is a schematic diagram of a replacement of VIA (VIA) with a pseudo magnetic tunnel junction cell (Dummy-MTJ) in a peripheral circuit.
FIG. 3 is a flow chart of the preparation of a pseudo magnetic tunnel junction cell (Dummy-MTJ).
Reference numerals illustrate: a 101-Magnetic Tunnel Junction (MTJ) bottom electrode, 102-adhesion layer, 103-photoresist layer, 111-Magnetic Tunnel Junction (MTJ) reference layer, 112-Magnetic Tunnel Junction (MTJ) barrier layer, 113-Magnetic Tunnel Junction (MTJ) memory layer, 211-pseudomagnetic tunnel junction cell (Dummy-MTJ) reference layer, 212-pseudomagnetic tunnel junction cell (Dummy-MTJ) barrier layer, 213-pseudomagnetic tunnel junction cell (Dummy-MTJ) memory layer, 214-hard mask layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memory (MRAM), nor is it limited to any process sequence or flow, provided that the resulting product or device is the same or similar to the following preferred process sequence or flow.
Step one: a bottom electrode 101 is deposited by physical sputtering on a Complementary Metal Oxide Semiconductor (CMOS) that has been fabricated to be suitable for use in a magnetic random access memory (pSTT-MRAM) and planarized by Chemical Mechanical Polishing (CMP). As shown in fig. 1 a. Wherein the bottom electrode material can be a single-layer film or multi-layer films formed by a plurality of types in Ta, taN, taON, ti, tiN, tiON, ru, pt, coFeB, preferably TiN with the thickness of 10-30nm.
Step two: an adhesive layer 102 and a photoresist layer 103 are sequentially deposited on the bottom electrode 101 by spin coating. As shown in fig. 1 b. The material of the deposited adhesive layer 102 is typically PMGI or LOR, and the thickness is 50-100nm, and the photoresist layer thickness is typically 300-500nm.
Step three: a peripheral circuit unit (Periphery Circuit Unit) region of a Magnetic Random Access Memory (MRAM) is exposed. As shown in fig. 1 c.
Step four: the peripheral circuit unit (Periphery Circuit Unit) region of the Magnetic Random Access Memory (MRAM) is developed and the adhesive layer 102 and photoresist layer 103 are removed from this region. As shown in fig. 1 d.
Step five: surface roughening of bottom electrode of peripheral circuit unit (Periphery Circuit Unit) region of Magnetic Random Access Memory (MRAM), cleaning with SC-1 solution of proper ammonia concentration or Cl 2 /Ar、SF 6 、CF 4 /CHF 3 、CF 4 /O 2 Or CF (compact flash) 4 /N 2 Plasma ion reactive etching (RIE) processes the bottom electrode of the peripheral circuit unit (Periphery Circuit Unit) region to roughen its surface. As shown in fig. 1 e.
Step six: the adhesion layer 102 and photoresist layer 103 of the Magnetic Tunnel Junction (MTJ) region of a Magnetic Random Access Memory (MRAM) are removed, typically using a lift off process. As shown in fig. 1 f.
Step seven: a physical vapor deposition (Physical Vapor Deposition, PVD) process is used to sequentially deposit a pseudo magnetic tunnel junction reference layer 211, a pseudo magnetic tunnel junction barrier layer 212, and a pseudo magnetic tunnel junction memory layer 213 on the bottom electrode of the peripheral circuit cell region of the mram, a physical vapor deposition process is used to sequentially deposit a magnetic tunnel junction reference layer 111, a magnetic tunnel junction barrier layer 112, and a magnetic tunnel junction memory layer 113 on the bottom electrode of the magnetic tunnel junction region of the mram, and a hard mask layer 214 is deposited on the magnetic tunnel junction memory layer 213 and the pseudo magnetic tunnel junction memory layer 113. As shown in fig. 1 g.
Further, the total thickness of the magnetic tunnel junction multilayer film is 4nm to 40nm.
Still further, pseudomagnetic tunnel junction reference layer 211 typically has a [ Co/(Ni, pd, pt) ] n/Co/Ru/[ Co/(Ni, pd, pt) ] m/(Ta, W, mo, hf, coTa, feTa, taCoFeB)/CoFeB (where n > m, m.gtoreq.0) superlattice multilayer film structure, typically requiring a seed layer, such as: ta/Pt, ta/Ru, pt/Ru, etc., which preferably have a total reference layer thickness of 2-20 nm.
Further, the pseudomagnetic tunnel junction barrier layer 212 is a non-magnetic metal oxide, preferably MgO, having a thickness of 0.5nm to 3nm.
Further, pseudomagnetic tunnel junction memory layer 213 is typically CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo, hf)/CoFeB, which is preferably 0.8nm to 2nm thick. A capping layer, preferably MgO, mg or Ti, is typically deposited again after the memory layer 213 is deposited.
Still further, the hard mask layer 214 is typically Ta, taN or Ta/TaN. The thickness is 60-100nm.
The constituent materials of the pseudo magnetic tunnel junction (Dummy-MTJ) reference layer 211, the barrier layer 212, the memory layer 213 and the Magnetic Tunnel Junction (MTJ) reference layer 111, the barrier layer 112, the memory layer 113 are identical, and the deposition is completed simultaneously in a physical vapor deposition (Physical Vapor Deposition, PVD) process chamber. But because the bottom electrode of the pseudomagnetic tunnel junction (Dummy-MTJ) region is locally roughened to obtain a poor quality pseudomagnetic tunnel junction (Dummy-MTJ) barrier layer 212, this will cause the presence of a large number of Pin Hole conductive channels due to the very rough interface between such barrier layer 212 and reference layer 211/memory layer 213, which will directly result in conduction from reference layer 211 to memory layer 213. Therefore, a pseudo magnetic tunnel junction cell (Dummy-MTJ Unit) may be placed in the peripheral region (peripheral Unit) of the MRAM circuit to replace the VIA (VIA).
Step eight: patterning of magnetic tunnel junctions (MTJ array) and pseudo magnetic tunnel junctions (Dummy-MTJ) is accomplished using photolithography and etching processes. As shown in fig. 1 h.
The circuit connection can be accomplished as well, using a pseudo magnetic tunnel junction (Dummy-MTJ) instead of a VIA (VIA) in the surrounding circuit area (periherey) of the Magnetic Random Access Memory (MRAM). Thus, only one photomask (Mask) is needed to complete the circuit connection of the magnetic tunnel junction region (MTJ Array area) and the surrounding circuit region (peripheral). Whereas the prior art requires at least 2 photomasks (masks) to complete the circuit connection. This will undoubtedly reduce the complexity of the process, which is advantageous for reducing the production costs
By adopting a pseudo magnetic tunnel junction (Dummy-MTJ) scheme, etching (etching) or Chemical Mechanical Polishing (CMP) is not needed to remove magnetic tunnel films of surrounding circuit areas (perithery), so that defects are fewer, and the yield is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (10)
1. A pseudomagnetic tunnel junction cell characterized by electrical conductivity comprising the steps of:
step one: depositing a layer of bottom electrode on the manufactured CMOS substrate with the metal connecting wire through holes, which is suitable for the surface polishing of the magnetic random access memory, and flattening the bottom electrode by adopting a chemical mechanical polishing method;
step two: sequentially depositing an adhesive layer and a photoresist layer on the bottom electrode by a spin coating method;
step three: exposing a peripheral circuit region of the magnetic random access memory;
step four: developing the peripheral circuit region of the magnetic random access memory, and removing the adhesive layer and the photoresist layer in the region;
step five: surface roughening a bottom electrode of a peripheral circuit region of the magnetic random access memory;
step six: removing the adhesive layer and the photoresist layer of the magnetic tunnel junction region of the magnetic random access memory;
step seven: a physical vapor deposition process is adopted to deposit a magnetic tunnel junction material, namely a pseudo magnetic tunnel junction reference layer, a pseudo magnetic tunnel junction barrier layer and a pseudo magnetic tunnel junction memory layer are sequentially deposited on a bottom electrode of a peripheral circuit unit area of the magnetic random access memory by adopting the physical vapor deposition process, and a physical vapor deposition process is adopted to sequentially deposit the magnetic tunnel junction reference layer, the magnetic tunnel junction barrier layer, the magnetic tunnel junction memory layer and a hard mask layer on the bottom electrode of the magnetic tunnel junction area of the magnetic random access memory;
step eight: patterning of the magnetic tunnel junction and the pseudo magnetic tunnel junction is completed by adopting a photoetching process and an etching process.
2. The pseudomagnetic tunnel junction cell of claim 1 wherein the bottom electrode material is a single layer film of one of Ta, taN, taON, ti, tiN, tiON, ru, pt, coFeB or a plurality of layers of films having a thickness of 10 to 30nm.
3. The pseudomagnetic tunnel junction cell of claim 1 wherein the adhesion layer is of PMGI or LOR and has a thickness of 50-100nm and the photoresist layer has a thickness of 300-500nm.
4. The pseudomagnetic tunnel junction cell of claim 1 wherein in step five, either the SC-1 solution cleaning method or Cl is used 2 /Ar、SF 6 、CF 4 /CHF 3 、CF 4 /O 2 Or CF (compact flash) 4 /N 2 The bottom electrode of the peripheral circuit unit area is processed by plasma reaction etching method of the gas, so that the surface of the peripheral circuit unit area is roughened.
5. The pseudomagnetic tunnel junction cell of claim 1 wherein in step six a lift-off process is employed.
6. The pseudomagnetic tunnel junction cell of claim 1 wherein the pseudomagnetic tunnel junction reference layer has a [ Co/(Ni, pd, pt) ] n/Co/Ru/[ Co/(Ni, pd, pt) ] m/(Ta, W, mo, hf, coTa, feTa, taCoFeB)/CoFeB superlattice multilayer film structure where n > m, m is greater than or equal to 0 and the total thickness of the pseudomagnetic tunnel junction reference layer is 2-20 nm.
7. The pseudomagnetic tunnel junction cell of claim 1 wherein the pseudomagnetic tunnel junction barrier layer is a non-magnetic metal oxide having a thickness of 0.5nm to 3nm.
8. The pseudomagnetic tunnel junction cell of claim 1 wherein the pseudomagnetic tunnel junction memory layer is CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo, hf)/CoFeB, and has a thickness of 0.8nm to 2nm, and wherein a capping layer is deposited again after the pseudomagnetic tunnel junction memory layer is deposited.
9. The pseudomagnetic tunnel junction cell of claim 1 wherein the hard mask layer is Ta, taN or Ta/TaN having a thickness of 60 to 100nm.
10. The pseudomagnetic tunnel junction cell of claim 1 wherein the pseudomagnetic tunnel junction reference layer, the pseudomagnetic tunnel junction barrier layer, and the pseudomagnetic tunnel junction memory layer are formed of substantially the same material as the magnetic tunnel junction reference layer, the magnetic tunnel junction barrier layer, and the magnetic tunnel junction memory layer, and wherein the depositing is accomplished simultaneously in a physical vapor deposition process chamber, the pseudomagnetic tunnel junction having a resistance that is one tenth or less than the resistance of the magnetic tunnel junction.
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| US10069064B1 (en) * | 2017-07-18 | 2018-09-04 | Headway Technologies, Inc. | Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same |
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| US8138562B2 (en) * | 2009-10-20 | 2012-03-20 | Magic Technologies, Inc. | Bit line preparation method in MRAM fabrication |
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| US10014464B1 (en) * | 2017-03-01 | 2018-07-03 | International Business Machines Corporation | Combined CMP and RIE contact scheme for MRAM applications |
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- 2019-04-24 CN CN201910334319.0A patent/CN111863865B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1774816A (en) * | 2003-04-16 | 2006-05-17 | 飞思卡尔半导体公司 | Magnetoresistive random acess memory device structures and methods for fabricating the same |
| TW200713647A (en) * | 2005-07-29 | 2007-04-01 | Freescale Semiconductor Inc | Magnetic tunnel junction sensor |
| JP2007317734A (en) * | 2006-05-23 | 2007-12-06 | Sony Corp | Storage device and memory |
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