CN109873009B - MRAM chip using grounding dummy - Google Patents

Abstract

The invention discloses an MRAM chip using a grounding dummy, which comprises an MRAM chip body and the grounding dummy, wherein the grounding dummy comprises a dummy and a through hole, and the dummy is grounded through the through hole. At least two grounding dummy devices are arranged, and when a plurality of MRAM chips are arranged into an MRAM core array, the grounding dummy devices are inserted into gaps of the MRAM chip array at equal intervals. The MRAM chip disclosed by the invention improves the deposition etching effect of the dummy through the grounding dummy, so that the difference caused by the antenna effect is eliminated, and higher process quality and higher yield are obtained.

Description

MRAM chip using grounding dummy

Technical Field

The invention belongs to the field of semiconductor chip memories, and particularly relates to an MRAM chip using a grounding dummy.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration, and can be written repeatedly infinitely many times. MRAM can be read and written as fast as SRAM/DRAM, and also can permanently retain data after power down as Flash.

MRAM has good economy and performance, and its unit capacity occupies a larger silicon area than SRAM, and also has an advantage over NOR Flash, which is often used in such chips, that is greater than embedded NOR Flash. MRAM has close read-write delay to the best SRAM, and power consumption is best in various memories and storage technologies; moreover, the MRAM is compatible with the standard CMOS semiconductor process, and the DRAM and the Flash are not compatible with the standard CMOS semiconductor process; MRAM may also be integrated with logic circuitry into one chip.

MRAM is based on MTJ (magnetic tunnel junction) structures. Composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower ferromagnetic material is a reference layer with a fixed magnetization direction and the upper ferromagnetic material is a memory layer with a variable magnetization direction, the magnetization direction of which may be parallel or antiparallel to the fixed magnetization layer. Due to quantum-physical effects, current can pass through the intermediate tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has low resistance and the latter case has high resistance.

The process of reading MRAM is to measure the resistance of the MTJ. Writing MRAM uses newer STT-MRAM techniques for writing operations using stronger currents through the MTJ than reading. A bottom-up current places the variable magnetization layer in a parallel orientation with respect to the fixed layer and a top-down circuit places it in an anti-parallel orientation.

As shown in FIG. 2, each MRAM memory cell is comprised of an MTJ and an NMOS tube. The gate electrode (gate) of the NMOS tube is connected to the Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on the Bit Line of the chip. The read-write operation is performed on the Bit Line.

As shown in fig. 3, an MRAM chip is composed of one or more MRAM memory cell arrays, each array having several external circuits, such as:

● Row address decoder: selection of a received address to become Word Line

● Column address decoder: selection of a received address to be a Bit Line

● And a read-write controller: controlling read (measurement) write (current) operations on Bit Line

● Input and output control: and externally exchange data

The read-out circuitry of MRAM is required to detect the resistance of the MRAM memory cells. Since the resistance of an MTJ shifts with temperature, etc., it is a common approach to use some memory cells on a chip that have been written to a high resistance state or a low resistance state as reference cells. A Sense Amplifier (Sense Amplifier) is then used to compare the resistances of the memory cell and the reference cell.

In the CMOS semiconductor process, an NMOS tube is formed by injecting an N-type doped region into a P-type semiconductor substrate to form a source electrode and a drain electrode, and the middle of the NMOS tube is isolated by a gate electrode with an oxide bottom layer. The source electrode is connected to the source line, and the drain electrode is connected to the MTJ formed by etching through the via hole, as shown in fig. 4.

During operation of the chip, the P-type substrate is connected with the ground wire

The MTJ is formed by first depositing multiple layers of thin films and then etching. The etch process is most quality when producing periodic equally spaced patterns, but cells near the edge of an array often suffer from non-uniform quality issues. To cope with this problem, a number of layers of dummy cells are typically added around an MRAM array, as shown in fig. 5. However, in process practice, such dummy deposition etching is not effective, thereby affecting the quality of the memory cells near the edge. The reason for this is the "antenna effect", where cells with vias grounded inside the MRAM array, unlike the dangling dummy field distribution, affect the deposition etching process.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an MRAM chip using a grounded dummy, which can improve the deposition etching effect of the dummy and eliminate the difference caused by the antenna effect.

In order to achieve the above object, the present invention provides an MRAM chip using a ground dummy, the MRAM chip including an MRAM chip body and the ground dummy, the ground dummy including a dummy and a via through which the dummy is grounded.

Further, the dummy is connected to the substrate of the MRAM chip body through the via.

Further, the dummy is connected to a ground line through the via.

Further, the grounding dummy has at least two layers at the periphery of the MRAM array formed by the MRAM chip.

Further, when a plurality of the MRAM chips are arranged into an MRAM core array, the grounding dummy is inserted into the gaps of the MRAM chip array at equal intervals.

Further, when the inside of the MRAM array needs to have a void due to the layout, the ground dummy is inserted into the void inside the array at equal intervals.

The MRAM chip using the grounding dummy is grounded through the dummy, so that the deposition etching effect of the dummy is improved, the difference caused by the antenna effect is eliminated, and higher process quality and higher yield are obtained.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ.

FIG. 2 is a schematic diagram of a prior art MRAM memory cell architecture.

FIG. 3 is a prior art MRAM chip architecture diagram.

FIG. 4 is a schematic cross-sectional view of a prior art MRAM chip along a bit line.

FIG. 5 is a schematic cross-sectional view of a prior art MRAM chip with dummy bit lines

FIG. 6 is a schematic diagram of an MRAM chip structure using a ground dummy according to a preferred embodiment of the invention.

Detailed Description

The following detailed description of the preferred embodiments of the invention is provided to enable those skilled in the art to more readily understand the advantages and features of the invention and to make a clear and concise definition of the scope of the invention.

As shown in fig. 6, an MRAM chip using a ground dummy includes an MRAM chip body 1 and a ground dummy 2, the ground dummy 2 including a dummy 21 and a via 22, the dummy 21 being grounded through the via 22.

The dummy 21 is connected to the substrate of the MRAM chip body 2 through a via 22, realizing grounding; or the dummy 21 is connected to the ground 23 through a via 22, realizing a ground.

There are at least two ground dummy 2. When a plurality of MRAM chips are arranged in an MRAM core array, the ground dummy 2 is inserted into the MRAM chip array void at equal intervals. The ground dummy 2 has at least two layers at the periphery of the MRAM array in which the MRAM chips are arranged.

When the inside of the MRAM array needs to have a gap due to the layout, the grounding dummy is inserted into the gap inside the array at equal intervals.

The MRAM chip using the grounding dummy disclosed in the embodiment improves the deposition etching effect of the dummy through the grounding dummy, so as to eliminate the difference caused by the antenna effect and obtain higher process quality and higher yield. The method can be applied to the fields of the Internet of things, wearable electronic equipment and the like with strict requirements on standby power consumption.

The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention without requiring creative effort by one of ordinary skill in the art. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (4)

1. An MRAM chip using a ground dummy, the MRAM chip comprising an MRAM chip body and a ground dummy, characterized in that the ground dummy comprises a dummy and a via through which the dummy is grounded; wherein the dummy is connected to the substrate of the MRAM chip body through the via hole, and the dummy is connected to a ground line through the via hole.

2. The MRAM chip using a ground dummy according to claim 1, wherein the ground dummy has at least two layers at a periphery of an MRAM array in which the MRAM chip is arranged.

3. The MRAM chip using a ground dummy according to claim 1, wherein the ground dummy is inserted into the MRAM chip array void at equal intervals when a plurality of the MRAM chips are arranged in an MRAM core array.

4. The MRAM chip using a ground dummy according to claim 1, wherein the ground dummy is inserted equally spaced into the array internal void when the MRAM array internal void is needed due to a layout.