TW200410353A - Method for manufacturing and testing semiconductor component - Google Patents

Abstract

Disclosed is a method for manufacturing and testing a semiconductor component. The method is suitable for semiconductor component having asymmetrical distributed conductive contacts disposed thereon. The method includes the steps of forming at least one pseudo contact on the surface of the semiconductor component such that the at least one pseudo contact and the conductive contacts form a symmetric pattern on the surface of the semiconductor component, and moving a prober onto the semiconductor component such that a testing program can be conducted through the prober. Since the interconnect contacts of the prober are arranged corresponding to the symmetric pattern, the prober can apply a force on the semiconductor component uniformly during the testing process to avoid misreading or misjudging of the prober.

Description

200410353 五、發明說明（l) 【發明所屬之技術領域】 本發明係有關於一種半導體元件的製造以及測試方法。 【先前技術】 半導體元件的製造需要多個製程，包含設計、製造以及泪, 試。測試可分成功能性（functional )、參數性 (parametric )以及燒機（burn-in)的方法。在這些方法 a玄半導體元件可能以晶圓、晶片或封裝構造的型態測 試。 2 了執行針對半導體元件的測試過程，必須使用一個具 miinterc〇nnect c〇ntac"探測器之褒 於待測之半導體元件表面的接點（c〇ntacts) 的完ί這，暫時電性連接，目前已發展出多種 接點，為使迅速且有效率地執件都具g 以同時測試每车；#二二夕具有對應的多個連接接釜 」利式母—丰導體兀件上的多個接點。 ^而，根據不同的設計 ’ 上的多個接點經常呈現不斜同的需要，半導體元件表 測試步驟中造成一個難題。、毒^佈’這種不對稱的分佈 器的多個連接接點與半因^在測試步驟中，為確保探 測器的每一個連接接點會同二士點有良好的接觸， 壓力。此時是半導體丰子+導體兀件上之接點施加 體元件整體受力不平衡，上的接點分佈不對稱，則半 象’而使探測器的連接接點盘=導：元件產生傾斜的 __ 〃牛導體兀件上的接點接觸不 苐8頁 200410353 五、發明說明（2) 致’導致探測器誤載或誤判。 另外，由於半導體元件不同用途不同或是由不同設計製造 的廠商不同，所設計的半導體元件其接點位置亦的不相同， 因此探測器的連接接點也需要根據不同的待測半導體而做調 整。這不但大幅提高執行測試步驟時的設備成本，在測試不 同半導體元件之間還必須執行繁複的裝卸動作。 【發明内容】 本發明之目的係提供一種製造以及測試半導體元件的方 法，能克服前述在測試過程中，因半導體元件上之接點分佈 不對稱所造成的難題。 本發明之另一目的在於提供一種半導體元件之設計，該設 計使不 藉此測 節省測 為了 件，其 被設計 接點。 該半導 對於該 供一種 本發 供一具 器，其 同的半 試機台 試過程 達成上 表面上 為不對 該偽接 體元件半導體 製造該 明針對 有複數 連接接 導體元件 便可使用 的成本並 述及其他 與内部積 稱，其另 點與前述 表面的接 元件表面 具有偽接 上述之半 個連接接 點之配置 能具有通用且分佈對稱的接點圖 具有通用連接接點圖案的探測器 提高測試的效率。 之目的，本發明提供一種半導體 體電路電性連接的導電接點之分 具有不與内部積體電路電性連接 之導電接點形成一對稱的圖案， 點（包含導電接點以及偽接點） 之幾何中心成對稱分佈。本發明 點之半導體元件之方法。 導體元件提供一測試方法。首先 點（interconnect contact)之探 方式係對應於該導電接點以及該 案 以 佈係 的偽 使得 係相 亦提 ，提 測 偽接200410353 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing and testing a semiconductor device. [Prior art] The manufacturing of semiconductor devices requires multiple processes, including design, manufacturing, and testing. Testing can be divided into functional, parametric, and burn-in methods. In these methods, a semiconductor device may be tested in the form of a wafer, wafer, or package structure. 2 To perform the test process for semiconductor components, you must use a miinterc〇nnect c〇ntac " detector on the surface of the semiconductor component to be tested (c〇ntacts) to complete this, temporarily electrically connected, At present, a variety of contacts have been developed. In order to quickly and efficiently implement the g to test each car at the same time; # 二 二 夕 has a corresponding number of connection joints. Contacts. ^ However, according to different designs, multiple contacts often present different requirements, which causes a problem in the test step of the semiconductor component table. In the test step, in order to ensure that each of the connection points of the detector will have good contact with the pressure point and pressure. At this time, the overall force of the contact-applying body element on the semiconductor ferrite + conductor element is unbalanced, and the distribution of the contact points on the semiconductor element is not symmetrical. Then the image of the detector is connected to the contact plate = guide: the component is inclined __ The contact on the yak conductor element is not too much. Page 8 200410353 V. Description of the invention (2) Causes the detector to be misloaded or misjudged. In addition, because semiconductor devices have different uses or are manufactured by different designs and manufacturers, the contact positions of the designed semiconductor elements are also different. Therefore, the connection points of the detectors need to be adjusted according to different semiconductors to be tested. . This not only greatly increases the equipment cost when performing the test steps, but also has to perform complicated loading and unloading operations between different semiconductor components under test. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for manufacturing and testing a semiconductor device, which can overcome the aforementioned problems caused by the asymmetry of the contact distribution on the semiconductor device during the test. Another object of the present invention is to provide a design of a semiconductor device, which is designed so that the test can be performed without using the tester, and the contact is designed. The semiconducting device is provided with a device for the present invention, and the same semi-testing machine test process achieves the cost of using the semiconductor device without the dummy junction element semiconductor on the upper surface. It also refers to other and internal claims that the other point and the surface of the contact element have a pseudo connection to the above half of the connection. The configuration can have a universal and symmetrically distributed contact diagram. A detector with a universal connection contact pattern Improve test efficiency. The object of the present invention is to provide a conductive contact of a semiconductor body circuit that has a conductive pattern that does not electrically connect with the internal integrated circuit to form a symmetrical pattern. The points (including conductive contacts and dummy contacts) The geometric centers are distributed symmetrically. A method of a semiconductor device according to the present invention. The conductor element provides a test method. First of all, the detection method of the interconnect contact corresponds to the conductive contact and the case of the system, so that the system is also mentioned, and the false connection is detected.

200410353 五、發明說明（3) 圖f。在測試過程令，將該探測器移至該半 件的導電接％==每—探測器之連接接點接觸半導體元 ^ ^ h ^^或疋偽接點的其中之一，藉此使該探測器均勻 牛導體疋件上。然後，利用該偵測器對該半導俨 僂逆5盘^ ^ 式，在測試過程中，沒有任何測試訊號被 在傳送二接點接觸之連接接點。詳細言之，該測試程ί ^減戒號通過每一與導電接點接觸之連接接點的同 拉Y W不會將該測試訊號傳送至其他與該偽接點接觸之連接 接點。 $饮 本發明另提供一種製造以及測試半導體元件的方法。首 丄在具有不對稱分佈之導電接點的半導體元件之表面上形 ^稱/刀if的接點，其中每一接點係電性連接於該半導體元件 導電接點的其中之—。值得注意的是，該半導體元件 % f =對佈士導電接點係被重佈為具有對稱分_^1接 ::3後，針對該半導體元件重佈後之接點，•行與勢述 致相同之測試步驟。 為了讓本發明之上述和直他曰沾 士 顯，下文特舉本發明較佳實2的、特徵、和優點能更明 說明如下。 實軛例，並配合所附圖式，作詳細 【實施方式 第1圖所示為根據本發明一眚 實也例之半導體元件1〇〇，其表 面具有多個導電接點1 1 〇與多個後 110傲主道麟-n ηη如/ 偽接點120，該多個導電接點 ’、 70 °卩之積體電路電性連接，該多個偽接200410353 V. Description of the invention (3) Figure f. During the test process, move the detector to the conductive contact of the half.% == Each—the connection contact of the detector is in contact with one of the semiconductor elements ^ ^ h ^^ or a pseudo-contact. The detector is evenly distributed on the bull conductor. Then, using this detector, the semiconducting 俨 is reversed to 5 disks ^ ^. During the test, no test signal is transmitted at the connection contact of the second contact. In detail, the test process ^ minus ring number through the same pull Y W of each connection contact that is in contact with the conductive contact will not transmit the test signal to other connection contacts that are in contact with the pseudo contact. The present invention also provides a method for manufacturing and testing a semiconductor device. First, a contact is formed on the surface of a semiconductor device having asymmetrically distributed conductive contacts. Each of the contacts is electrically connected to one of the conductive contacts of the semiconductor device. It is worth noting that the semiconductor element% f = the conductive contacts are redistributed to have symmetrical points _ ^ 1 :: 3, after the semiconductor elements are redistributed, The same test procedure. In order to make the above and other aspects of the present invention obvious, the features, advantages, and advantages of the preferred embodiment 2 of the present invention are specifically described below. The actual yoke example is shown in detail in conjunction with the attached drawings. [Embodiment 1 shows a semiconductor device 100 according to a practical example of the present invention. The surface has a plurality of conductive contacts 1 1 0 and more. The rear 110 is proud of Dolin-n ηη such as / pseudo contact 120, the multiple conductive contacts', 70 ° 卩 integrated circuit is electrically connected, and the multiple pseudo contacts

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.= 20僅形成在該半導體元件1〇〇的表φ， 内：的積體電路電性連接。該半導體元件1〇。之導電接: —〇原本係没什為不對稱分佈。偽接點12〇的功能係使半導 :件1〇〇表面所有接點的分佈具有對稱性，藉此使測試過程 :的+導體兀件100能均勻受力。適用於本發明之半導體元 件可以是-半導體封裝構造，或是一突塊化或僅具有接㈣ 晶圓、晶片。 ‘ 第2a-2d圖係圖示根據本發明之一實施例製造一具有對稱 接點之半導體元件的主要步驟。參照第2a圖，首先，提供一 個裸晶片200，其表面具有複數個不對稱分佈的鋁接墊21〇以 及一保護層（passivation layer)22Q，該鋁接墊210與該裸 晶片2 0 0内部之積體電路（未示於圖中）電性連接，該保護層 (passivation layer) 22 0覆蓋該裸晶片20〇之表面，僅裸露 出該铭接墊2 1 0。下一步，參照第2b圖，於該鋁接墊21 〇上形 成一凸塊下金屬層230。更具體地說，該突塊下金屬包 含二層金屬’其分別為：（a)铭層230a，作為黏附層)鎳 /釩層2 3 0b，作為阻障層；以及（c)銅層230c，作為潤濕層。 參照第2c圖，在突塊下金屬層23 0上塗佈一光阻層2 40，並且 將該光阻層240圖案化，而在該突塊下金屬層230上形成複數 個對稱分佈的開孔區域2 5 0，該開孔屉域2 5 0係對應於預備形 成之導電突塊260以及偽突塊2 70 (參見第2e圖）的位置。將 銲錫電沉積（electrodeposition)於光阻層240的開孔區域 2 50，並同時形成導電突塊2 6 0 (位於鋁接墊210上方）以及偽 突塊27 0，之後將光阻去除而製得如第2d圖所示之裝置。最. = 20 is formed only on the table φ of the semiconductor device 100, where: the integrated circuit is electrically connected. This semiconductor element 10. The conductive connection:-〇 The original system is not even asymmetric distribution. The function of the pseudo contact 120 is to make the distribution of all the contacts on the surface of the semiconductor device 100 symmetrical, so that the + conductor element 100 of the test process can be uniformly stressed. The semiconductor device suitable for the present invention may be a semiconductor package structure, or it may be a bump or only have a wafer or a wafer. ‘Figures 2a-2d illustrate the main steps of manufacturing a semiconductor device with symmetrical contacts according to one embodiment of the present invention. Referring to FIG. 2a, first, a bare wafer 200 is provided, the surface of which has a plurality of asymmetrically distributed aluminum pads 21 and a passivation layer 22Q. The aluminum pads 210 and the bare wafer 200 are internal The integrated circuit (not shown in the figure) is electrically connected. The passivation layer 22 0 covers the surface of the bare chip 20. Only the inscribed pad 2 10 is exposed. Next, referring to FIG. 2b, an under bump metal layer 230 is formed on the aluminum pad 21o. More specifically, the metal under the bump includes two layers of metal, which are: (a) a layer 230a as an adhesion layer) a nickel / vanadium layer 2 3 0b as a barrier layer; and (c) a copper layer 230c , As a wetting layer. Referring to FIG. 2c, a photoresist layer 2 40 is coated on the metal layer 230 under the bump, and the photoresist layer 240 is patterned, and a plurality of symmetrically distributed openings are formed on the metal layer 230 under the bump. The hole area 250 is a position corresponding to the conductive bumps 260 and the dummy bumps 2 70 (see FIG. 2e) to be formed. Electrodeposition is performed on the opening area 2 50 of the photoresist layer 240, and a conductive bump 26 (located above the aluminum pad 210) and a dummy bump 27 0 are formed at the same time, and then the photoresist is removed to make it. The device shown in Figure 2d is obtained. most

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後 以‘電突塊2 6 0以及偽突地？ 7 η ^^ “ Ai, i*i ^ n , 属層23 0，缺後進塊2 70為遮敝，蝕刻该凸塊下金 信〜、、t立…、後進订回焊步驟而製得如第2e圖所示之裝置。 m :二忍2是，該導電突塊2 6 0以及偽突塊270係相對於第2e 回μ I^ ^置表面之幾何中心成對稱分佈（未示於圖中） 乂 η +疋提供一種於具有不對稱分佈鋁接墊的裸晶片2 0 0表 ”時形成對稱分佈之導電突塊以及偽突塊的方法，然而表聲 ^已形成導電突塊的半導體元件上另外形成偽突塊，使4 ‘體元件表面具有對稱分佈之突塊的方法，亦適 明。 本發月另k供一種藉由形成一重佈層（redistributi〇n 1 ayer+)來製造具有對稱接點之半導體元件的方法。該重佈層 具有複數個對稱分佈的接點，且每一接點係電性連接於該半 導體元件表面之導電接點的其中之一。該方法之步驟敘述如 下·參照第3 a圖，首先將一鈦層3 3 0 a濺鍍沉積在裸晶片3 〇 0 的表面上’此裸晶片300具有不對稱分怖之铭接塾31〇 (_有 一個鋁接墊3 10標示於第3a圖中）。在形成一金屬導電參 330b覆蓋該鈦層33 0a之後，選擇性蝕刻該鈦層3 30a與該金屬 導電層330b，以形成一多層引線330 (參見第3b圖）。該多 層引線330的一端部連接至鋁接墊31 〇，其另一端部則係延伸 於該保，護層3 20上。參照第3c圖，一介電層340 (較佳係以聚 醯亞胺（poly i mi de)製成）覆蓋於該多層引線33 0以及保護層 320上，並且於該介電層340上形成複數個對稱分佈的光界定 開孔（photo-defined via)340a，以暴露出該多層引線330遠 離鋁接墊310之端部。參照第3d圖，一導電銲墊（conductiveThen take ‘Electric Burst 2 60 and a pseudo-burst? 7 η ^^ "Ai, i * i ^ n, metal layer 23 0, after entering the block 2 70 as a mask, etching the gold letter under the bump ~,, t stand ... The device shown in Fig. 2e. M: Er Ni 2 is that the conductive bumps 2 60 and the pseudo bumps 270 are symmetrically distributed with respect to the geometric center of the surface of the 2e loop μ I ^ ^ (not shown in the figure). (Middle) 乂 η + 一种 provides a method for forming symmetrically distributed conductive bumps and pseudo bumps on a bare wafer with asymmetrically distributed aluminum pads. The method of forming pseudo bumps on the element to make the surface of the 4 'body element symmetrically distributed is also suitable. This article also provides a method for manufacturing a semiconductor device having symmetrical contacts by forming a redistributive layer (a layer +). The redistribution layer has a plurality of symmetrically distributed contacts, and each contact is electrically connected to one of the conductive contacts on the surface of the semiconductor element. The steps of the method are described as follows. Referring to FIG. 3a, first, a titanium layer 3 3 0 a is sputter-deposited on the surface of a bare wafer 300. 'This bare wafer 300 has an asymmetric distribution. 31' (There is an aluminum pad 3 10 marked in Figure 3a). After a metal conductive parameter 330b is formed to cover the titanium layer 330a, the titanium layer 330a and the metal conductive layer 330b are selectively etched to form a multilayer lead 330 (see FIG. 3b). One end portion of the multi-layered lead 330 is connected to the aluminum pad 31 0, and the other end portion thereof extends on the protection layer 3 20. Referring to FIG. 3c, a dielectric layer 340 (preferably made of polyimide) covers the multilayer leads 330 and the protective layer 320, and is formed on the dielectric layer 340. A plurality of symmetrically-distributed photo-defined vias 340a to expose the end of the multilayer lead 330 far from the aluminum pad 310. Referring to Figure 3d, a conductive pad

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pad)350覆蓋於該開孔340a。該導電銲墊35〇較佳包含_錄, 釩層35 0 a以及一銅層3 5 0 b，其中鎳/釩層35〇a形成於開孔 340a所界定之多層引線330上，並且該銅層35〇b係設於該鎳/ 釩層35 0a上。參照第3e圖，一銲錫凸塊36〇設於該銅層35〇b 上。該銲錫凸塊36 0亦可以一金凸塊取代。 根據上述的方法形成具有對稱接點之半導體元件之後，利 用一探測器測試該元件。該探測器具有複數個連接接點 (interconnect contact)4U)，該複數個連接接點41〇之配1 五、發明說明（6) 方式係對應於該導電突塊26 0以及偽突塊27〇所形成之對稱圖 案。該測試方法之步驟敘述如下：首先直接將該探測器4〇 〇 移至半導體元件2 0 0之上。接著，使每一連接接點4丨〇對半導 體元件20 0之導電突塊260以及偽突塊27〇的其中之一施加一 預先设定壓力，藉此讓連接接點41〇與半導體元件2〇〇之導電 突塊26 0以及偽突塊270有良好的暫時性連接。此時，由於導 電突塊260以及偽突塊27 0係成一對稱的分佈，因此測器 4〇〇經由芩接接點410對半導體元件2〇〇上的突塊26〇 ^7〇施 力時’該半導體元件200所受之應力係均勾分配於其表面。 因此，在測試的過程中，半導體元件2〇〇能保持平衡，不會 因受力不平均而歪斜。 由：偽f塊270並未與半導體元件2〇〇内部的積體電路連 接，因此右針對偽突塊2 7〇送出測試訊息時將不會得到回 成測試系統的誤判。因此本發明提供-種測 的元件m上的偽突塊270接觸之連接接點。詳A pad) 350 covers the opening 340a. The conductive pad 350 preferably includes a vanadium layer 35 0 a and a copper layer 3 5 0 b, wherein a nickel / vanadium layer 35 0a is formed on the multilayer lead 330 defined by the opening 340a, and the copper The layer 350b is provided on the nickel / vanadium layer 350a. Referring to FIG. 3e, a solder bump 36o is disposed on the copper layer 35ob. The solder bump 360 can also be replaced by a gold bump. After a semiconductor device having symmetrical contacts is formed according to the method described above, the device is tested with a detector. The detector has a plurality of interconnect contacts (4U). The plurality of interconnect contacts 41 are provided with one. 5. Description of the invention (6) The method corresponds to the conductive bumps 26 0 and the dummy bumps 27. The resulting symmetrical pattern. The steps of the test method are described as follows: First, the detector 400 is directly moved above the semiconductor device 2000. Next, each connection contact 4 is applied with a predetermined pressure to one of the conductive bump 260 and the dummy bump 27 of the semiconductor device 200, so that the connection contact 41 is connected to the semiconductor device 2 The conductive bump 260 and the dummy bump 270 of 〇〇 have good temporary connections. At this time, since the conductive bumps 260 and the dummy bumps 27 0 are symmetrically distributed, when the tester 400 applies a force to the bump 26 on the semiconductor element 200 via the contact point 410, 'The stresses on the semiconductor device 200 are all distributed on its surface. Therefore, during the test, the semiconductor device 200 can maintain balance without being distorted due to uneven force. The reason is that the dummy f-block 270 is not connected to the integrated circuit inside the semiconductor device 200, so when the test message is sent to the dummy bump 27, the right will not get a false judgment of the test system. Therefore, the present invention provides a connection contact of the pseudo bump 270 on the component m. detailed

第13頁 200410353Page 13 200410353

五、發明說明（7) ;ϊΐ藉2導，接觸之連接接點傳送一測試訊號給該 件的同日寺，不傳送^則試訊號至與該偽接點接觸之 運接接點。因此，可以正確地檢測判斷待測的半導體元件a 否具有正常之效能。 疋 另外，根據本發明所提供之方法，可將具有各種不同接墊 排列設計之的半導體元件加工成具有相同排列圖案之接點。 因此操/則器之連接接點可設計成通用的（u η丨V㊀^ & 1 )分佈圖 案藉此僅需選擇不同的測試程式加以檢測判斷，而不用針 對不同的半導體元件裝卸相對應之探測器。因此可大量節省 測試的成本以及時間。 雖然本發明已以前述較佳實施例揭示，然其並非用以限定 本發$，任何熟習此技藝者，在不脫離本發明之精神和範圍 内 §可作各種之更動與修改。因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。V. Description of the invention (7); By borrowing 2 leads, the contact point of contact sends a test signal to the same day temple of the piece. If it does not transmit ^, the trial signal is sent to the contact point in contact with the pseudo contact. Therefore, it is possible to correctly detect and determine whether the semiconductor element a to be tested has normal performance.疋 In addition, according to the method provided by the present invention, semiconductor elements having various pad arrangement designs can be processed into contacts having the same arrangement pattern. Therefore, the connection points of the actuator can be designed into a universal (u η 丨 V㊀ ^ & 1) distribution pattern so that only different test programs need to be selected for detection and judgment, instead of corresponding to different semiconductor component loading and unloading. detector. As a result, significant cost and time savings can be achieved. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

200410353 圖式簡單說明 【圖式簡 第1圖 第 2a-2 造一突塊 第 3a-3 製造一突 第4圖 暫時性電 單說明】 :根據本發明一實施例之半導體元件之上視圖； e圖：以剖視圖圖示根據本發明一實施例之方法製 化晶片的主要驟， e圖：以剖視圖圖示根據本發明另一實施例之方法 塊化晶片的主要步驟，以及 :根據本發明之一實施例，檢測器與待測晶片形成 性連接之剖面圖。200410353 Schematic description [Schematic diagram 1 Figure 2a-2 Making a bump 3a-3 Making a bump 4 Figure Temporary electricity bill description]: A top view of a semiconductor device according to an embodiment of the present invention; FIG. e: a cross-sectional view illustrating the main steps of forming a wafer according to a method of an embodiment of the present invention, e-graph: a cross-sectional view illustrating the main steps of forming a wafer by a method according to another embodiment of the present invention, and: In one embodiment, a cross-sectional view of the detector is formally connected to the wafer to be tested.

圖號說 明： 100 半 導 體 元 件 110 導 電 接 點 120 偽 接 點 200 裸 晶 片 210 鋁 接 墊 220 保 護 層 230 凸 塊 下 金 屬層 230a IS 層 23 0 b 鎳 /飢層 230c 銅 層 240 光 阻 層 250 開 孔 區 域 260 導 電 突 塊 270 偽 突 塊 300 裸 晶 片 310 鋁 接 墊 320 保 護 層 330a 鈦 層 330 b 金 屬 導 電 層 330 多 層 引 線 340 介 電 層 340a 開 孔 350 導 電 銲 墊 35 0a 鎳 /飢層 35 0 b 銅 層 360 銲 錫 凸 塊 400 探 測 器 410 連 接 接 點 第15頁Description of drawing number: 100 semiconductor element 110 conductive contact 120 dummy contact 200 bare wafer 210 aluminum pad 220 protective layer 230 under bump metal layer 230a IS layer 23 0 b nickel / starved layer 230c copper layer 240 photoresist layer 250 open Hole area 260 Conductive bump 270 Pseudo bump 300 Bare wafer 310 Aluminum pad 320 Protective layer 330a Titanium layer 330 b Metal conductive layer 330 Multi-layer lead 340 Dielectric layer 340a Opening hole 350 Conductive pad 35 0a Nickel / Hunger layer 35 0 b Copper layer 360 solder bump 400 detector 410 connection contact page 15

Claims (1)

200410353 六、申請專利範圍 1、一種用以製造以及測試一半導體元件之方法，其中該 導體元件具有積體電路以及複數個導電接點（c〇nductiv二 con tact)與該積體電路電性連接，其中該複數個導電接點（ 設計為不對稱地分佈於該半導體元件之表面上，該方法包= 下列步驟： 3 形成至少一偽接點（PSeU(J〇 C〇ntact)於該半導體元件之 表面上，使得該偽接點與該複數個導電接點於該半導體元件 之表面上形成一對稱圖案； “七、诛’則器其具有複數個連接接點（i n t e r c ο η n e c t contact)以對應於該對稱圖案之方式配置； 接點 >移動該採測器於該半導體元件上，使得每一連接接點接觸 該偽接點與該複數個導電接點的其中之一，藉此在偵測過程 中a亥探測器係均勻地施力於該半導體元件上；以及 ^經由該偵測器對該半導體元件執行一測試程式，其中在測 试過程中沒有任何測試訊號被傳送至與該偽接點接稼艺連接 2、依申請專利範圍第丨項之用以製造以及測試一半導體元件 之方法，其中該半導體元件係為 曰曰 圓 3、 依申請專利範圍第i項之用以製造以及測試—半導體元件 之方法，其中該半導體元件係為一晶片。 4、 依申請專利範圍第1項之用以製造以及測試一半導體元件200410353 VI. Application Patent Scope 1. A method for manufacturing and testing a semiconductor element, wherein the conductor element has an integrated circuit and a plurality of conductive contacts (conductiv 2 con tact) are electrically connected to the integrated circuit , Wherein the plurality of conductive contacts (designed to be distributed asymmetrically on the surface of the semiconductor device, the method package = the following steps: 3 forming at least one dummy contact (PSeU (Jocontact) on the semiconductor device) On the surface, so that the dummy contact and the plurality of conductive contacts form a symmetrical pattern on the surface of the semiconductor element; "Seven, 诛" has a plurality of connection contacts (interc ο η nect contact) to Configuration corresponding to the symmetrical pattern; Contacts> Move the detector on the semiconductor element so that each connection contact contacts one of the dummy contact and the plurality of conductive contacts, thereby During the detection process, the ai detector is uniformly applied to the semiconductor element; and ^ a test program is executed on the semiconductor element through the detector, where the test During the process, no test signal is transmitted to the connection with the dummy contact. 2. The method for manufacturing and testing a semiconductor device according to item 丨 of the patent application scope, wherein the semiconductor device is a circle 3, A method for manufacturing and testing a semiconductor device according to item i of the scope of patent application, wherein the semiconductor device is a wafer. 4. A method for manufacturing and testing a semiconductor device according to item 1 of the scope of patent application H1 200410353 六、申請專利範圍 之方法，其中該半導體元件係為一半導體封裝構造 5 '依申請專利範圍第2、3或4項之用以製造以及測試一半導 體π件之方法，其中該半導體元件之導電接點係為一 $ 墊（pad)。 我 6、依申請專利範圍第2、3或4項之用以製造以及測試—半立 體π件之方法，其中該偽接點係形成為一偽接墊。 L •依申專利範圍第2、3或4項之用以製造以及測試一丰_ f元件之方法，其中該半導體元件之導電接點係為一 塊（bump)。 免’ 8、 依申請專利範圍第2、3或4項之用以製造以及測試— 體疋件之方法，其中該偽接點係形成為一偽突塊。 1 9、 依申請專利範圍第丨項之用以製造以及測試一半^元々 之方法’其中該偽接點的形成步驟包含下列步驟·· v成凸塊下金屬層（under bump metallurgy，簡猶hrm 於該半導體元件之表面上；以及 間稱_ 形成至少一偽突塊於該凸塊下金屬層上。 ^體元SIS製造以及測試一半導體元件之方法，其中該斗 導體凡件具有積體電路以及複數個導電接點（ — tiveH1 200410353 VI. Method of applying for a patent, wherein the semiconductor element is a semiconductor package structure 5 ′ The method for manufacturing and testing a semiconductor π part according to item 2, 3, or 4 of the scope of patent application, wherein the semiconductor element The conductive contact is a $ pad. I 6. The method for manufacturing and testing a half-cube π part according to item 2, 3 or 4 of the scope of patent application, wherein the dummy contact is formed as a dummy contact pad. L • The method for manufacturing and testing a Fonf device according to item 2, 3 or 4 of the scope of the applied patent, wherein the conductive contact of the semiconductor device is a bump. Exemption '8. The method for manufacturing and testing a body part according to item 2, 3 or 4 of the scope of the patent application, wherein the dummy contact is formed as a dummy bump. 1 9. The method for manufacturing and testing half of the yuan according to item 丨 of the scope of the patent application, wherein the step of forming the dummy contact includes the following steps: v forming an under bump metallurgy (Janu hrm) On the surface of the semiconductor element; and at least one dummy bump is formed on the metal layer under the bump. ^ The method of manufacturing and testing a semiconductor element by the voxel SIS, wherein the bucket conductor has an integrated circuit And multiple conductive contacts (— tive 200410353 六、申請專利範圍 contact)與該積體電路電性連接，其中該複數個導電接點係 不對稱地分佈於該半導體元件之表面上，該方法包含下列步 於族半導體元件之表面上形成一其上具有複數個對稱地分 佈的接點之重佈層（redistribution layer)，其中每一接點 係電性連接於該半導體元件表面之導電接點的其中之一； 提供一探測器，其具有複數個連接接點（interc〇nnec|; contact)，對應於該重佈層之接點之方式配置； 移動該探測器於該半導體元件上，使得每一連接接點接觸 戎重佈層之接點的其中之一，藉此在偵測過程中該探測器係 均勻地施力於該半導體元件上；以及 經由該債測器對該半導體元件執行一測試程式。 11、依申請專利範圍第10項之用以製造以及測試一半導體元 件之方法’其中該半導體元件係為一晶圓。 以製造以及測試一半導體元 12、依申請專利範圍第1 〇項之用以製 件之方法，其中該半導體元件係為— β製造以及測試一半導體元 為一半導體封裝構造。 1 3、依申請專利範圍第1 〇項之用以 件之方法，其中該半導體元件係為200410353 VI. Patent application scope contact) is electrically connected to the integrated circuit, wherein the plurality of conductive contacts are distributed asymmetrically on the surface of the semiconductor element, the method includes the following steps to form on the surface of a family of semiconductor elements A redistribution layer having a plurality of symmetrically distributed contacts thereon, wherein each contact is one of the conductive contacts electrically connected to the surface of the semiconductor element; a detector is provided; There are a plurality of connection contacts (interc〇nnec |; contact), which are arranged in a manner corresponding to the contacts of the redistribution layer; the detector is moved on the semiconductor element so that each connection contact contacts the redistribution layer One of the contacts, whereby the detector exerts uniform force on the semiconductor element during the detection process; and executes a test program on the semiconductor element through the debt detector. 11. The method for manufacturing and testing a semiconductor device according to item 10 of the scope of patent application, wherein the semiconductor device is a wafer. A method for manufacturing and testing a semiconductor element 12. The method for manufacturing a component according to item 10 of the patent application scope, wherein the semiconductor element is-β manufactured and tested for a semiconductor element as a semiconductor package structure. 1 3. According to the method of applying for item 10 in the scope of patent application, wherein the semiconductor element is 以製造以及測試一 導電接點係為一導Guided by manufacturing and testing a conductive contact system 200410353 六、申請專利範圍 電接墊（pad)。 1 5、依申請專利範圍第n、丨2或丨3項之用以製造以及測試一 半導體元件之方法，其中該半導體元件之導電接點係為一導 電突塊（bump)。200410353 VI. Scope of Patent Application Electric pad. 15. The method for manufacturing and testing a semiconductor device according to item n, 丨 2 or 丨 3 of the scope of patent application, wherein the conductive contact of the semiconductor device is a conductive bump. 1 6、一種用以測試一半導體元件之方法，其中該半導體元件 具有積體電路以及複數個導電接點（c〇ncjuctive contact) 與至少一個偽接點（pseu(j0 contact)於該半導體元件之表面 上’其中只有該導電接點與該積體電路電性連接，其中該複 數個導電接點與該偽接點係形成一對稱圖案，該方法包含下 列步驟： 提供一探測器，其具有複數個連接接點（interc〇nnect contact)以對應於該對稱圖案之方式配置； 移動該探測器於該半導體元件上，使得每一連接接觸 該偽接點與導電接點的其中之一，藉此在偵測過程&探測 器係均勻地施力於該半導體元件上；以及 經由該偵測器對該半導體元件執行一測試程式，其中在測16. A method for testing a semiconductor device, wherein the semiconductor device has an integrated circuit and a plurality of conductive contacts (c0ncjuctive contact) and at least one pseudo contact (pseu (j0 contact) on the semiconductor device) On the surface, only the conductive contact is electrically connected to the integrated circuit, and the plurality of conductive contacts and the dummy contact form a symmetrical pattern. The method includes the following steps: providing a detector having a plurality of Interc0nnect contacts are arranged in a manner corresponding to the symmetrical pattern; the detector is moved on the semiconductor element so that each connection contacts one of the dummy contact and the conductive contact, thereby During the detection process & the detector is uniformly applied to the semiconductor element; and a test program is executed on the semiconductor element via the detector, wherein 試過程中沒有任何測試訊號被傳送至與該偽接點接觸之連接 接點。 17' —種半導體元件，其包含： 積體電路； 複數個導電接點（conduct ive contact)不對稱地分佈於該During the test, no test signal is transmitted to the connection contact that is in contact with the pseudo contact. 17 '—A semiconductor device comprising: an integrated circuit; a plurality of conductive contacts are distributed asymmetrically thereon 第19頁 200410353 六、申請專利範圍 半導體元件之表面上；以及 至少一個偽接點（pseudo contact) 設於該半導體元件之 表面上，使得該導電接點與該偽接點係於該半導體元件之表 面上形成一對稱圖案， 其中只有該導電接點與該積體電路電性連接。 18、依申請專利範圍第17項之半導體元件，其中該半導體元 件係為一晶圓。Page 19 200410353 VI. Patent application scope on the surface of the semiconductor element; and at least one pseudo contact is provided on the surface of the semiconductor element, so that the conductive contact and the pseudo contact are connected to the semiconductor element A symmetrical pattern is formed on the surface, wherein only the conductive contact is electrically connected to the integrated circuit. 18. The semiconductor device according to item 17 of the scope of patent application, wherein the semiconductor device is a wafer. 1 9、依申請專利範圍第1 7項之半導體元件，其中該半導體元 件係為一晶片。 2 0、依申請專利範圍第1 7項之半導體元件，其中該半導體元 件係為一半導體封裝構造。 2 1、依申請專利範圍第1 8、1 9或2 0項之半導體元件，/其中該 導電接點係為一導電接墊（pad)。19. The semiconductor device according to item 17 of the scope of patent application, wherein the semiconductor device is a wafer. 20. The semiconductor device according to item 17 of the scope of patent application, wherein the semiconductor device is a semiconductor package structure. 21 1. The semiconductor device according to item 18, 19, or 20 of the scope of the applied patent, wherein the conductive contact is a conductive pad. 22、依申請專利範圍第18、19或20項之半導體元件，其中該 偽接點係形成為一偽接墊。 2 3、依申請專利範圍第1 8、1 9或2 0項之半導體元件，其中該 導電接點係為一導電突塊（bump)。22. The semiconductor device according to claim 18, 19, or 20, wherein the dummy contact is formed as a dummy pad. 2 3. The semiconductor device according to item 18, 19, or 20 of the scope of patent application, wherein the conductive contact is a conductive bump. 第20頁 200410353 六、申請專利範圍 2 4、依申請專利範圍第1 8、1 9或2 0項之半導體元件，其中該 偽接點係形成為一偽突塊。 2 5、依申請專利範圍第2 4項之半導體元件，另包含： 複數個與該積體電路電性連接並且分佈不對稱的接合接墊 (bonding pad);以及 一保護層（passivation layer)覆蓋該半導體元件除了該 接合接墊之外的整個表面， 其中該導電接點係一導電突塊，其係形成於該接合接墊 上，以及該偽突塊係形成於該保護層上。 26、依申請專利範圍第25項之半導體元件，另包含一凸塊下 金屬層（under bump metallurgy，簡稱UBM)設於該導電突塊 與該接合接墊之間，以及設於該偽突塊與該保護層之間。Page 20 200410353 VI. Scope of patent application 24. According to the semiconductor device according to item 18, 19 or 20 of the scope of patent application, the dummy contact is formed as a dummy bump. 25. The semiconductor device according to item 24 of the scope of patent application, further comprising: a plurality of asymmetric bonding pads electrically connected to the integrated circuit and distributed asymmetrically; and a passivation layer covering The entire surface of the semiconductor device except the bonding pad, wherein the conductive contact is a conductive bump formed on the bonding pad, and the dummy bump is formed on the protective layer. 26. The semiconductor device according to item 25 of the patent application scope, further comprising an under bump metallurgy (UBM) disposed between the conductive bump and the bonding pad, and disposed on the dummy bump. And the protective layer. 第21頁Page 21