CN110494964B - Semiconductor packages with exposed redistribution layer features and related packaging and testing methods - Google Patents

Semiconductor packages with exposed redistribution layer features and related packaging and testing methods Download PDF

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Publication number
CN110494964B
CN110494964B CN201880022899.3A CN201880022899A CN110494964B CN 110494964 B CN110494964 B CN 110494964B CN 201880022899 A CN201880022899 A CN 201880022899A CN 110494964 B CN110494964 B CN 110494964B
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redistribution
package
semiconductor device
bond pad
layer
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CN110494964A (en
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M·拉姆
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Microchip Technology Inc
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Microchip Technology Inc
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Abstract

The present disclosure provides a method of packaging a semiconductor device having a bond pad (120) on a surface thereof, the method comprising: forming a redistribution material (140) electrically coupled to the bond pads; forming a dielectric material (150) over the redistributed material; and removing the first portion of the dielectric material to expose the first portion of the redistributed material. The semiconductor package may include a redistribution layer having: a first portion adjacent to and coupled to a first contact (170) of the package; a second portion (152) exposed by the first opening in the dielectric material (150); and a redistribution line (140) electrically coupled to the first bond pad (120), the first portion, and the second portion. Such packages may be tested, at least one probe needle placed in contact with at least one terminal of the package, a test signal from the probe needle provided to the package through the terminal, and the signal detected using the needle.

Description

Semiconductor packages with exposed redistribution layer features and related packaging and testing methods
Priority statement
This patent application claims the benefit of the filing date of U.S. provisional patent application Ser. No. 62/483,253"A SEMICONDUCTOR PACKAGE HAVING EXPOSED REDISTRIBUTION LAYER FEATURES AND RELATED METHODS OF PACKAGING AND TESTING," filed on 7, 4, 7.
Technical Field
The present disclosure relates generally to semiconductor packages and methods of packaging and testing semiconductor packages. Some specifically disclosed embodiments relate to Wafer Level Chip Scale Packages (WLCSPs) having one or more exposed portions of a redistribution layer in a final package configuration and methods of packaging and testing such wafer level chip scale packages.
Background
During the packaging process, which includes high temperature process steps, electronic components and circuits in the semiconductor device may be damaged or their characteristics may be altered. Techniques such as wafer probing may be utilized to test semiconductor devices and detect damage and/or variations to the characteristics of electronic components and/or circuits. If damage or a change is detected, then a mitigation step may sometimes be performed.
Fig. 1A and 1B illustrate techniques known in the art. Fig. 1A is a cross-sectional view of a semiconductor package 10 having a packaged redistribution layer 30. The semiconductor package 10 includes a semiconductor device 11 having a passivation layer 12 and at least one bond pad 13 thereon. Semiconductor package 10 further includes a dielectric layer 14, a redistribution layer 15, a dielectric layer 16, an adhesive layer 160 (e.g., a solderable adhesion metal layer), and package contacts 17. The redistribution layer 30 is only accessible from the outside through the package contacts 17. As non-limiting examples, the package contacts may be solder balls, solder bumps, copper pillar bumps, or a combination thereof.
Fig. 1B is a plan view of the semiconductor package 10 shown in fig. 1A. The redistribution layer 30 of the semiconductor package 10 is only accessible from the outside through the package contacts 17.
There is a need for semiconductor packages and packaging techniques that facilitate testing and mitigate defects in a cost-effective manner. Other drawbacks and disadvantages may exist in the prior art.
Drawings
Fig. 1A is a schematic cross-sectional view of a portion of a semiconductor package having a packaged redistribution layer, the diagram representing techniques known in the art.
Fig. 1B is a schematic isometric view of a semiconductor package with a packaged redistribution layer, which represents a technique known in the art.
Fig. 2A is a schematic cross-sectional view of a portion of a semiconductor package having at least one exposed portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 2B is a schematic isometric view of a semiconductor package having at least one exposed redistribution layer according to an embodiment of the present disclosure.
Fig. 3 is a flow chart of actions in a process for packaging a semiconductor device having at least one exposed portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 4A through 4E are schematic cross-sectional views of portions of a semiconductor device undergoing a packaging process exposing at least a portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 5A-5E are schematic plan views of a semiconductor device undergoing a packaging process exposing at least a portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of a portion of a semiconductor package having at least one exposed portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 7 is a flow chart of actions in a process for packaging a semiconductor device having at least one exposed portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 8A-8D are schematic cross-sectional views of a portion of a semiconductor device undergoing a packaging process exposing at least a portion of a redistribution layer, according to an embodiment of the present disclosure.
Fig. 9A-9D are schematic plan views of a semiconductor device undergoing a packaging process exposing at least a portion of a redistribution layer according to an embodiment of the present disclosure.
Fig. 10 is a flow chart of actions in a process for testing a semiconductor package having an exposed portion of a redistribution layer according to an embodiment of the present disclosure.
Detailed Description
The illustrations presented herein are not intended to be actual views of any particular act in a method of making a semiconductor device, an intermediate product of such a method, a semiconductor device, or components thereof, but are merely idealized representations that are employed to describe the exemplary embodiments of the present disclosure. Accordingly, the drawings are not necessarily drawn to scale.
The disclosed embodiments relate generally to semiconductor packages and methods of packaging and testing semiconductor packages. Some specifically disclosed embodiments relate to semiconductor packages that may include one or more exposed portions of a redistribution layer. The exposed portion of the redistribution layer may include one or more terminals (among other purposes) that are electrically conductive and accessible to make electrical contact with probes of the test apparatus. As described further below, referring to fig. 5A-5E and 9A-9D, the redistribution layer may include more than one terminal; indeed, the redistribution areas of the one or more redistribution layers may each include one or more terminals.
Various embodiments of the present disclosure relate to semiconductor devices that include circuitry that is "embedded" or "integrated" in the silicon or semiconductor material of the device. Sometimes these are also referred to as semiconductor chips. Examples of circuitry include, but are not limited to, integrated Circuits (ICs), application Specific Integrated Circuits (ASICs), microprocessors, memory devices, and combinations thereof.
The semiconductor device may be part of a "component" or "package" that protects the circuitry of the semiconductor device, dissipates heat, and holds external electrical contacts (e.g., bumps, pins, and/or leads) for electrically and physically coupling the semiconductor device to external circuitry.
Techniques for packaging include, but are not limited to, wire bonding, tape automated bonding, and flip chip. One such packaging technique is "chip scale packaging" in which the semiconductor package has the same or nearly the same form factor as the semiconductor device. Conventionally, chip scale packaging includes any packaging process that results in a package to die ratio of less than or equal to 1.2:1. When such semiconductor devices are packaged while they remain part of a larger wafer that includes a plurality of such devices, these packages are commonly referred to as Wafer Level Chip Scale Packages (WLCSP).
Fig. 2A is a cross-sectional view of a semiconductor package 100 having at least one exposed redistribution layer 140 according to an embodiment of the present disclosure. Semiconductor package 100 includes semiconductor device 110, dielectric layer 130, redistribution layer 140, dielectric layer 150, and adhesive layer 160, and package contacts 170. At least one bond pad 120 and passivation layer 114 are formed on a top surface of the semiconductor device 110.
Fig. 2B is an isometric view of a semiconductor package 100 having at least one exposed portion of a redistribution layer 140 according to an embodiment of the present disclosure. The exposed redistribution layer 140 includes terminals 141 and 145 that are conductive and accessible to probes of the test device—other terminals shown in fig. 2B are also conductive and physically accessible, but are not specifically mentioned for simplicity of discussion.
Fig. 3 is a flow chart of actions in a process for packaging a semiconductor device having at least one exposed redistribution layer according to an embodiment of the present disclosure.
Fig. 4A-4E illustrate cross-sectional views of a packaging process of a semiconductor package 100 that exposes one or more portions of a redistribution layer 140 of the semiconductor package 100, according to an embodiment of the present disclosure.
Referring to fig. 4A, a semiconductor die 110 is shown having a bottom surface 111 that is approximately planar and a top surface 112 that is approximately planar opposite the bottom surface 111. The semiconductor die 110 has at least one bond pad 120 formed on the top surface 112. The semiconductor die 110 has a passivation layer 114 (e.g., a nitride such as silicon nitride) formed on the top surface 112 with a suitable thickness such that the bond pads 120 are open, i.e., such that the passivation layer 114 covers the top surface 112 but does not cover some or all of the bond pads 120.
Referring to fig. 4B, a first dielectric layer 130 having a suitable thickness is shown formed on the passivation layer 114. The first dielectric layer 130 may cover the entire passivation layer 114 and be formed with an opening 131 such that the bonding pad 120 is exposed. As a non-limiting example, a suitable thickness of the first dielectric layer 130 may vary between 3 μm and 20 μm (inclusive).
In one embodiment, the opening 131 is formed by a photolithographic process that includes applying a photoresist material to the dielectric layer 130, masking the photoresist layer according to a predetermined pattern, exposing the masked photoresist layer, developing the photoresist layer and etching a portion of the first dielectric layer 130 to form the opening 131 and expose the bond pad 120, stripping any remaining photoresist material, and curing the dielectric material. Those of ordinary skill in the art will appreciate that variations of the lithographic process exist or are possible and may be used.
As non-limiting examples, the dielectric material may be polyimide, benzocyclobutane, polybenzoxazole, bismaleimide triazine, phenolic resin, epoxy resin, silicone resin, oxide layer, nitride layer, and the like. In one embodiment, curing of the polyimide dielectric material is performed for up to 90 minutes at one or more curing stages of 100 to 400 degrees celsius (inclusive) until the desired hardness is reached. The curing conditions may be selected according to the material selected for use as the dielectric material.
In another embodiment, the dielectric material of the first dielectric layer 130 is composed of a photodefinable polymer (e.g., a positive polyimide, a negative polyimide, or a negative polyimide). The openings 131 are formed by applying a photodefinable polymer onto the passivation layer 114, semi-curing the material, masking the semi-cured dielectric layer 130, exposing the masked first dielectric layer 130, developing the first dielectric layer 130 to form the openings 131 and exposing the bond pads 120, and finally curing the photodefinable polymer to form the first dielectric layer 130 by spin coating, applicator roll, or similar process.
Referring to fig. 4C, a redistribution layer 140 having a suitable thickness is shown formed on the first dielectric layer 130. As a non-limiting example, suitable thicknesses of the redistribution layer 140 may vary between 1 μm and 20 μm (inclusive).
In one embodiment, the redistribution layer 140 may be formed by a sputter deposition process on the first dielectric layer 130 and the exposed bond pad 120. In other embodiments, other deposition processes may be utilized, such as sputtering followed by electroplating. The area of the redistribution layer 140 is formed to have a predefined length (cross-sectional view) and a predefined area (plan view). A portion of the redistribution layer is positioned adjacent (e.g., under) the package contacts 170 to electrically and physically couple the bond pads 120 to the package contacts 170. The redistribution layer 140 is further formed to include terminals 141. In this embodiment, terminal 141 is repositioned away from and electrically coupled to bond pad 120 and package contact 170; however, as will be explained in more detail with reference to fig. 5A to 5D, the position of the terminal 141 is a design consideration. As a non-limiting example, the terminals may be organized around the perimeter of the surface of the semiconductor package; terminals are combined together in the form of diagonal lines, circles, etc. on the center of the surface of the semiconductor package, on the side walls of the semiconductor package.
In one embodiment, the redistribution layer 140 includes a sputtered titanium adhesion layer, a sputtered copper conductive layer, and a plated copper. The redistribution layer 140 may be made of other materials that are suitably conductive and suitably adhere to the polymers of the first dielectric layer 130 and the dielectric layer 150 (see fig. 2A). As non-limiting examples, the redistribution layer 140 may include one or more layers or alloys of any of titanium, chromium, aluminum, copper, nickel, tungsten, cobalt, and combinations thereof.
Referring to fig. 4D, a second dielectric layer 150 having a suitable thickness is shown formed on the redistribution layer 140 and the first dielectric layer 130. As a non-limiting example, a suitable thickness of the second dielectric layer 150 may vary between 3 μm and 20 μm (inclusive).
The second dielectric layer 150 is formed with openings 151 (such that at least a portion of the redistribution layer 140 is exposed to the area where the package contacts will be located) and openings 152 (such that at least a portion of the redistribution layer is exposed to the area over the terminals 141). In one embodiment, openings 151 and 152 are formed by one of the substantially identical processes described herein for forming openings 131 (see fig. 4B) in dielectric layer 130.
As non-limiting examples, the dielectric material of the second dielectric layer 150 may be polyimide, benzocyclobutane, polybenzoxazole, bismaleimide triazine, phenolic resin, epoxy resin, siloxane, oxide layer, nitride layer, and the like. As another non-limiting example, the dielectric material of the second dielectric layer 150 may also be a photodefinable polymer.
Referring to fig. 4E, an adhesive layer 160 and package contacts 170 (solder balls in this embodiment) are shown that span the opening 151 and are formed on the redistribution layer 140 and are conductively coupled to the redistribution layer. By way of non-limiting example, suitable thicknesses of the adhesive layer 160 may vary between 1 μm and 20 μm (inclusive).
The adhesive layer 160 may partially cover the second dielectric layer 150. In one embodiment, the adhesive layer 160 may be formed on the redistribution layer 140 through the openings 151 by a sputter deposition process. In other embodiments, other deposition processes may be utilized, such as evaporation, sputtering, followed by electroplating or evaporation, followed by electroplating. In one embodiment, the adhesive layer 160 is a solderable adhesion metal layer and includes a sputtered titanium adhesion layer, a sputtered copper conductive layer, and plated copper.
The adhesive layer 160 may be made of other materials that are suitably electrically conductive and suitably adhere to the redistribution layer 140 and the package contacts 170 and allow the package contacts 170 to be suitably reflowed. As non-limiting examples, the adhesive layer 160 may include one or more layers or alloys of any of titanium, chromium, aluminum, copper, nickel, tungsten, cobalt, and combinations thereof. In one embodiment, the adhesive layer 160 is an Under Bump Metallization (UBM) layer or stack.
Package contacts 170 are formed on and adhered to adhesive layer 160. In one embodiment, the package contacts 170 may be lead-free alloy solder balls comprising tin, alloys of tin, silver, copper, cobalt, bismuth zinc, and any combination thereof, as non-limiting examples.
Although the adhesive layer 160 is shown and described in connection with the embodiment shown in fig. 4E, it is specifically contemplated that in another embodiment the adhesive layer 160 is partially or completely omitted from the structure. In such embodiments, package contacts 170 (e.g., solder balls) are formed on one or more portions of redistribution layer 140 and are electrically and physically coupled to redistribution layer 140.
Still referring to fig. 4E, the semiconductor package 100 includes an opening 152 over the terminal 141. Openings 152 and terminals 141 provide conductive access to bond pads 120 and enable testing and reprogramming of semiconductor electronic devices (wafer level integrated circuits including WLSCP) in semiconductor device 110.
The high temperature of the polymer used to cure dielectric layer 130 and dielectric layer 150 may cause semiconductor package 100 to operate outside of specifications. In the specific case of WLSCP, high temperatures can cause charge loss in the integrated circuit, resulting in program boundaries moving out of specification. Testing and repair may be performed at various steps in the packaging process. Testing and repair are preferably performed after all high temperature processing steps in the encapsulation process (e.g., after curing the dielectric layer). Testing WLCSP of the semiconductor package type shown in fig. 1A and 1B is challenging and expensive. Some bond pads on a semiconductor device are dedicated to testing and must be run before the package layer makes them inaccessible. However, the programming boundary offset of the base circuit should be readjusted after all high temperature process steps that may affect the charging characteristics.
As will be described with reference to fig. 5A-5E, testing and reprogramming of the semiconductor package 100 shown in fig. 2A and 2B is facilitated by openings 151 that allow conductive access to test bond pads (for testing circuits) and functional bond pads (for interacting with and reprogramming circuits).
Fig. 5A-5E illustrate plan views of the encapsulation process shown in fig. 4A-4E of the semiconductor package 100 exposing at least a portion of the redistribution layer 140 of the semiconductor package 100, according to embodiments of the present disclosure.
Referring to fig. 5A, a plan view of semiconductor die 110 and top surface 112 is shown. Also shown is bond pad 120, which in this embodiment includes test bond pads 121 and 122, and functional bond pads 123, 124, 125 and 126. The location and number of bond pads 120 is a design consideration and may vary based on the size of the semiconductor die, the electronics in the die, the standards that the final semiconductor package will follow, the shape, fit, functional requirements of the final semiconductor package, and combinations thereof.
Referring to fig. 5B, a plan view of a partially assembled semiconductor package 100 according to an embodiment of the present disclosure is shown, and more particularly, dielectric layer 130 and bond pad 120 are shown. Each of the test bond pads 121 and 122 and the functional bond pads 123, 124, 125 and 126 are exposed due to the openings formed in the dielectric layer 130. In this embodiment, all of the bond pads on semiconductor die 110 are exposed after formation of dielectric layer 130, however, in other embodiments, it is specifically contemplated that some of bond pads 120 may be covered by dielectric layer 130. As a non-limiting example, the bond pads 120 that are not relevant to the testing or functional operation of the semiconductor package 100 may be covered by a dielectric layer 130.
Referring to fig. 5C, a plan view of a partially assembled semiconductor package 100 according to an embodiment of the present disclosure is shown, and more particularly, the redistribution layer 140 is shown. In this embodiment, the redistribution layer 140 includes six conductive redistribution areas, but for simplicity of this discussion, only the redistribution areas 143 and 146 are referred to in fig. 5C. The redistribution area 143 includes a redistribution line 142 and a terminal 141. Redistribution lines 142 electrically and physically couple the functional bond pads 124 to the areas where external package contacts will be located (see fig. 2A) and terminals 141. The redistribution area 146 includes a redistribution line 144 and a terminal 145. Redistribution line 144 electrically and physically couples test bond pad 121 to terminal 145.
Referring to fig. 5D, a plan view of a partially assembled semiconductor package 100 according to an embodiment of the present disclosure is shown, and more particularly, dielectric layer 150 is shown, along with rerouted test bond pads and rerouted functional bond pads. For the rerouted bond pads of the redistribution areas 143 and 146 (and similarly for the other redistribution areas), the terminals 141 and 145, respectively, are exposed due to openings 151 formed in the dielectric layer 150. The portion of the redistribution line 142 in which the package contact 170 (see fig. 2A) is to be positioned is also exposed due to the opening 152 formed in the dielectric layer 150.
Referring to fig. 5E, a plan view of a partially assembled semiconductor package 100 according to an embodiment of the present disclosure is shown, and more particularly, the adhesive layer 160 is shown. Four UBMs with package contacts are shown, but only UBM 161 with package contacts 170 positioned thereon is mentioned. The terminals of the rewiring bond pads 120 are exposed and these terminals and bond pads 120 are electrically and physically accessible independently of the package contacts.
In the embodiment shown in fig. 5E, the surfaces of terminals 141 and 145 are physically and electrically exposed, however, in alternative embodiments, terminals 141 and 145 may be coated with another material that is suitably electrically conductive. Such a material may protect terminals 141 and 145 from contaminants during packaging and other processes. In one embodiment, the process for applying the adhesive layer 160 may include applying the adhesive layer to the terminals of the redistribution areas.
In another embodiment, a metal filler may be deposited on the exposed terminals in the gap formed by the opening 151 of the dielectric layer 150. A predetermined amount of metal filler may be deposited, or the metal filler may be deposited to a level below or above the top surface of the dielectric layer 150. In one embodiment, the top surface of the metal filler is approximately flush with the top surface of the dielectric layer 150.
Fig. 6 illustrates a cross-sectional view of a semiconductor package 200 in accordance with an embodiment of the present disclosure, wherein a redistribution layer 240 is formed on the passivation layer 214 without a dielectric layer between the passivation layer and the redistribution layer.
Fig. 7 illustrates a flow chart of actions in a process for packaging a semiconductor package 200 having at least one exposed redistribution layer, according to an embodiment of the present disclosure.
Fig. 8A-8D illustrate cross-sectional views of a process for packaging a semiconductor package 200 exposing at least one redistribution layer 240 of the semiconductor package 200 according to another embodiment of the present disclosure.
Referring to fig. 8A, a semiconductor die 210 is shown having a bottom surface 211 that is approximately planar and a top surface 212 that is approximately planar opposite the bottom surface 211. The semiconductor die 210 has at least one bond pad 220 formed on the top surface 212. The semiconductor die 210 has a passivation layer 214 (e.g., nitride or silicon nitride) formed on the top surface 212 with a suitable thickness such that the bond pads 220 are open, i.e., such that the passivation layer 214 covers the top surface 212 but does not cover some or all of the bond pads 220.
Referring to fig. 8B, a redistribution layer 240 having a suitable thickness is shown formed on the passivation layer 214. As a non-limiting example, suitable thicknesses of the redistribution layer 240 may vary between 1 μm and 20 μm (inclusive).
In one embodiment, the redistribution layer 240 may be formed by a sputter deposition process on the passivation layer 214 and the exposed bond pad 220. In other embodiments, other deposition processes may be utilized, such as sputtering followed by electroplating. The area of the redistribution layer 240 is formed to have a predefined length (cross-sectional view) and a predefined area (plan view). A portion of the redistribution layer 240 is positioned adjacent to the package contacts 270 to directly electrically and physically couple the bond pads 220 to the package contacts 270. The redistribution layer 240 is further formed to include terminals 241. In this embodiment, terminal 241 is repositioned away from and electrically coupled to bond pad 220 and package contact 270; however, as will be explained in more detail with reference to fig. 9A to 9D, the position of the terminal 241 is a design consideration. As a non-limiting example, terminals may be organized around the perimeter of the surface of the semiconductor package; terminals are combined together in the form of diagonal lines, circles, etc. on the center of the surface of the semiconductor package, on the side walls of the semiconductor package.
In one embodiment, the redistribution layer 240 includes a sputtered titanium adhesion layer, a sputtered copper conductive layer, and a plated copper. The redistribution layer 240 may be made of other materials that are suitably conductive and suitably adhere to the polymer of the dielectric layer 250 (see fig. 6) and the passivation layer 214. As non-limiting examples, the redistribution layer 240 may include one or more layers or alloys of any of titanium, chromium, aluminum, copper, nickel, tungsten, cobalt, and combinations thereof.
Referring to fig. 8C, a dielectric layer 250 of suitable thickness is shown formed over the redistribution layer 240 and the passivation layer 214. As a non-limiting example, suitable thicknesses of the dielectric layer 250 may vary between 1 μm and 20 μm (inclusive).
The dielectric layer 250 is formed with openings 251 (such that at least a portion of the redistribution layer 240 is exposed to the area where the package contacts will be located) and openings 252 (to expose the terminals 241).
In various embodiments, openings 251 and 252 are formed by a photolithographic process that includes applying a photoresist material to dielectric layer 250, masking the photoresist layer according to a predetermined pattern, exposing the masked photoresist layer, developing the photoresist layer and etching portions of dielectric layer 250 to form openings 251 and 252 and expose portions of redistribution layer 240 in which terminals 241 and package contacts will be located, stripping any remaining photoresist material, and curing the dielectric material. Those of ordinary skill in the art will appreciate that variations of the lithographic process exist or are possible and may be used.
As non-limiting examples, the dielectric material may be polyimide, benzocyclobutane, polybenzoxazole, bismaleimide triazine, phenolic resin, epoxy resin, silicone resin, oxide layer, nitride layer, and the like. In one embodiment, curing is performed for up to 90 minutes at one or more curing stages of 100 to 400 degrees celsius (inclusive) until the desired hardness is reached.
In another embodiment, the dielectric material of the dielectric layer 250 is comprised of a photodefinable polymer (e.g., a positive polyimide, a negative polyimide, or a negative polyimide). The openings 231 and 232 are formed by applying a photodefinable polyimide onto the redistribution layer 240 by spin coating, a coating roller, or similar process, semi-curing the material, masking the dielectric layer 250, exposing the masked dielectric layer 250, developing the dielectric layer 250 to form the openings 251 and 252 and exposing portions of the redistribution layer 240 adjacent to which the terminals 241 and package contacts will be located, and finally curing the photodefinable polyimide to form the dielectric layer 250.
Referring to fig. 8D, an adhesive layer 260 and package contacts 270 are shown that are formed across opening 251 and are electrically and physically coupled to redistribution layer 240. By way of non-limiting example, a suitable thickness of adhesive layer 260 may vary between 1 μm and 20 μm (inclusive).
Adhesive layer 260 may partially cover dielectric layer 250. In one embodiment, adhesive layer 260 may be formed on redistribution layer 240 through openings 251 by a sputter deposition process. In other embodiments, other deposition processes may be utilized, such as evaporation, sputtering, followed by electroplating or evaporation, followed by electroplating. In one embodiment, adhesive layer 260 is a solderable adhesion metal layer and includes a sputtered titanium adhesion layer, a sputtered copper conductive layer, and plated copper.
Adhesive layer 260 may be made of other materials that are suitably electrically conductive and suitably adhere to redistribution layer 240 and package contacts 270 and allow package contacts 270 to be suitably reflowed. As non-limiting examples, the adhesive layer 260 may include one or more layers or alloys of any of titanium, chromium, aluminum, copper, nickel, tungsten, cobalt, and combinations thereof. In one embodiment, the solderable adhesion metal layer is an Under Bump Metal (UBM) layer or stack.
Package contacts 270 are formed on and adhered to adhesive layer 260. In one embodiment, the package contact 270 may be a lead-free alloy solder ball comprising tin, an alloy of tin, silver, copper, cobalt, bismuth zinc, and any combination thereof, as non-limiting examples.
Although adhesive layer 260 is shown and described in connection with the embodiment shown in fig. 8D, it is specifically contemplated that in another embodiment adhesive layer 260 is partially or completely omitted from the structure. In such embodiments, package contacts 270 are formed on one or more portions of redistribution layer 240 and are electrically and physically coupled to redistribution layer 140.
Still referring to fig. 8D, the semiconductor package 200 includes an opening 252 over the terminal 241. Openings 252 and terminals 241 provide conductive access to bond pads 220 and enable testing and reprogramming of semiconductor electronic devices (wafer level integrated circuits including WLSCP) in semiconductor die 210.
As will become apparent with reference to fig. 9A-9D, testing and reprogramming of the semiconductor package 200 shown in fig. 6 is facilitated by openings 251 that allow conductive access to test bond pads (for testing circuits) and functional bond pads (e.g., for interacting with and reprogramming circuits).
Fig. 9A-9D illustrate plan views of the encapsulation process shown in fig. 8A-8D of the semiconductor package 200 exposing at least a portion of the redistribution layer 240 of the semiconductor package 200, according to embodiments of the present disclosure.
Referring to fig. 9A, a plan view of a semiconductor die 210 and a top surface 212 is shown. Also shown is bond pad 220, which in this embodiment includes test bond pads 221 and 222, and functional bond pads 223, 224, 225, and 226. The location and number of bond pads 220 is a design consideration and may vary based on the size of the semiconductor die, the electronics in the die, the standards that the final semiconductor package will follow, the shape, fit, functional requirements of the final semiconductor package, and combinations thereof.
Referring to fig. 9B, a plan view of a partially assembled semiconductor package 200 according to an embodiment of the present disclosure is shown, and more particularly, a redistribution layer 240 is shown. In this embodiment, the redistribution layer 240 includes six redistribution areas, but for simplicity of this discussion, only the redistribution areas 243 and 246 are referred to in fig. 9B. The redistribution area 243 includes a redistribution line 242 and a terminal 241. Redistribution lines 242 electrically and physically couple the functional bond pads 224 to the portion of the redistribution area (see fig. 6) and terminals 241 adjacent which the package contacts are to be located. The redistribution area 246 includes a redistribution line 244 and a terminal 245. Redistribution line 244 electrically and physically couples test bond pad 221 to terminal 245.
Referring to fig. 9C, a plan view of a partially assembled semiconductor package 200 is shown, and more particularly dielectric layer 250, as well as rerouted test bond pads and rerouted functional bond pads, in accordance with an embodiment of the present disclosure. For the rerouted bond pads of the redistribution areas 243 and 246 (and similarly for the other redistribution areas), the terminals 241 and 245 are exposed due to the openings 251 formed in the dielectric layer 250, respectively. The portion of the redistribution line 242 to which the package contact 270 (see fig. 6) will adhere is also exposed by the opening 252 formed in the dielectric layer 250.
Referring to fig. 9D, a plan view of a partially assembled semiconductor package 200 according to an embodiment of the present disclosure is shown, and more particularly, adhesive layer 260 is shown. Four UBMs with package contacts are shown, but only UBM 261 with package contacts 270 positioned thereon is mentioned. The terminals of the rewiring bond pads 220 are exposed and these terminals and bond pads 220 are electrically and physically accessible independently of the package contacts.
In this embodiment, the surfaces of terminals 241 and 245 are directly exposed, however, in alternative embodiments, terminals 241 and 245 may be coated with another material that is suitably electrically conductive. Such a material may protect terminals 241 and 245 from contaminants during packaging and other processes. In one embodiment, the process for applying adhesive layer 260 may include applying adhesive layer 260 to the terminals of the redistribution areas.
In another embodiment, a metal filler may be deposited on the exposed terminals in the gap formed by the opening 251 of the dielectric layer 250. A predetermined amount of metal filler may be deposited, or the metal filler may be deposited to a level below or above the top surface of the dielectric layer 250. In one embodiment, the top surface of the metal filler is approximately flush with the top surface of the dielectric layer 250.
Fig. 10 illustrates a test process 40 of a semiconductor package (such as semiconductor package 100 and semiconductor package 200) or a partially assembled variation according to an exemplary embodiment of the present disclosure.
A semiconductor package having an exposed redistribution layer is provided in operation S41. In this embodiment, the semiconductor package is a partial package such as that shown in fig. 4D, 5D, 8C, and 9C, but the semiconductor package may also be a fully assembled semiconductor package. Preferably, the stage of testing the package may be consistent with completing all high temperature process steps. Reference numerals of the partial packages shown in fig. 4D and 5D will be used to simplify the description.
In operation S42, a wafer prober (not shown) is connected with the semiconductor package. The wafer prober pins may be positioned in conductive contact with one or more of the exposed terminals 141 and 145 of the semiconductor package.
In operation S43, an electrical test of the semiconductor package is performed by the wafer prober. The electrical testing may include testing a base circuit of the semiconductor device by generating a test voltage at one or more of the exposed terminals 141 and 144 and reading the voltage at one or more of the terminals 141 and 144.
In operation S44, a charge loss and/or a program boundary offset (or loss) according to specifications is detected. If a program boundary shift is detected, the base circuit may be reprogrammed in operation S45.
While various embodiments of the present disclosure have been described with respect to certain layers, the scope of the present disclosure should not be so limited. It is specifically contemplated that additional layers may be included in the encapsulation package. As a non-limiting example, an adhesion layer may be included between the redistribution layer and the dielectric layer to couple the metal of the redistribution layer to the polymer of the dielectric layer.
Furthermore, it is specifically contemplated that more than one redistribution layer may be formed during the encapsulation process. For example, a redistribution layer may be added to facilitate conduction through the package for the ground and power planes. These redistribution layers may or may not include exposed terminals (such as in the case of redistribution layer 140).
Finally, while various embodiments of the present disclosure are described in terms of layers having a "thickness," and the figures may appear to exhibit a consistent thickness, it is specifically contemplated that the thickness of the layers may be varied by way of non-limiting example to accommodate the desired characteristics of the final package. Such as signal characteristics, heat, structural strength, etc. Furthermore, the thickness may vary only due to imperfections in the application process.
Although acts performed in a particular order are recited by or in connection with each of the operations illustrated in fig. 1A-10 and the accompanying text, embodiments of the disclosure do not necessarily operate in the order recited. Those of ordinary skill in the art will recognize many variations, including performing the actions in parallel or in a different order.
Additional non-limiting exemplary embodiments of the present disclosure are set forth below.
Embodiment 1: a method of packaging a semiconductor device having at least one bond pad on a surface of the semiconductor device, the method comprising: forming a redistribution material electrically coupled to the at least one bond pad; forming a dielectric material on a side of the redistribution material opposite the at least one bond pad; and removing the first portion of the dielectric material to expose the first portion of the redistributed material.
Embodiment 2: the method of embodiment 1, further comprising removing a second portion of the dielectric material to expose a second portion of the redistributed material.
Embodiment 3: the method of embodiment 2, further comprising forming an adhesive material on the second portion of the redistribution material.
Embodiment 4: the method of embodiment 3, wherein the adhesive material is a weldable adhesive.
Embodiment 5: the method of embodiment 4, further comprising providing encapsulated contacts on the adhesive material.
Embodiment 6: the method of any of embodiments 2-5, further comprising providing package contacts on the second portion of the redistribution material.
Embodiment 7: the method of embodiment 5 or embodiment 6, wherein the first portion of the redistribution layer remains exposed after the package contacts are provided.
Embodiment 8: a redistribution layer, the redistribution layer comprising: a first portion formed adjacent to and electrically coupled to a first contact of the semiconductor package; a second portion exposed by the first opening in the dielectric material; and a redistribution line electrically coupled to the first bond pad, the first portion, and the second portion.
Embodiment 9: the redistribution layer of embodiment 8, wherein the second portion is electrically and physically accessible via the first opening in the dielectric material.
Embodiment 10: the redistribution layer of embodiment 8, further comprising a third portion exposed by the second opening in the dielectric material.
Embodiment 11: the redistribution layer of embodiment 10, wherein the third portion is electrically coupled to the second bond pad.
Embodiment 12: the redistribution layer of embodiment 11 wherein the first bond pad is for input/output with a semiconductor device and the second bond pad is for testing the semiconductor device.
Embodiment 13: a semiconductor package comprising the redistribution layer according to any one of embodiments 8 to 13.
Embodiment 14: a semiconductor package, the semiconductor package comprising: one or more electrically and physically accessible terminals; and one or more contacts at a surface of the semiconductor package.
Embodiment 15: a method of testing a semiconductor package, the method comprising: placing at least one probe pin in electrical and physical contact with at least one terminal of the semiconductor package; providing one or more test electrical signals from the at least one probe pin to the semiconductor package through the at least one terminal; and detecting a signal indicative of a charge loss or a programming boundary shift.
Embodiment 16: the method of embodiment 15, further comprising reprogramming circuitry of the semiconductor package in response to the detected signal.
Embodiment 17: the method of embodiment 16, wherein reprogramming the circuitry of the semiconductor package includes using at least one package contact.
Embodiment 18: the method of embodiment 17, wherein the at least one package contact is remote from the at least one terminal.
While certain exemplary embodiments have been described in connection with the accompanying drawings, those of ordinary skill in the art will recognize and appreciate that the scope of the present disclosure is not limited to those embodiments explicitly shown and described in the present disclosure. Rather, many additions, deletions, and modifications to the embodiments described in the present disclosure may be made to produce embodiments within the scope of the present disclosure, such as those specifically claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure as contemplated by the inventors.

Claims (12)

1. A method of packaging a semiconductor device having at least one test bond pad and at least one functional bond pad on a surface of the semiconductor device, wherein the at least one test bond pad is configured to be capable of testing the semiconductor device and the at least one functional bond pad is configured to be capable of reprogramming circuitry of the semiconductor device, among other functions, the method comprising:
forming a first redistribution material electrically coupled to the at least one functional bond pad;
forming a second redistribution material electrically coupled to the at least one test bond pad;
forming a dielectric material on first corresponding sides of the first and second redistribution materials, the first sides of the first and second redistribution materials being opposite second corresponding sides of the first and second redistribution materials adjacent the at least one functional bond pad and the at least one test bond pad;
removing a first portion of the dielectric material to expose a first portion of the first redistribution material;
removing a second portion of the dielectric material to expose a second portion of the first redistribution material; and
a third portion of the dielectric material is removed to expose a first portion of the second redistributed material.
2. The method of claim 1, further comprising forming an adhesive material on the second portion of the first redistribution material.
3. The method of claim 2, wherein the adhesive material is a weldable adhesive.
4. The method of claim 3, further comprising providing package contacts on the adhesive material.
5. The method of any of claims 2-4, further comprising providing package contacts on the second portion of the first redistribution material.
6. The method of claim 5, wherein the first portion of the first redistribution material remains exposed after providing the package contacts.
7. The method of any of claims 2-4, further comprising testing the semiconductor device after removing the first portion of the dielectric material and after removing the third portion of the dielectric material, the testing comprising:
placing at least one probe needle in electrical and physical contact with the first portion of the second redistributed material;
providing one or more test electrical signals from the at least one probe needle to the semiconductor device through the first portion of the second redistribution material; and
a signal indicative of a charge loss or a programming boundary shift is detected.
8. The method of claim 7, further comprising reprogramming circuitry of the semiconductor device in response to the detected signal.
9. The method of claim 8, wherein reprogramming circuitry of the semiconductor device comprises using at least one package contact.
10. The method of claim 9, wherein the at least one package contact is remote from the first portion of the redistribution material.
11. The method of any of claims 1-4, wherein the packaged semiconductor device is a wafer level chip scale package.
12. A method of correcting program margin offset at a semiconductor package comprising a semiconductor device having at least one test bond pad and at least one functional bond pad, the at least one functional bond pad electrically coupled to a package contact, the method comprising:
providing one or more test signals to a first portion of the exposed first redistribution material, the first redistribution material being electrically coupled to the at least one test bond pad of the semiconductor device;
detecting a signal indicative of a charge loss or a programming boundary shift; and
reprogramming circuitry of the semiconductor device in response to the detected signal by providing a reprogramming signal to an exposed second redistribution material, the second redistribution material being electrically coupled to the at least one functional bond pad of the semiconductor device.
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