TW200304702A - Transistor arrangement with a structure for making electrical contact with electrodes of a trench transistor cell - Google Patents
Transistor arrangement with a structure for making electrical contact with electrodes of a trench transistor cell Download PDFInfo
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- TW200304702A TW200304702A TW092102939A TW92102939A TW200304702A TW 200304702 A TW200304702 A TW 200304702A TW 092102939 A TW092102939 A TW 092102939A TW 92102939 A TW92102939 A TW 92102939A TW 200304702 A TW200304702 A TW 200304702A
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Description
200304702 五、發明說明(l) 發明之領域 槽中之=月:二於 丹化电日日體胞兀電極之電接觸結構。 ;仏/丹 如M0S功率電晶體的電晶體排列,係藉由 衣置用於控制高電流強度(上至十安培)之 :控制電壓之 的負載電路中電晶體排列的介電強度可達數U,在轉換 晶體排列之轉換次數通常係於數微秒之間。百揭特’且該電 目河M〇S功率電晶體係如溝槽M0S功率電晶體。 率電晶體一般包含一半導體 且 —溝槽M0S功 一個排列於至少一活性胞二=個溝槽電晶體 第二圖中所示’正常關^通道溝 :別習知的溝槽電晶體胞元3。在此 率電晶體1之 =汲極區223係形成於該半導體基質中。再—者重n;雜(n++- ς成23。配置一較弱的n摻雜漂移區224,其係自—蟲晶在^及所極 ^ 〇 fΓη++ # ^ ^ ^ 區形成該溝槽電晶體皰元3 : 厂$運區203且該n++摻擴散| 擴散區中,其溝槽壁^3著之=極區213 °提供-溝槽9於該 内部與周圍的半導體基質6電::化物1 4,其可將該溝槽的 成閘極電極1 0之導體多晶矽充填。、此外,该溝槽9係以形 在該溝槽9之上,閘極今厘' 金屬化係於該基質表面7上緊鄰閘極電 Μ 第6頁 200304702 五、發明說明(2) 極1 0之邊緣區。在該基質表面7進行源極金屬化2丨,且與該 源極區2/1 3與通道區2 0 3電性連接。該源極金屬化2丨與該閘極 金屬化係藉由一中間氧化物層與彼此電性絕緣且與該半導體 基質6電性絕緣。與該半導體基質6上該基質表面7對面之基 質後側8上’有一汲極金屬化22緊鄰該半導體基質6之該汲極 區 2 2 3。
在無電壓狀態,該導體源極區213係藉由該p_摻雜通道 區203與該汲極區223電性絕緣。若該閘極電極1〇係正電位偏 壓,則^邛分載體,此範例為電子,係累積於該通道區2 〇 3 中’ 接相鄰於該閘極氧化物丨4。當該閘極電極丨〇之正偏壓 上升時,一η-傳導通道5形成原始?_傳導通道區2〇3 (反轉)。 當該源極區與該汲極區間的電流強度增加時,該半導體 本體的溫度增加且該通道區中電荷載體的移動降低。此效應 係指,槽電晶體胞元可用簡單的方式並聯電連接。此範例… 中,若在活化態中,初始較高的電流流經並聯電連接的溝样 電晶體胞7〇之一,則在此溝槽電晶體胞元中的溫度較高。^ 度增加的原因,該通道中電荷載體移動降低,且該溝槽: 體胞凡因而需要較高的阻抗。因此,該電流係分佈於: 的並聯溝槽電晶體胞元之間。 Λ m /皿 在溝槽M0S電力電晶體的半導體基質中,一般溝槽 體胞兀係沿著一延伸溝槽,或係以多邊形的溝槽而定義。曰曰 上所述之方式中,可能複數個溝槽之配置係彼此相接,以 成一活化的胞元陣列,溝槽旁的該閘極電極亦可經由橋 ‘
200304702 五、發明說明(3) 槽彼此連接 藉由一溝槽M0S電力電晶體轉換之最 並聯相連之該溝槽電晶體胞元的汲極〜阿電^強度,係由 定。最小的轉換時間與最大的運作頻Λ、$電阻(RPS⑽〉)所決| (RG)、閘極電荷QG與電容(Ciss)之閘極係數入電阻 該輸入電阻基本上係由該溝槽中該n疋。 定至小範圍,藉由該溝槽M0S電力電晶髀f 。一^極之電阻所決 溝槽中之該閘S電極間的連接線之電曰曰阻。今一閘極么端與該 ^曾加該閘極-源極電容(CGS)與該閘極—汲極;容(電二:: 如第一圖中所不之溝槽電晶體胞元之配置, 極1 0與該汲極終端之該漂移區224之間且 ^閘極電 ::漂移區224與該,㈣極10係對立於該氧二由4 在Turkes等人提出的肋98/〇29 25專利說明書中, 一M0S電力電晶體’其具有閘極電極配置於該基質表面上,路 其中該轉換次數與轉換降低係藉由減少閘極—汲 達到。在此範例中,電傳導連接至該咖電力電 源極終端之場電極,係配置於該閘極電極旁。該場電極庇 該自該漂移區閘極電極之電荷,且降低該閘極電極與該 之漂移區的區域。
降低該閘極-源極電容Cgd的另一觀念,係如美國專利 5, 283’ 201 (Tsang等人)中所揭示。在此範例中,在溝栌電曰 體胞元中,其電導體基質中具有閘極電極配置於一溝^中BB 第8頁 200304702
輔助電極係配置於該閘極電極之 以該閘極電極材質所製之 下,且係與後者絕緣。 源極:;c而言,=M〇S電力電晶體係強調要更降低該閘極― 】,:::’以改善功能且增加M0S電力電晶體的應用範 圍 例如用於更高的運作頻率。 構可:U!!之目的係提供一電晶體配置,其具有-結 胞元:二;固;ί:曰胃胞70之一溝槽中所酉己置的-溝槽電晶體 配置,;ϊΐ二 電性接觸,其中相較於習知的電晶體 " ^電日日體配置之閘極-汲極電容C彳έ ^ _ 可保‘留其功能。 不冤合CGD係較低的,且同時 根據本發明申請專利範 到此一目的。而根據本發明K1 專員之電晶體配置可達 晶體配置之其他優點。 π專利乾圍之依附項,可得電 根據本發明之電晶體配置形式,其 至少一閘極終端,一源極終端與—二山 至少-活化的胞元陣列於一半導體二終鈿, 一邊緣區域緊鄰該活化的胞元陣列:貝中, =、-溝槽於該活化的胞元陣列之 至y —溝槽電晶體胞元、;儿 X + ν體基貝中, 至少兩電極基質,其係^ 溝槽, 槽延伸,以及 ^ '…置於该溝槽内,且沿著該溝 至 該 至 溝槽係自該邊緣區心:肢基冑 , 4花出,以及 >'一電極基質係電性 導連接至該邊緣區域中金屬化
200304702 五、發明說明(5) 之一 根據本發明之此一電晶體配置形 胞元之溝槽中至少兩緊鄰或上下相鄰之f溝槽電晶體 體配置之終端金屬化,其優點在於節省空至該電 便。因此’可保持該電晶體配置 ::上的方 功能。 J内谷(晶片區域)之 根據本發明之該電晶體配置較 獅s電力電晶體。在此範例中,係配2具有~電極之-溝 並聯電連接至個別胞元陣列。在置 價甲母乾例之場電極係配置於 匕兀之屏 該溝槽M〇S電力電曰_ | h ^ s 電極之侧或之下。 端,以及一間極金曰曰Λ連Vy原極 =屬化連接至該源極終 電傳導連接至該較上之電極 二终端,該閘極金屬化係 本發明之每一 ^ t 構(閘極電極)。 式與配置以二t低y金屬化與閑極電極間之電連接方 可大幅改善該;=== 場電極)與場金屬化之間, 方式與配置。 土貝之基貝表面上源極與閘極金屬化的 因此,該源極会屬& 4 列之上,且至少产切而ά ^至乂部分配置於該活化的胞元陣 因此,首間r屬化環繞。 有非常低的阻抗…凡陣列中之源極區的接觸連接具 數微米厚度之源及金屬化該源極金屬化的圖案化。具有 的’因為例如再渴式餘刻^案化對於生產技術而言是複雜 該源極金屬化厚度之程度過程中,該源極金屬化被切除至
200304702 五、發明說明(6) 例如在上下相鄰之閘極或揚Φ 4 電性連接ΐ藉由同的方式電應之金屬t間的 C1 ^ ^ ^例如藉由在該溝槽中所個 別梃供之自該金屬化至该電極結構平面穿孔之裝置。此配置 之優點料該溝槽與平面穿孔之大小使得該平面穿孔可 地相對於該溝槽而定位。 另車父佳的方式中,β閘極結構與該閘極電極胞還相同 的材質,且在製造技術上有相同的處理步驟。在此範例中, =極電極之材:沉積之後’在該材質被回蝕至少在該該 之抗則要…閑極電極,需要該問極結構 辨ί另—有利的方式中’根據本發明之溝槽M0S電力電商 U有一場=於該基質表面之上,其分給該場電極盘 段:段地延伸’例如在該溝槽之上該邊緣區域中屬且具;: 面牙孔,其係直接電傳導連接該閘極金屬 =電極。此可在該問極電極之該沉積的材質=二亥 肩除閘極結構之光罩。 再者,該場電極之沉積材質所製之該 可於單-可控制之回蝕步驟中實行。 僧中的场包極 而後,首先自該場多晶矽出現之該場結構係 ?该場多晶矽被回蝕。未被覆蓋之場氧化物,苗;、番而 二ί ί二库其Ϊ在該場多晶矽回姓過程中被偵測::μ ’ t 時“貞:的信號。剩餘的物程ΐ 』圮度屋纟冑充兩度,可使該場電極填充該溝槽。在此
200304702 五、發明說明(7) 方式中’ s亥填充兩度可被調敕一 其係於稍後該半導體基質中二 k ,示移區接合處, 尸+代及一丄办 土貝中所形成。在此配置的範例中,兮 = 平面電性連接,相對地,在第-“製i 該琢夕日日矽於该基質表面之 衣& 接之區域中。在該活化& & _ A而後被後盍於用於接觸連 在此r心ί 胞7"陣列中,該場電極再被回敍。 :據化的蝕刻程序之信號無法簡單地產生。 極係縮短的,因此嗲、、羞"/ f溝槽中5亥邊緣區中該場電 雷托甘γ _巧方式係電連接至該胞元陣列之嗲η托 =if電傳導連接至遠離該胞元陣列之-閑極全;Γ :该场電極係電傳導連接至位於該胞元陣列上之—場ϋ 在較佳實施例中,該基質表 面係以絕緣層,達到彼此雷二構與該基質表 且俜H ^ 緣且與該半導體基質電絕缘, 層平面上。因此優點為該間極與 = 面結構,且為非關鍵的場條件。 再你為千 槿卜較佳之方式為該閘極結構係至少配置…… 構上之橫切面上,該閘極結構係藉由一中 亥%結 %緣。此一配置方式造成非中 ^而電性 位與該閘極結構間的該場結構係自該閘極結構= 附力二另電2:實::;傳=ΐ:之電晶體配置具有-、、鲕,兵係電傳導連接至該場金屬化,且其中可 第12頁 200304702 五、發明說明(8)
Si Ϊ 該源極、閘極與汲極電位旁之該電晶體配置, $、蓋二二’虽可更有效地控制。此外,該場金屬化係連接至 “溝槽刪電〜力電晶體可控制此-電位之電流部分。 化相實施例中,該場金屬化係與該源極金屬 接至該源極金屬化。藉由控制該場電極之電 位與a玄源極電位,# p f ^ 制。 3亥场電極可用非常簡單的方式而被有效控 ί上所述,本發明已如溝槽電晶體胞元之實施例中所 ί田發Ϊ可延伸至具汲極上結構之1GBT。再者,本發明可 心於正#開與正常關之ρ-通道與η-通道電晶體胞元。 ίΐΓΐ更詳細說明可參照所提供之圖示,其中相同之符號 係指相同之元件。 發明之詳細說明 第一圖a係一溝槽M0S電力電晶體的 中,-活化的胞元陣列2係與一邊緣區域4相連丄二 兀陣列2具有複數個溝槽電晶體胞元3沿著並聯溝槽9配置。 該溝槽9係延長至該邊緣區域4,在此範例中配置於該溝 槽9中的電極結構首先藉由橫向溝槽91而彼此電傳導連接。 在該溝槽9與該橫向溝槽91之間的電連接,以一已知的方式 避免乂叉’且T結構的處理過程較不具決定性。 在該邊緣區域4中,該溝槽9具有第一開口切面212,立 中製造該較上的電極結構(閘極電極)於該溝槽9中,且其/中 §亥杈下的電極結構(場電極)填充該溝槽9至一基質表面而不 需絕緣層。
200304702 五、發明說明(9) 再者’在該邊緣區域4中該溝槽9具有第二開口 202,其中該閘極電極1〇在每一中係 不需絕緣層。 /基貝表面上而 場電極’在此範例中係如源極結構2 11, 的傳導半導體材質製造,如同嗲意之莖 其係以相同 士曰雷托甘〆 如问該,冓槽9之第一開口切面212的 :::雷;;糸:連接至該場電極。在此範例中,該源極結構 係自該傳導半導體材質之單一沉積層產生,例如 利用回餘的方式。 =結構2(31延伸於該第二開口切面202上。該個別的 =電極係電傳導連接至該閘極結獅!。該閘極結構2〇1與 邊閘極電極亦自該傳導半導體材質之單一沉積層產生,例如 利用回蝕的方式。該閘極結構2〇1係更延伸至該源極結構2ΐι 之上,該閘極結構201與該源極結構211係藉由一絕緣層〗6而 彼此電性絕緣。一中間氧化物層丨6係在該閘極結構2〇丨曰之切 面中。 乂#配置上述該閘極結構201之切面係為閘極金屬化2〇,其 係藉由平面穿孔3 1透過該中間氧化物層丨6而電傳導連接至該 閘極結構2 〇 1。 一場金屬化,如同此範例中源極金屬化2丨,係於該活化 的胞元陣列2之區域中與該邊緣區域4的切面中。該源^金屬 化2 1係經由該活化的胞源陣列2中平面穿孔33而連接至該溝 槽電晶體胞元3之源極區。在該邊緣區域4中,該源極金屬化 21係經由平面穿孔32而電傳導連接至該源極結構21ι。 第一圖b中詳細說明沿著第一圖a中溝槽M0S電力電晶體
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A -B的橫切面。
一與第一圖a相較,第一圖b說明一場氧化物層15,其係將 一半導體基質6自配置於該基質表面7上之該結構2〇1、211電 性、、’巴、、彖。再者,第一圖b說明該源極結構2 11、該源極結構 211上之該閘極結構2〇1以及該絕緣層丨5、丨6之該金屬化2〇、 2 1之垂直配置。在此範例中,該絕緣層丨5、丨6之絕緣,特別 係為非常簡化之方法。所以,每一絕緣層丨5、丨6可被包埋為 多層系統。交接處的該絕緣層丨5、丨6係端視於該製造方式, 如沉積式或氧化方式。同樣地,該閘極與該場電極丨〇、丨丨且 該%結構2 0 1、2 11可用矽化物或金屬強化,或是可完全由矽 化物或金屬或其他高傳導物質組成。 第^圖a係第二實施例之平面圖,用以說明一溝槽M〇s電力電 相#乂於第一圖中所示之實施例,該閘極結構2 〇 1係被配 裏,β源極結構2 11之旁。個別源極結構2 i i之相互抵銷配置 造成^源極結構211區域中該閘極結構2〇ι之網狀物。在溝槽 ;、力電曰曰體運作^呈中,該間極結構之網狀物造成該閘 棰結構2 0 1中均勻的電位分布。 第一圖b係根據第二圖&中本發明第二實施例之溝槽 電力電晶體之C-D橫切面的詳细說明。 因;,該閑極結構201與該源極結_係相連配置於-半導 艨f質6之基質表面7之上,因而產生該場結構201、211與該 金屬化2 0、2 1之平面的型熊。
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200304702 圖式簡單說明 第一圖係說明第一實施例之溝槽M0S電力電晶體且說明沿著^ A-B的橫切面之一平面概示圖。 第二圖係說明一溝槽電晶體胞元之橫切面之一概示圖。 第三圖係說明第二實施例之溝槽M0S電力晶體且說明沿著C-D 之橫切面之一概示圖。 元件符號說明 1 電 晶 體 配 置 2 活 化 胞 元 陣 列 3 (溝槽) 電 晶體胞元 4 邊 緣 區 域 5 通 道 6 半 導 體 基 質 7 基 質 表 面 8 基 質 後 側 9 溝 槽 10 閘 極 電 極 11 場 電 極 12 絕 緣層 13 場 電 極 上 絕緣層 14 閘 極 氧 化 物 15 場 氧 化 物 層(F0X) 16 中 間 氧 化 物 層 20 閘 極 金 屬 化 21 源 極 金 屬 化 22 汲 極 金 屬 化 23 半 導 體 本 體 31 平 面 穿 孔 32 平 面 穿 孔 33 平 面 穿 孔 91 橫 向 溝槽 201 閘 極 結 構 20^ ί第 _ 一 切 面 203 通 道 區 21 C 1場 金 屬 化 211 源 極 結 構(場結構) 2Π ί第 一 切 面 213 二 區 22 3汲 極 區 224 :漂 移 區 %
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Claims (1)
- 200304702 六、申請專利範圍 1 · 一種電晶體排列,其包含: 至少一閘極終端,一源極終端與一汲極終端, 至少一活化胞元陣列(2 )形成於一半導體基質(6 )中, 一邊緣區域(4 )與該活化的胞元陣列(2 )相連, 至夕、溝槽(9 )於該半導體基質之該活化胞元陣列(6 ) 中, 至少一溝槽電晶體胞元(3),其係沿著該至少一溝槽(9) 而形成, s 至少兩電極結構(10,;1丨),其係被配置於該溝槽(9)中’ ’且沿著該溝槽(9 )延伸, 至少一金屬化(20,21)配置於該半導體基質(6)之一某 質表面(7)之上, 1 ,以及 導連接至該邊緣 該溝槽(9 )係被導出至該邊緣區域(4 )中 至少該兩電極結構(1 0, 1 1 )之一係電傳 區域(4)中該金屬化(20,21)之一。 2·如=專利範圍第1項之電晶體排列,其中 ⑼至中少一其V雷與:第二電極結構(1 °,11)係配置於該溝:” 極結構係相鄰且/或上下配置,且姑士垂 絕緣且與該半導騁A所r 、 彼此電 (10,11)係各自電=首U邑緣,以及該電極結構 2 。 電丨生傳今連接至一對應之金屬化(2 0, 3 ·如申請專利範圍第J 項或第2項之電晶體排列 其中該電第17頁 200304702 六、申請專利範圍 晶體配置係如一溝槽M0S電力電晶體,其具有至少_ 金屬化(2 0 ),其係電性傳導連接至該閘極終端,一閘^極 屬化(2 1 )’其係電性傳導連接至該源極終端,以及、、"金 金屬化(2 2 ),其係電性傳導連接至該汲極終端,該^ j極 極金屬化係與該第一金屬化(2 0 )相同,且黾少抑\弟 閘 土 乂 冲分環辑 該源極金屬化,其係配置於該胞元陣列之 上。 、几; 4 ·如申請專利範圍第1項至第3項中任一項之電晶體排列 其中在個別的胞元陣列(2 )中,提供複數個溝槽電晶體’ 元U)至複數個溝槽(6)中,以及在每一溝槽(6)中^ 一電極結構係如閘極結構(1 〇 )且該第二電極結構係如3曰。 極(11 ),該場電極(1 1 )係配置於該閘極電極(丨〇 ) 之下野電 5·如申請專利範圍第1項至第4項中任一項之電晶體 其中 j , 一個別胞元陣列(2 )之複數個溝槽電晶體胞元(3 )之兮 極電極(1 〇 )係藉由橫向溝槽(g 1 )而達到彼此電傳導連 至少一部分的場金屬化(21 0)係配置於該溝槽(9)之 j ’ 切面(212)上之該邊緣區域(4)中,以及 一 該場金屬化(2 1 0 )係藉由至少一平面穿孔(3 2 ),而電 導連接至該溝槽(9 )中的該場電極(11 )。 ” 6 ·如申請專利範圍第5項之電晶體排列,其中 至少一部分的場金屬化(2 〇 )係配置於該溝槽(9 )之第 200304702 六、申請專利範圍 切面(202)上之該邊緣區域(4)中,且藉由至少一平面穿孔 (31),而電傳導連接至該溝槽(9)中的該閘極電極(1〇)。 7.如申請專利範圍第5項之電晶體排列,豆中 上1閘極電極(10)係自該基質表面(7)上第二切面(2〇2)中 5玄邊緣區域(4)導出,且在該基質表面向(7)上形成一閘 極結構(201),以及 ❿风网 一部分的閘極金屬化(2〇)係排列於該閘極結構 而區,切面中’且藉由複數個平面穿孔㈤ 而電‘性傳導連接至該閘極結構(2〇1)。 8其=申請專利範圍第!項至第4項中任—項之電晶體排列’ 邊= 系自該基質表面⑺上第-切面(2⑴ 二以Τ 且在該基質表面⑺上形成-場結構 (2=f Λ部/的閑極金屬化(20)係排列於該閉極結構 )上邊緣區域(4)切面中,且藉由複數個平面 而電性傳導連接至該閘極結構(2 0 1 )。 9.如申請專利範圍第8項之電晶體排列,其中 至少一部分的閘極金屬化(2〇)係排於嗲 二切面(202)上之該邊緣區域⑷中:9)之第 孔(31)而電性傳導連接至該溝槽(9)中的該間極電#面穿 第19頁 200304702(10)。 第8項之電晶體排列,t中 :閘極電極〇〇)係自該基質表j :中 該邊緣區域(4)導出,以及在兮()上弟二切面(202 )中 結構(201), 在基貝表面(7)上形成一閘 (20^上一之部Λ"?極金屬化(2〇)係排列於該閘極結構 (31)而雷域(4)切面中,且藉由複數個平面穿 (31)而電性傳導連接至該閘極結構(2〇ι)。 < n· f申請專利範圍第10項之電晶體排列,其中 一忒閘極結構(2 〇 1 )與該場結構(2丨1 )係獨佔地形成於一 共同平面上,該閘極結構(2 〇丨)至少部分環繞該場結構 (211)。 1 2 ·如申請專利範圍第1 〇項之電晶體排列,其中 該場結構(2 1 1 )至少切面被該閘極結構(2 〇 1 )覆蓋第二 層。 1 3·如申請專利範圍第1項至第丨2項中任一項之電晶體排 列,其中 該電晶體排列具有一場終端,其係電性傳導連接至 場金屬化(2 1 0 )。 “第20頁 200304702 六、申請專利範圍 1 4.如申請專利範圍第1項至第1 2項中任一項之電晶體排 列,其中 該場金屬化(2 1 0 )係與該源極金屬化(2 1)相同。 1 5.如申請專利範圍第1項至第1 4項中任一項之電晶體排 列,其中 該閘極電極(10)與該閘極結構(201)係自同一層產生 1 6.如申請專利範圍第1項至第1 5項中任一項之電晶體排 列η其中 該場電極(11)與該場結構(211)係自同一層產生。 鲁第21頁
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DE10212144A DE10212144B4 (de) | 2002-03-19 | 2002-03-19 | Transistoranordnung mit einer Struktur zur elektrischen Kontaktierung von Elektroden einer Trench-Transistorzelle |
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TWI398000B (zh) * | 2006-02-17 | 2013-06-01 | Alpha & Omega Semiconductor | 保護閘極溝槽式金氧半場效電晶體(sgt mosfet)元件及其製造方法 |
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US6891223B2 (en) | 2005-05-10 |
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DE10212144A1 (de) | 2003-10-30 |
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