SG160295A1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- SG160295A1 SG160295A1 SG200906069-0A SG2009060690A SG160295A1 SG 160295 A1 SG160295 A1 SG 160295A1 SG 2009060690 A SG2009060690 A SG 2009060690A SG 160295 A1 SG160295 A1 SG 160295A1
- Authority
- SG
- Singapore
- Prior art keywords
- single crystal
- crystal semiconductor
- semiconductor substrate
- substrate
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 10
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 11
- 239000013078 crystal Substances 0.000 abstract 9
- 239000011521 glass Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000001629 suppression Effects 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008249401 | 2008-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG160295A1 true SG160295A1 (en) | 2010-04-29 |
Family
ID=42057898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200906069-0A SG160295A1 (en) | 2008-09-29 | 2009-09-11 | Method for manufacturing semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (2) | US7943487B2 (zh) |
JP (1) | JP5586906B2 (zh) |
KR (1) | KR101630216B1 (zh) |
CN (1) | CN101714519B (zh) |
SG (1) | SG160295A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101443580B1 (ko) * | 2007-05-11 | 2014-10-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Soi구조를 갖는 기판 |
SG160295A1 (en) * | 2008-09-29 | 2010-04-29 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
US8043938B2 (en) | 2009-05-14 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and SOI substrate |
JP2011029609A (ja) * | 2009-06-26 | 2011-02-10 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法およびsoi基板 |
JP5866088B2 (ja) * | 2009-11-24 | 2016-02-17 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
JP5926887B2 (ja) * | 2010-02-03 | 2016-05-25 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4882610A (en) * | 1987-10-29 | 1989-11-21 | Deutsche Itt Industries Gmbh | Protective arrangement for MOS circuits |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US6191007B1 (en) | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
JPH1145862A (ja) | 1997-07-24 | 1999-02-16 | Denso Corp | 半導体基板の製造方法 |
JP2000012864A (ja) | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
US6380019B1 (en) | 1998-11-06 | 2002-04-30 | Advanced Micro Devices, Inc. | Method of manufacturing a transistor with local insulator structure |
DE19936941B4 (de) * | 1998-11-11 | 2008-11-06 | Robert Bosch Gmbh | Verfahren zur Herstellung dünner Schichten, insbesondere Dünnschichtsolarzellen, auf einem Trägersubstrat |
JP4677707B2 (ja) * | 2003-05-30 | 2011-04-27 | セイコーエプソン株式会社 | 電気光学装置用薄膜トランジスタアレイ基板の製造方法 |
FR2855650B1 (fr) * | 2003-05-30 | 2006-03-03 | Soitec Silicon On Insulator | Substrats pour systemes contraints et procede de croissance cristalline sur un tel substrat |
JP4759919B2 (ja) * | 2004-01-16 | 2011-08-31 | セイコーエプソン株式会社 | 電気光学装置の製造方法 |
JP5110772B2 (ja) | 2004-02-03 | 2012-12-26 | 株式会社半導体エネルギー研究所 | 半導体薄膜層を有する基板の製造方法 |
FR2888663B1 (fr) * | 2005-07-13 | 2008-04-18 | Soitec Silicon On Insulator | Procede de diminution de la rugosite d'une couche epaisse d'isolant |
US7288458B2 (en) | 2005-12-14 | 2007-10-30 | Freescale Semiconductor, Inc. | SOI active layer with different surface orientation |
JP4839818B2 (ja) * | 2005-12-16 | 2011-12-21 | 信越半導体株式会社 | 貼り合わせ基板の製造方法 |
US8629490B2 (en) | 2006-03-31 | 2014-01-14 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor storage device with floating gate electrode and control gate electrode |
EP1975998A3 (en) | 2007-03-26 | 2013-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a plurality of island-shaped SOI structures |
US7846817B2 (en) | 2007-03-26 | 2010-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
SG160295A1 (en) | 2008-09-29 | 2010-04-29 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
-
2009
- 2009-09-11 SG SG200906069-0A patent/SG160295A1/en unknown
- 2009-09-23 US US12/564,951 patent/US7943487B2/en not_active Expired - Fee Related
- 2009-09-24 CN CN200910178514.5A patent/CN101714519B/zh not_active Expired - Fee Related
- 2009-09-25 JP JP2009219856A patent/JP5586906B2/ja not_active Expired - Fee Related
- 2009-09-29 KR KR1020090092163A patent/KR101630216B1/ko active IP Right Grant
-
2011
- 2011-05-12 US US13/106,301 patent/US8273637B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20100036208A (ko) | 2010-04-07 |
JP5586906B2 (ja) | 2014-09-10 |
CN101714519B (zh) | 2014-03-12 |
CN101714519A (zh) | 2010-05-26 |
US20110212597A1 (en) | 2011-09-01 |
US7943487B2 (en) | 2011-05-17 |
JP2010103513A (ja) | 2010-05-06 |
KR101630216B1 (ko) | 2016-06-14 |
US8273637B2 (en) | 2012-09-25 |
US20100081252A1 (en) | 2010-04-01 |
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