SG159436A1 - Method for fabricating a semiconductor on insulator substrate with reduced secco defect density - Google Patents

Method for fabricating a semiconductor on insulator substrate with reduced secco defect density

Info

Publication number
SG159436A1
SG159436A1 SG200903082-6A SG2009030826A SG159436A1 SG 159436 A1 SG159436 A1 SG 159436A1 SG 2009030826 A SG2009030826 A SG 2009030826A SG 159436 A1 SG159436 A1 SG 159436A1
Authority
SG
Singapore
Prior art keywords
substrate
semiconductor
fabricating
source
defect density
Prior art date
Application number
SG200903082-6A
Other languages
English (en)
Inventor
Luciana Capello
Oleg Kononchuk
Eric Neyret
Alexandra Abbadie
Walter Schwarzenbach
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG159436A1 publication Critical patent/SG159436A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
SG200903082-6A 2008-09-03 2009-05-06 Method for fabricating a semiconductor on insulator substrate with reduced secco defect density SG159436A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08290825.2A EP2161741B1 (en) 2008-09-03 2008-09-03 Method for fabricating a semiconductor on insulator substrate with reduced SECCO defect density

Publications (1)

Publication Number Publication Date
SG159436A1 true SG159436A1 (en) 2010-03-30

Family

ID=40259201

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200903082-6A SG159436A1 (en) 2008-09-03 2009-05-06 Method for fabricating a semiconductor on insulator substrate with reduced secco defect density

Country Status (7)

Country Link
US (1) US7947571B2 (zh)
EP (1) EP2161741B1 (zh)
JP (1) JP5745753B2 (zh)
KR (1) KR101623968B1 (zh)
CN (1) CN101667553B (zh)
SG (1) SG159436A1 (zh)
TW (1) TWI498972B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343379B2 (en) * 2011-10-14 2016-05-17 Sunedison Semiconductor Limited Method to delineate crystal related defects
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
JP6086031B2 (ja) * 2013-05-29 2017-03-01 信越半導体株式会社 貼り合わせウェーハの製造方法
FR3051979B1 (fr) * 2016-05-25 2018-05-18 Soitec Procede de guerison de defauts dans une couche obtenue par implantation puis detachement d'un substrat
FR3063176A1 (fr) * 2017-02-17 2018-08-24 Soitec Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique
FR3077923B1 (fr) * 2018-02-12 2021-07-16 Soitec Silicon On Insulator Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche
CN112262467A (zh) * 2018-06-08 2021-01-22 环球晶圆股份有限公司 将硅薄层移转的方法
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3327180B2 (ja) 1997-08-29 2002-09-24 信越半導体株式会社 Ｓｏｉ層上酸化膜の形成方法ならびに結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ
FR2777115B1 (fr) 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2797714B1 (fr) 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
DE10131249A1 (de) 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
FR2827423B1 (fr) 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
EP1652230A2 (fr) * 2003-07-29 2006-05-03 S.O.I.Tec Silicon on Insulator Technologies Procede d' obtention d' une couche mince de qualite accrue par co-implantation et recuit thermique
FR2858462B1 (fr) 2003-07-29 2005-12-09 Soitec Silicon On Insulator Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
JP2005286220A (ja) * 2004-03-30 2005-10-13 Toshiba Ceramics Co Ltd シリコンウェーハの品質評価方法
WO2006032947A1 (en) * 2004-09-21 2006-03-30 S.O.I.Tec Silicon On Insulator Technologies Thin layer transfer method wherein a co-implantation step is performed according to conditions avaoiding blisters formation and limiting roughness
CN100550342C (zh) 2004-12-28 2009-10-14 S.O.I.Tec绝缘体上硅技术公司 用于获得具有低密度孔的薄层的方法
JP4934966B2 (ja) 2005-02-04 2012-05-23 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
JP2006216826A (ja) 2005-02-04 2006-08-17 Sumco Corp Ｓｏｉウェーハの製造方法
FR2895563B1 (fr) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
FR2898431B1 (fr) * 2006-03-13 2008-07-25 Soitec Silicon On Insulator Procede de fabrication de film mince
FR2903809B1 (fr) 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法

Also Published As

Publication number Publication date
TW201011833A (en) 2010-03-16
EP2161741B1 (en) 2014-06-11
TWI498972B (zh) 2015-09-01
KR101623968B1 (ko) 2016-05-24
CN101667553A (zh) 2010-03-10
KR20100027947A (ko) 2010-03-11
US20100052092A1 (en) 2010-03-04
EP2161741A1 (en) 2010-03-10
JP5745753B2 (ja) 2015-07-08
JP2010062532A (ja) 2010-03-18
CN101667553B (zh) 2015-03-11
US7947571B2 (en) 2011-05-24

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