SG11201901194SA - Wafer-level package with enhanced performance - Google Patents

Wafer-level package with enhanced performance

Info

Publication number
SG11201901194SA
SG11201901194SA SG11201901194SA SG11201901194SA SG11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA
Authority
SG
Singapore
Prior art keywords
die
thinned
wafer
mold compound
international
Prior art date
Application number
SG11201901194SA
Inventor
Julio Costa
Jan Vandemeer
Jonathan Hammond
Merrill Hatcher
Jon Chadwick
Original Assignee
Qorvo Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qorvo Us Inc filed Critical Qorvo Us Inc
Publication of SG11201901194SA publication Critical patent/SG11201901194SA/en

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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

APPLYA THIRD DIELECTRIC LAYER AT THE BOTTOM SURFACE OF THE MULTILAYER REDISTRUBUTION STRUCTURE THIN DOWN THE FIRST MOLD COMPOUND TO EXPOSE THE SUBSTRATES OF THE DIE AND THE MEMS DIE REMOVE SUBSTANRALY THE SUBSTRATES OF THE SOI DIE AND THE MEMS DIE TO PROVIDE AN ETCHED PRECUSOR PACKAGE, WHICH INCLUDES A THINNED SOI DIE WITH A FIRST CAVITY AND A THINNED MEMS DIE WITH A SECOND CAVITY ATTACH THE ETCHED PRECUSOR PACKAGE TO A RIGID CARRIER MAN ADHESIVE MATERIAL. WHERE THE BOTTOM SURFACE OF THE THIRD DIELECTRIC LAYER IS IN CONTACT WITH THE ADHESIVE MATERIAL APPLY A SECOND MOLD COMPOUND TO SUBSTANTIALLY FILL THE FIRST AND SECOND CAVITIES (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 15 February 2018 (15.02.2018) WIP0 I PCT olimion °nolo III 01110l (10) International Publication Number WO 2018/031995 Al (51) International Patent Classification: H01L 23/31 (2006.01) H01L 21/60 (2006.01) H01L 21/56 (2006.01) (21) International Application Number: PCT/US2017/046758 (22) International Filing Date: 14 August 2017 (14.08.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/374,318 12 August 2016 (12.08.2016) US 62/374,332 12 August 2016 (12.08.2016) US 62/374,439 12 August 2016 (12.08.2016) US (71) Applicant: QORVO US, INC. [US/US]; 7628 Thomdike Road, Greensboro, North Carolina 27409 (US). (72) Inventors: COSTA, Julio, C.; 6601 Ashton Park Drive, Oak Ridge, North Carolina 27310 (US). VANDEMEER, Jan, Edward; 279 Weatherfield Lane, Kemersville, North Carolina 27284 (US). HAMMOND, Jonathan, Hale; 5808 Autumn Gate Drive, Oak Ridge, North Carolina 27310 (US). HATCHER, Merrill, Albert, Jr.; 5607 Old Fox Trail, Greensboro, North Carolina 27407 (US). CHAD- WICK, Jon; 1907 Efland Drive, Greensboro, North Caroli- na 27408 (US). (74) Agent: WITHROW, Benjamin, S.; WITHROW & TER- RANOVA, P.L.L.C., 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, (54) Title: WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE (57) : The present disclosure relates to a packaging process to en- 00 Nance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die 102 (14) having a first device layer (20), a multilayer redistribution structure (52), a first mold compound (42), and a second mold compound (74). The multi- 104 layer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects con- necting the first device layer to the package contacts. The first mold com- 1 pound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to de- fine a cavity (66) within the first mold compound and over the first thinned 1613 die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die. 110 I 112 I 116 118 CURE THE SECOND MOLD COMPOUND PLANARIZE A TOP SURFACE OF THE SECOND MOLD , XIMPOUND W O 20 18/03 1995 Al DETACH THE RIGID CARRIER FROM THE THIRD DIELECTRIC LAYER COMPLETE A WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE MARK. DICE. AND SINGULATE THE WAFER-LEVEL PACKAGE FIG. 9 [Continued on next page] WO 2018/031995 Al D ill TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: with international search report (Art. 21(3)) with amended claims (Art. 19(1))
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