SG10095G - Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer - Google Patents

Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer

Info

Publication number
SG10095G
SG10095G SG10095A SG10095A SG10095G SG 10095 G SG10095 G SG 10095G SG 10095 A SG10095 A SG 10095A SG 10095 A SG10095 A SG 10095A SG 10095 G SG10095 G SG 10095G
Authority
SG
Singapore
Prior art keywords
capping
fabricating
semiconductor device
conductive layer
nitride layer
Prior art date
Application number
SG10095A
Other languages
English (en)
Inventor
Michael S Wang
Kuang-Yi Chiu
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Priority to SG10095A priority Critical patent/SG10095G/en
Publication of SG10095G publication Critical patent/SG10095G/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG10095A 1989-05-22 1995-01-23 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer SG10095G (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG10095A SG10095G (en) 1989-05-22 1995-01-23 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/356,021 US4923822A (en) 1989-05-22 1989-05-22 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer
SG10095A SG10095G (en) 1989-05-22 1995-01-23 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer

Publications (1)

Publication Number Publication Date
SG10095G true SG10095G (en) 1995-06-16

Family

ID=23399784

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10095A SG10095G (en) 1989-05-22 1995-01-23 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer

Country Status (6)

Country Link
US (1) US4923822A (fr)
EP (1) EP0399141B1 (fr)
JP (1) JPH034527A (fr)
KR (1) KR900019171A (fr)
DE (1) DE69011203T2 (fr)
SG (1) SG10095G (fr)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02262371A (ja) * 1989-04-03 1990-10-25 Toshiba Corp 半導体装置及びその製造方法
US5268590A (en) * 1989-12-27 1993-12-07 Motorola, Inc. CMOS device and process
US5288666A (en) * 1990-03-21 1994-02-22 Ncr Corporation Process for forming self-aligned titanium silicide by heating in an oxygen rich environment
US5443996A (en) * 1990-05-14 1995-08-22 At&T Global Information Solutions Company Process for forming titanium silicide local interconnect
US5130266A (en) * 1990-08-28 1992-07-14 United Microelectronics Corporation Polycide gate MOSFET process for integrated circuits
US5196360A (en) * 1990-10-02 1993-03-23 Micron Technologies, Inc. Methods for inhibiting outgrowth of silicide in self-aligned silicide process
US5326724A (en) * 1991-12-27 1994-07-05 Texas Instruments Incorporated Oxide-capped titanium silicide formation
TW209308B (en) * 1992-03-02 1993-07-11 Digital Equipment Corp Self-aligned cobalt silicide on MOS integrated circuits
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
US5576556A (en) * 1993-08-20 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Thin film semiconductor device with gate metal oxide and sidewall spacer
US5384285A (en) * 1993-07-26 1995-01-24 Motorola, Inc. Process for fabricating a silicide layer in a semiconductor device
US5420058A (en) * 1993-12-01 1995-05-30 At&T Corp. Method of making field effect transistor with a sealed diffusion junction
KR0135163B1 (ko) * 1993-12-16 1998-04-22 문정환 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법
EP0724287A3 (fr) * 1995-01-30 1999-04-07 Nec Corporation Méthode de fabrication d'un dispositif à semiconducteur comprenant un film de siliciure de titane
US6376372B1 (en) * 1995-06-02 2002-04-23 Texas Instruments Incorporated Approaches for mitigating the narrow poly-line effect in silicide formation
US5593924A (en) * 1995-06-02 1997-01-14 Texas Instruments Incorporated Use of a capping layer to attain low titanium-silicide sheet resistance and uniform silicide thickness for sub-micron silicon and polysilicon lines
TW366585B (en) * 1996-08-17 1999-08-11 United Microelectronics Corp Manufacturing method of low-temperature epitaxy titanium silicide
US6080645A (en) * 1996-10-29 2000-06-27 Micron Technology, Inc. Method of making a doped silicon diffusion barrier region
US5679585A (en) * 1996-11-15 1997-10-21 Advanced Micro Devices, Inc. Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants
US5926730A (en) * 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
US6015997A (en) 1997-02-19 2000-01-18 Micron Technology, Inc. Semiconductor structure having a doped conductive layer
US6262458B1 (en) 1997-02-19 2001-07-17 Micron Technology, Inc. Low resistivity titanium silicide structures
JPH10335613A (ja) * 1997-05-27 1998-12-18 Mitsubishi Electric Corp 半導体集積回路装置
JP3248570B2 (ja) * 1997-10-09 2002-01-21 日本電気株式会社 半導体装置の製造方法
KR100481839B1 (ko) * 1997-10-23 2005-07-07 삼성전자주식회사 반도체장치의제조방법
US6211083B1 (en) 2000-04-17 2001-04-03 Taiwan Semiconductor Manufacturing Company Use of a novel capped anneal procedure to improve salicide formation
TW522513B (en) 2001-10-09 2003-03-01 Winbond Electronics Corp Manufacturing method of self-aligned silicide for metal oxide semiconductor transistor
US7214630B1 (en) * 2005-05-06 2007-05-08 Novellus Systems, Inc. PMOS transistor with compressive dielectric capping layer
US7504336B2 (en) * 2006-05-19 2009-03-17 International Business Machines Corporation Methods for forming CMOS devices with intrinsically stressed metal silicide layers
TWI549301B (zh) * 2014-05-27 2016-09-11 華亞科技股份有限公司 垂直式電晶體結構與形成垂直式電晶體結構接觸節點的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137367A (ja) * 1984-12-10 1986-06-25 Hitachi Ltd 半導体集積回路装置の製造方法
US4657628A (en) * 1985-05-01 1987-04-14 Texas Instruments Incorporated Process for patterning local interconnects
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation

Also Published As

Publication number Publication date
KR900019171A (ko) 1990-12-24
DE69011203T2 (de) 1995-03-16
EP0399141B1 (fr) 1994-08-03
EP0399141A2 (fr) 1990-11-28
US4923822A (en) 1990-05-08
DE69011203D1 (de) 1994-09-08
EP0399141A3 (fr) 1991-10-30
JPH034527A (ja) 1991-01-10

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