SE9901290D0 - Avdelad buffert - Google Patents

Avdelad buffert

Info

Publication number
SE9901290D0
SE9901290D0 SE9901290A SE9901290A SE9901290D0 SE 9901290 D0 SE9901290 D0 SE 9901290D0 SE 9901290 A SE9901290 A SE 9901290A SE 9901290 A SE9901290 A SE 9901290A SE 9901290 D0 SE9901290 D0 SE 9901290D0
Authority
SE
Sweden
Prior art keywords
buffer
data
buffer device
integrated circuit
divided buffer
Prior art date
Application number
SE9901290A
Other languages
English (en)
Other versions
SE515897C2 (sv
SE9901290L (sv
Inventor
Niklas Roejemo
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9901290A priority Critical patent/SE515897C2/sv
Publication of SE9901290D0 publication Critical patent/SE9901290D0/sv
Priority to PCT/SE2000/000631 priority patent/WO2000062153A1/en
Priority to AU43223/00A priority patent/AU4322300A/en
Priority to DE10084462T priority patent/DE10084462B4/de
Priority to US09/547,386 priority patent/US6625672B1/en
Publication of SE9901290L publication Critical patent/SE9901290L/sv
Publication of SE515897C2 publication Critical patent/SE515897C2/sv

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/066User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
SE9901290A 1999-04-12 1999-04-12 Anordning och förfarande för en avdelad buffert SE515897C2 (sv)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SE9901290A SE515897C2 (sv) 1999-04-12 1999-04-12 Anordning och förfarande för en avdelad buffert
PCT/SE2000/000631 WO2000062153A1 (en) 1999-04-12 2000-03-31 Divided buffer
AU43223/00A AU4322300A (en) 1999-04-12 2000-03-31 Divided buffer
DE10084462T DE10084462B4 (de) 1999-04-12 2000-03-31 Geteilter Puffer
US09/547,386 US6625672B1 (en) 1999-04-12 2000-04-11 Divided buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9901290A SE515897C2 (sv) 1999-04-12 1999-04-12 Anordning och förfarande för en avdelad buffert

Publications (3)

Publication Number Publication Date
SE9901290D0 true SE9901290D0 (sv) 1999-04-12
SE9901290L SE9901290L (sv) 2000-10-13
SE515897C2 SE515897C2 (sv) 2001-10-22

Family

ID=20415177

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9901290A SE515897C2 (sv) 1999-04-12 1999-04-12 Anordning och förfarande för en avdelad buffert

Country Status (5)

Country Link
US (1) US6625672B1 (sv)
AU (1) AU4322300A (sv)
DE (1) DE10084462B4 (sv)
SE (1) SE515897C2 (sv)
WO (1) WO2000062153A1 (sv)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7136991B2 (en) * 2001-11-20 2006-11-14 Henry G Glenn Microprocessor including random number generator supporting operating system-independent multitasking operation
US7219112B2 (en) * 2001-11-20 2007-05-15 Ip-First, Llc Microprocessor with instruction translator for translating an instruction for storing random data bytes
US20060064448A1 (en) * 2001-11-20 2006-03-23 Ip-First, Llc. Continuous multi-buffering random number generator
US7512721B1 (en) 2004-05-25 2009-03-31 Qlogic, Corporation Method and apparatus for efficient determination of status from DMA lists
US7895390B1 (en) * 2004-05-25 2011-02-22 Qlogic, Corporation Ensuring buffer availability

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233603A (en) * 1988-04-21 1993-08-03 Nec Corporation Packet switch suitable for integrated circuit implementation
JPH03212776A (ja) * 1990-01-18 1991-09-18 Nec Corp ワンチップcpu
KR970010368B1 (ko) * 1994-01-18 1997-06-25 삼성전자 주식회사 캐시라인 리프레이스장치 및 방법
US5490113A (en) * 1994-06-15 1996-02-06 Digital Equipment Corporation Memory stream buffer
US5852826A (en) * 1996-01-26 1998-12-22 Sequent Computer Systems, Inc. Parallel merge sort method and apparatus
IL116984A (en) * 1996-01-31 2000-07-26 Galileo Technology Ltd Multiple FIFO array and method of construction thereof
US6290406B1 (en) * 1996-09-20 2001-09-18 Varis Corporation System and method for interfacing a raster printer controller with a plurality of print engines
US5959466A (en) * 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6078565A (en) * 1997-06-20 2000-06-20 Digital Equipment Corporation Method and apparatus to expand an on chip FIFO into local memory
KR100327330B1 (ko) * 1998-12-17 2002-05-09 윤종용 램버스디램반도체장치

Also Published As

Publication number Publication date
SE515897C2 (sv) 2001-10-22
AU4322300A (en) 2000-11-14
DE10084462B4 (de) 2009-08-13
WO2000062153A1 (en) 2000-10-19
US6625672B1 (en) 2003-09-23
SE9901290L (sv) 2000-10-13
DE10084462T1 (de) 2002-03-21

Similar Documents

Publication Publication Date Title
DE69418020D1 (de) Ausgangspufferkreis, Eingangspufferkreis und Zweirichtungspufferkreis für mehrere Spannungssysteme
EP1213655A3 (en) Circuits and methods for interconnecting bus systems
DE69514394D1 (de) Ein-/Ausgabedatenports
WO2003044652A3 (en) High-speed first-in-first-out buffer
BR9900530A (pt) Amplificador de faixa duplas.
EP1612573A3 (en) Test circuit and semiconductor integrated circuit effectively carrying out verification of connection of nodes
TR200001328T2 (tr) Tele-yazı aygıtı
SE9901290D0 (sv) Avdelad buffert
DE69531597D1 (de) Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis
EP1324189A3 (en) Self-timed digital processing circuits
KR960043531A (ko) 고속 동기 카운터 회로
KR910014940A (ko) 반도체 기억장치
KR970055506A (ko) 혼합 전압 입력 버퍼
DE60044145D1 (de) Brückeschnittstellenschaltung
WO2005027549A8 (de) Verlängerung der sim-karten-schnittstelle in gsm-geräten
SE9801674D0 (sv) Application specific integrated circuit and transceiver circuit
TW431067B (en) Single source differential circuit
DE60324502D1 (de) Bandführunsgvorichtung
KR960026651A (ko) 퓨징 시스템
GB2252186B (en) Input buffer circuit,input/output buffer circuit and portable semiconductor storage
SE9900887D0 (sv) Krypteringsanordning
KR960025124A (ko) 클럭 버퍼링 회로
KR920018566A (ko) 정보처리장치
KR970076207A (ko) 마이크로프로세서(Micro-Procesor)의 입력단 회로
KR970068363A (ko) 브이. 엠. 이. 보드의 데이타 전송 장치

Legal Events

Date Code Title Description
NUG Patent has lapsed