DE69531597D1 - Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis - Google Patents
Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreisInfo
- Publication number
- DE69531597D1 DE69531597D1 DE69531597T DE69531597T DE69531597D1 DE 69531597 D1 DE69531597 D1 DE 69531597D1 DE 69531597 T DE69531597 T DE 69531597T DE 69531597 T DE69531597 T DE 69531597T DE 69531597 D1 DE69531597 D1 DE 69531597D1
- Authority
- DE
- Germany
- Prior art keywords
- flipflop
- electronic circuit
- test method
- comprehensive electronic
- iddq
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
- G01R31/3008—Quiescent current [IDDQ] test or leakage current test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318577—AC testing, e.g. current testing, burn-in
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94201929 | 1994-07-05 | ||
EP94201929A EP0633530B1 (de) | 1993-07-09 | 1994-07-05 | Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung |
EP95200212 | 1995-01-30 | ||
EP95200212 | 1995-01-30 | ||
PCT/IB1995/000527 WO1996001434A1 (en) | 1994-07-05 | 1995-06-29 | A method of testing and an electronic circuit comprising a flipflop with a master and a slave |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69531597D1 true DE69531597D1 (de) | 2003-10-02 |
DE69531597T2 DE69531597T2 (de) | 2004-06-24 |
Family
ID=27235995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69531597T Expired - Fee Related DE69531597T2 (de) | 1994-07-05 | 1995-06-29 | Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis |
Country Status (8)
Country | Link |
---|---|
US (1) | US6445235B1 (de) |
EP (1) | EP0717851B1 (de) |
JP (1) | JP3626757B2 (de) |
KR (1) | KR100495456B1 (de) |
CN (1) | CN1076479C (de) |
DE (1) | DE69531597T2 (de) |
TW (1) | TW281726B (de) |
WO (1) | WO1996001434A1 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5907080A (en) * | 1995-11-30 | 1999-05-25 | Nexia Biotechnologies, Inc. | Method for development of transgenic dwarf goats |
JP3614125B2 (ja) * | 2000-10-23 | 2005-01-26 | 三星電子株式会社 | Cpフリップフロップ |
US6919875B2 (en) * | 2001-10-02 | 2005-07-19 | Rohm Co., Ltd. | Flip-flop circuit, shift register and scan driving circuit for display device |
TW200535857A (en) * | 2004-04-20 | 2005-11-01 | Innolux Display Corp | Dynamic shift register |
US20060013352A1 (en) * | 2004-07-13 | 2006-01-19 | Ching-Wei Lin | Shift register and flat panel display apparatus using the same |
US7262648B2 (en) * | 2004-08-03 | 2007-08-28 | Marvell International Ltd. | Two-latch clocked-LSSD flip-flop |
JP2006217540A (ja) * | 2005-02-07 | 2006-08-17 | Fujitsu Ltd | 半導体集積回路および半導体集積回路の制御方法 |
WO2007148156A1 (en) * | 2006-06-20 | 2007-12-27 | Freescale Semiconductor, Inc. | Device and method for hadling metastable signals |
US7764086B2 (en) * | 2006-12-22 | 2010-07-27 | Industrial Technology Research Institute | Buffer circuit |
KR101136936B1 (ko) * | 2009-10-26 | 2012-04-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 동작방법 |
CN101706554B (zh) * | 2009-11-02 | 2012-03-14 | 中国科学院计算技术研究所 | 用于部分增强型扫描时延测试的触发器选择方法及*** |
US8514000B1 (en) * | 2012-07-31 | 2013-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Meta-hardened flip-flop |
CN105092930B (zh) * | 2014-05-06 | 2020-10-30 | 恩智浦美国有限公司 | 片上电流测试电路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE30173E (en) * | 1977-02-14 | 1979-12-18 | Rca Corporation | Current mirror amplifier |
DE3443788C2 (de) * | 1984-11-30 | 1987-01-08 | Siemens AG, 1000 Berlin und 8000 München | Taktgesteuerte Master-Slave-Kippschaltung |
JPS6295016A (ja) * | 1985-10-21 | 1987-05-01 | Mitsubishi Electric Corp | ラツチ回路 |
JPH0654860B2 (ja) * | 1987-09-30 | 1994-07-20 | ローム株式会社 | フリップフロップ回路 |
NL8900050A (nl) * | 1989-01-10 | 1990-08-01 | Philips Nv | Inrichting voor het meten van een ruststroom van een geintegreerde monolitische digitale schakeling, geintegreerde monolitische digitale schakeling voorzien van een dergelijke inrichting en testapparaat voorzien van een dergelijke inrichting. |
JP2621993B2 (ja) * | 1989-09-05 | 1997-06-18 | 株式会社東芝 | フリップフロップ回路 |
JPH03201717A (ja) * | 1989-12-28 | 1991-09-03 | Mitsubishi Electric Corp | フリップフロップ回路 |
JPH04167612A (ja) * | 1990-10-26 | 1992-06-15 | Seiko Epson Corp | フリップフロップ回路 |
JPH04246908A (ja) * | 1991-02-01 | 1992-09-02 | Nec Corp | フリップフロップ回路 |
JPH04263510A (ja) * | 1991-02-18 | 1992-09-18 | Nec Corp | フリップフロップ回路 |
TW222725B (en) * | 1993-07-09 | 1994-04-21 | Philips Electronics Nv | Testing sequential logic circuit upon changing into combinatorial logic circuit |
-
1995
- 1995-06-29 TW TW084106702A patent/TW281726B/zh active
- 1995-06-29 EP EP95921948A patent/EP0717851B1/de not_active Expired - Lifetime
- 1995-06-29 WO PCT/IB1995/000527 patent/WO1996001434A1/en active IP Right Grant
- 1995-06-29 DE DE69531597T patent/DE69531597T2/de not_active Expired - Fee Related
- 1995-06-29 CN CN95190769A patent/CN1076479C/zh not_active Expired - Fee Related
- 1995-06-29 JP JP50376496A patent/JP3626757B2/ja not_active Expired - Fee Related
- 1995-06-29 KR KR1019960701104A patent/KR100495456B1/ko not_active IP Right Cessation
- 1995-07-05 US US08/498,549 patent/US6445235B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69531597T2 (de) | 2004-06-24 |
EP0717851A1 (de) | 1996-06-26 |
JPH09502808A (ja) | 1997-03-18 |
CN1076479C (zh) | 2001-12-19 |
JP3626757B2 (ja) | 2005-03-09 |
CN1131985A (zh) | 1996-09-25 |
EP0717851B1 (de) | 2003-08-27 |
WO1996001434A1 (en) | 1996-01-18 |
KR960705220A (ko) | 1996-10-09 |
US6445235B1 (en) | 2002-09-03 |
TW281726B (de) | 1996-07-21 |
KR100495456B1 (ko) | 2005-09-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |
|
8339 | Ceased/non-payment of the annual fee |