SE9203882L - Sätt och anordning för minimering av scew - Google Patents

Sätt och anordning för minimering av scew

Info

Publication number
SE9203882L
SE9203882L SE9203882A SE9203882A SE9203882L SE 9203882 L SE9203882 L SE 9203882L SE 9203882 A SE9203882 A SE 9203882A SE 9203882 A SE9203882 A SE 9203882A SE 9203882 L SE9203882 L SE 9203882L
Authority
SE
Sweden
Prior art keywords
delta
buffer units
driver circuits
delayed
buffer
Prior art date
Application number
SE9203882A
Other languages
English (en)
Swedish (sv)
Other versions
SE9203882D0 (sv
Inventor
Per Anders Holmberg
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9203882A priority Critical patent/SE9203882L/
Publication of SE9203882D0 publication Critical patent/SE9203882D0/xx
Priority to MX9307973A priority patent/MX9307973A/es
Priority to JP6515082A priority patent/JPH08504986A/ja
Priority to PCT/SE1993/001088 priority patent/WO1994015398A1/en
Priority to EP94903213A priority patent/EP0676101A1/en
Priority to BR9307709-2A priority patent/BR9307709A/pt
Priority to AU57239/94A priority patent/AU693774B2/en
Priority to US08/170,879 priority patent/US5469477A/en
Priority to CN93119962A priority patent/CN1040585C/zh
Publication of SE9203882L publication Critical patent/SE9203882L/
Priority to FI953102A priority patent/FI953102A0/fi
Priority to NO952481A priority patent/NO952481L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Automobile Manufacture Line, Endless Track Vehicle, Trailer (AREA)
  • Dc Digital Transmission (AREA)
  • Analogue/Digital Conversion (AREA)
SE9203882A 1992-12-22 1992-12-22 Sätt och anordning för minimering av scew SE9203882L (sv)

Priority Applications (11)

Application Number Priority Date Filing Date Title
SE9203882A SE9203882L (sv) 1992-12-22 1992-12-22 Sätt och anordning för minimering av scew
MX9307973A MX9307973A (es) 1992-12-22 1993-12-15 Metodo y arreglo para disminuir la asimetria.
AU57239/94A AU693774B2 (en) 1992-12-22 1993-12-17 Method and device for minimizing skew
EP94903213A EP0676101A1 (en) 1992-12-22 1993-12-17 Method and device for minimizing skew
PCT/SE1993/001088 WO1994015398A1 (en) 1992-12-22 1993-12-17 Method and device for minimizing skew
JP6515082A JPH08504986A (ja) 1992-12-22 1993-12-17 スキューを最少とするための方法並びに装置
BR9307709-2A BR9307709A (pt) 1992-12-22 1993-12-17 Processo e aparelho para minimizar distorção em sistemas digitais sìncronos
US08/170,879 US5469477A (en) 1992-12-22 1993-12-21 Method and arrangement for minimizing skew
CN93119962A CN1040585C (zh) 1992-12-22 1993-12-22 一种用于将时滞降低到最小的方法和装置
FI953102A FI953102A0 (fi) 1992-12-22 1995-06-21 Menetelmä ja laite vinovääristymien minimointia varten
NO952481A NO952481L (no) 1992-12-22 1995-06-21 Fremgangsmåte og innretning ved minimering av synkroniseringsavvik

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9203882A SE9203882L (sv) 1992-12-22 1992-12-22 Sätt och anordning för minimering av scew

Publications (2)

Publication Number Publication Date
SE9203882D0 SE9203882D0 (sv) 1992-12-22
SE9203882L true SE9203882L (sv) 1994-06-23

Family

ID=20388227

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9203882A SE9203882L (sv) 1992-12-22 1992-12-22 Sätt och anordning för minimering av scew

Country Status (11)

Country Link
US (1) US5469477A ( )
EP (1) EP0676101A1 ( )
JP (1) JPH08504986A ( )
CN (1) CN1040585C ( )
AU (1) AU693774B2 ( )
BR (1) BR9307709A ( )
FI (1) FI953102A0 ( )
MX (1) MX9307973A ( )
NO (1) NO952481L ( )
SE (1) SE9203882L ( )
WO (1) WO1994015398A1 ( )

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727021A (en) * 1996-04-03 1998-03-10 Teradyne, Inc. Apparatus and method for providing a programmable delay with low fixed delay

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2073467A (en) * 1980-03-17 1981-10-14 Ainsworth Nominees Pty Ltd Gaming or amusement machines
US4782253A (en) * 1984-02-15 1988-11-01 American Telephone & Telegraph Company, At&T Bell Laboratories High speed MOS circuits
US4833695A (en) * 1987-09-08 1989-05-23 Tektronix, Inc. Apparatus for skew compensating signals
US4860322A (en) * 1988-10-05 1989-08-22 Intel Corporation Anti-clock skew distribution apparatus
US5163068A (en) * 1991-02-22 1992-11-10 El Amawy Ahmed Arbitrarily large clock networks with constant skew bound
GB2478126A (en) * 2010-02-25 2011-08-31 Vodafone Intellectual Property Licensing Ltd Analysing missed call events based on called mobile terminal status

Also Published As

Publication number Publication date
US5469477A (en) 1995-11-21
WO1994015398A1 (en) 1994-07-07
NO952481D0 (no) 1995-06-21
AU693774B2 (en) 1998-07-09
FI953102A (fi) 1995-06-21
FI953102A0 (fi) 1995-06-21
JPH08504986A (ja) 1996-05-28
AU5723994A (en) 1994-07-19
NO952481L (no) 1995-08-11
BR9307709A (pt) 1999-08-31
CN1093180A (zh) 1994-10-05
EP0676101A1 (en) 1995-10-11
CN1040585C (zh) 1998-11-04
MX9307973A (es) 1994-08-31
SE9203882D0 (sv) 1992-12-22

Similar Documents

Publication Publication Date Title
TW347639B (en) System and method for processing video data
US3072855A (en) Interference removal device with revertive and progressive gating means for setting desired signal pattern
MY112993A (en) Clock re-timing apparatus with cascaded delay stages
FR2371105A1 (fr) Compensateur electronique de defauts de signaux
KR900019352A (ko) 디지탈 볼륨의 열화방지회로
EP0111262A3 (en) Output multiplexer having one gate delay
SE9203882L (sv) Sätt och anordning för minimering av scew
AU601500B2 (en) A tone control system for sampled data signals
GB1366472A (en) Phasesynchronising device
CA2108725A1 (en) Expansible High Speed Digital Multiplexer
KR950010618A (ko) 샘플링 비율 변환 시스템
US3614776A (en) Pulse synchronization for digital to analog converters
JPS5685127A (en) Digital signal processor
CA2070811A1 (en) Waveshaping transversal filter and method utilizing the same for data transmission over coaxial cable
US4032720A (en) Integrated demultiplexing circuit with continuously variable outputs
RU1830527C (ru) Устройство дл синхронизации вычислительной системы
JPS596620A (ja) デイジタル信号多重化装置
KR940020729A (ko) 디지탈 오디오 적외선 수신기의 에러처리 회로
KR880014469A (ko) 비트순차 신호 스케일링 장치
JPS6449977A (en) Peak value detecting circuit
JPS6446323A (en) Analog/digital converter
SU1485413A1 (ru) Преобразователь кодов
JPS6120424A (ja) 論理回路
JPS57556A (en) Digital amplitude detecting circuit
JPS5566131A (en) Integrated circuit

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 9203882-7