SE8200314L - MODULE BUILT, DECENTRALIZED DATA PROCESSING SYSTEM - Google Patents

MODULE BUILT, DECENTRALIZED DATA PROCESSING SYSTEM

Info

Publication number
SE8200314L
SE8200314L SE8200314A SE8200314A SE8200314L SE 8200314 L SE8200314 L SE 8200314L SE 8200314 A SE8200314 A SE 8200314A SE 8200314 A SE8200314 A SE 8200314A SE 8200314 L SE8200314 L SE 8200314L
Authority
SE
Sweden
Prior art keywords
module
modules
data processing
processing system
bus
Prior art date
Application number
SE8200314A
Other languages
Swedish (sv)
Inventor
A Meyer
W Zucker
Original Assignee
Stollmann & Co Gmbh
Triumph Adler Buero Inf
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stollmann & Co Gmbh, Triumph Adler Buero Inf filed Critical Stollmann & Co Gmbh
Publication of SE8200314L publication Critical patent/SE8200314L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)

Abstract

The system consists of any desired number of independent computer modules (2) with equal priority and independent periphery modules (3) with equal priority, wherein a processor (5) with a local bus and store is contained in each module (2, 3). The computer modules (2) which can work out user and service programs independently by interpreting at least one program language and the periphery modules (3) which can execute independently input-output instructions, or instruction chains are operated together with a general store (4) on common asynchronous bus (1). Operations are divided between the modules (2, 3) so that each module (2, 3) contains only that instruction which it needs to fulfil its special function. Tasks which one module (2, 3) cannot perform itself are passed on via the bus, to a module (2, 3) which is specialized for the purpose. Thus both in the hardware construction and in the operating system, a modular data processing system is afforded which can be extended as desired without alteration or adaptation of the operating system. <IMAGE>
SE8200314A 1981-03-31 1982-01-20 MODULE BUILT, DECENTRALIZED DATA PROCESSING SYSTEM SE8200314L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813112693 DE3112693A1 (en) 1981-03-31 1981-03-31 MODULAR DECENTRALIZED DATA PROCESSING SYSTEM

Publications (1)

Publication Number Publication Date
SE8200314L true SE8200314L (en) 1982-10-01

Family

ID=6128793

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8200314A SE8200314L (en) 1981-03-31 1982-01-20 MODULE BUILT, DECENTRALIZED DATA PROCESSING SYSTEM

Country Status (7)

Country Link
JP (1) JPS57209561A (en)
DE (1) DE3112693A1 (en)
FR (1) FR2503420A1 (en)
GB (1) GB2096369A (en)
IT (1) IT1140489B (en)
NL (1) NL8104891A (en)
SE (1) SE8200314L (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538140B1 (en) * 1982-12-21 1988-06-24 Thomson Csf Mat Tel BUS COUPLING DEVICE FOR MULTIPLE BUS DATA PROCESSING SYSTEM
ATE74675T1 (en) * 1983-04-25 1992-04-15 Cray Research Inc MULTIPROCESSOR CONTROL FOR VECTOR COMPUTERS.
US4814983A (en) * 1984-03-28 1989-03-21 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4751637A (en) * 1984-03-28 1988-06-14 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system
GB2195038A (en) * 1986-07-05 1988-03-23 Narayanaswamy D Jayaram A multi-microprocessor system with confederate processors
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
GB2433396B (en) 2005-12-15 2010-06-23 Bridgeworks Ltd A bridge

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1287657A (en) * 1969-07-09 1972-09-06 Burroughs Corp Apparatus for signalling peripheral unit configuration within computer system
US3662401A (en) * 1970-09-23 1972-05-09 Collins Radio Co Method of program execution
US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system
US4257099A (en) * 1975-10-14 1981-03-17 Texas Instruments Incorporated Communication bus coupler
GB1561962A (en) * 1977-04-29 1980-03-05 Int Computers Ltd Data processing systems
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
JPS5840214B2 (en) * 1979-06-26 1983-09-03 株式会社東芝 computer system

Also Published As

Publication number Publication date
IT8124991A0 (en) 1981-11-12
GB2096369A (en) 1982-10-13
NL8104891A (en) 1982-10-18
DE3112693A1 (en) 1982-10-14
IT1140489B (en) 1986-09-24
JPS57209561A (en) 1982-12-22
FR2503420A1 (en) 1982-10-08

Similar Documents

Publication Publication Date Title
EP0255186A3 (en) System and method for parallel processing with mostly functional languages
MY105754A (en) Tightly coupled multiprocessor instruction synchronization.
ATE161980T1 (en) SYSTEM FOR OPERATING APPLICATION SOFTWARE IN A SAFETY-CRITICAL ENVIRONMENT
NL186939C (en) TELECOMMUNICATIONS CONNECTION PLAN, CONTROLLED BY A CONFIGURATION OF MUTELY CONNECTED UNITS INCLUDING EACH PROGRAM-CONTROLLED PROCESSOR.
FR2445555B1 (en) CENTRAL COMPUTER UNIT WITH OPERATION CODE EXTENSION REGISTER
DE3687724D1 (en) DIGITAL PROCESSOR CONTROL.
AU585076B2 (en) Interrupt handling in a multiprocessor computing system
SE8200314L (en) MODULE BUILT, DECENTRALIZED DATA PROCESSING SYSTEM
DK9981A (en) TRANSFER MACHINE - UNIVERSAL COMPUTER
CA2019299A1 (en) Multiprocessor system with multiple instruction sources
DE69113639D1 (en) REAL-TIME INPUT / OUTPUT METHOD FOR A VECTOR PROCESSOR SYSTEM.
EP0049521A3 (en) Information processing system
JPS6472237A (en) Address calculation system
JPS57141756A (en) Program processor
AU6446386A (en) Multiprocessor data processing system
JPS57113144A (en) Stored program computer
GRUENEWALD Modular programming for multicomputer systems
JPS54139445A (en) Composite computer system
JPH025104A (en) Arithmetic processing unit
JPS5518720A (en) Multiple computer system
JPS556602A (en) Multiprocessor system
Grierson Perspectives in simulation hardware and software architecture
Shrimpton An implementation of MIL-STD-1750 airborne computer instruction set architecture
d'Epinay Development of the New Real-Time Operating System “CHA-OS” at the Federal Institute of Technology, Zürich
WO1994015280A3 (en) Computer architecture for parallel data transfer in declarative computer languages

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 8200314-6

Effective date: 19880415

Format of ref document f/p: F