GB1561962A - Data processing systems - Google Patents

Data processing systems Download PDF

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Publication number
GB1561962A
GB1561962A GB17922/77A GB1792277A GB1561962A GB 1561962 A GB1561962 A GB 1561962A GB 17922/77 A GB17922/77 A GB 17922/77A GB 1792277 A GB1792277 A GB 1792277A GB 1561962 A GB1561962 A GB 1561962A
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Prior art keywords
coupler
highway
message
couplers
store
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GB17922/77A
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Fujitsu Services Ltd
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Fujitsu Services Ltd
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Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB17922/77A priority Critical patent/GB1561962A/en
Priority to ZA00782032A priority patent/ZA782032B/en
Priority to DE2815716A priority patent/DE2815716C2/en
Priority to AU35289/78A priority patent/AU513777B2/en
Priority to FR7812757A priority patent/FR2389176B1/en
Publication of GB1561962A publication Critical patent/GB1561962A/en
Expired legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607Interleaved addressing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/4045Coupling between buses using bus bridges where the bus bridge performs an extender function

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

(54) IMPROVEMENTS IN OR RELATING TO DATA PROCESSING SYSTEMS (71) We, INTERNATIONAL COMPUTERS LIMITED, a British Company, of ICL House, Putney, London, S.W.15, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: INTRODUCTION This invention relates to data processing systems.
A data processing system generally comprises a number of functional units such as data processing units, data storage units and peripheral devices. It has been proposed to connect these units together by means of a message exchange comprising a data highway to which the functional units are attached by way of devices referred to herein as couplers. When a coupler has a message to send over the highway, it sends a request to a highway control unit which responds by granting the coupler the use of the highway. (If more than one request is received simultaneously, the highway control unit arbitrates between them so as to ensure that only one coupler is allowed to use the highway at any given time). The coupler which is granted the use of the highway then broadcasts its message over the highway to all the other couplers. Each coupler compares the destination address contained within the message with its own address and accepts the message from the highway if the two addresses are equal.
One problem with such a system is that when a message is on the highway, the next message cannot be sent until the couplers have had sufficient time to compare the destination address of the first message with their own addresses.
Since comparison is a relatively slow operation, this restricts the rate at which messages can be sent over the highway.
One obiect of the invention is to avoid this problem and therefore increase the rate at which messages can be sent.
SUMMARY OF THE INVENTION According to the invention there is provided a data processing system comprising a plurality of functional units and a message exchange for conveying messages between the functional units, each message including a coded destination address specifying the intended destination of the message, wherein the message exchange comprises a data highway, a plurality of couplers connecting respective functional units to the highway, and a highway control unit arranged to receive request signals from the couplers and to respond to each such request signal in turn by sending a control signal to the coupler which issued the request signal, granting that coupler the use of the highway, wherein each coupler is so arranged that when it has a message to send to another coupler it sends a request signal to the highway control unit, and, while it is waiting for a control signal granting it the use of the highway, decodes the destination address of the message and then, when it receives the control signal, places the message on the highway and at the same time utilises the decoded destination address to send a select signal to the coupler specified by the decoded address, each coupler having a separate select line to each other coupler for this purpose, and wherein each coupler is so arranged that when it receives a select signal from another coupler it accepts the message which that other coupler has placed on the highway if it is free to do so.
It can be seen that since the destination coupler is selected by a signal from the source coupler, it is not necessary for each coupler to compare the destination addresses of every message on the highway with its own address in order to decide whether or not to accept the message. Thus, the delay introduced by such a comparison is avoided.
(Of course, the destination coupler may perform such a comparison, as a check, after it has accepted the message, but this need not delay the transmission of the next message). Moreover the decoding of the destination address within the source coupler is overlapped with the request to the highway control unit, which reduces or eliminates the delay involved in this decoding.
BRIEF DESCRIPTION OF THE DRAW INGS One embodiment of the invention will now be described, by way of example, with reference to the drawings filed with the Provisional Specification of which: Figure 1 is a block diagram showing a data processing system including a message exchange in accordance with the invention; Figure 2 shows a processor coupler; Figure 3 shows a buffer control circuit; Figure 4 shows a store coupler; and Figure 5 shows parts of two interlinked transfer couplers.
OVERALL WEW OF SYSTEM Referring to Figure 1, the system comprises a plurality of functional units including one or more processors 1, a plurality of store units 2, and a plurality of device control units 3. The device control units are connected to peripheral devices 4.
These functional units are interconnected by a message exchange 5 which operates as a store-and-forward transmission system, capable of receiving a message from any of the functional units and steering that message to the required destination without alteration. The message exchange is thus completely transparent to the rest of the system.
All functional communication between the functional units takes place by exchange of messages in this way: there are no direct wiring connections between the units.
Thus for example, if a processor wishes to read an item of data, it sends a read request message to the store unit which holds that item. The store unit will respond by retrieving the item and sending it to the processor as a data returned message. Interrupts and activations are also sent as messages.
Every functional unit which originates a message will expect a reply, either data or simply an acknowledgement.
Each functional unit is connected to the message exchange by means of a coupler, specific to the type of unit: processors are connected by means of processor couplers PC. storge units by store couplers SC, and device control units by channel couplers CC.
The message exchange contains one or more highways 6 (in the present example there are two highways) each having its own highway control unit 7. Each highway has a plurality of ports (in the present example, seven) into which couplers are plugged.
Any coupler can be plugged into any port; the only significance of the particular ports is that their ordering determines the order of priority for use of the highway.
As shown, the highways are joined by a pair of transfer couplers TC which are connected together by a link 8. The use of transfer couplers allows extended systems to be constructed, using several highways.
Every message within the exchange carries a six-bit destination port number DPN which specifies the port to which the message must be routed. The first three bits of this number define which highway the destination port is on, and the other three bits define the position of the destination port on that highway.
Each message is automatically tagged at this point of entry into the exchange, with a six-bit source port number SPN which can be used by the recipient if a reply is expected.
DATA HIGHWAY Each data highway is wide enough to carry a complete message in parallel, and includes the following lines: (a) 64 data lines, which carry a bit data word.
(b) 24 Address lines. The first six of these lines carry the destination port number DPN. The remaining 18 carry a word address, when required.
(c) 6 lines carry the source port number SPN.
(d) 12 message function lines carry a code specifying the function of the message (i.e. whether it is a request or a re ponse to a request; if it is a request, whether it is for a read or a write, and so on).
The highway also includes parity lines for parity bits associated with all the above fields. All the highway lines are bidirectional.
MESSAGE ROUTING Messages are steered through the exchange, using the destination port number DPN contained within the message. Where the destination coupler is connected to the same highway as the source coupler the message is transferred to the destination coupler in a single highway operation. However, if the source and destination couplers are attached to different highways, the message has to be routed through the transfer couplers interconnecting the highways. In an extended system including several highways, a message might be steered through several successive transfer couplers before reaching its eventual destination.
Steering of messages through the exchange is controlled by tables set up within each coupler (with the exception of the store couplers). Each steering table has sixty-four entries, indexed by the destination port number DPN of the message, each entry con sisting of a three-bit exit code, which identifies the exit coupler to which the message has to be steered. This exit coupler will either be the actual destination coupler or a transfer coupler through which the message has to be routed to reach the destination coupler.
The steering tables are all writable, thus facilitating reconfiguration of the system.
Since there are only seven ports on each highway, only seven of the exit codes (i.e.
codes e6) are valid. The remaining code (7) is used as a dummy, and is ignored by the coupler.
MESSAGE CONTROL When a coupler has a message which it wishes to place on the highway, it sends a highway request signal HR to the highway control. Each coupler has a separate request line to the highway control for this purpose.
In parallel with this, the coupler indexes its steering table with the destination port number DPN of the message, to find the identity of the exit coupler to which the message must be steered.
When the highway control receives a request HR, it sends a highway busy signal HB to all the couplers on the highway, to warn them of the possibility of receiving a message. The highway control then sends a highway control signal HC to the coupler which made the request, there being a separate control line to each coupler for this purpose. If several couplers are contending for this highway simultaneously, the requests are serviced in order of priority, only one control signal HC being issued at a time.
The duration of the highway control signal HC defines a time slot allocated to the coupler for use of the highway.
When the coupler receives the highway control signal HC, it places its message on the highway, and at the same time sends a coupler select signal CS to the exit coupler (whose identity was found from the steering table). Each coupler has seven select lines leading respectively to the seven couplers on the highway, including itself.
(Thus, a coupler can select itself as the exit coupler, which is useful for diagnostic selftesting). The highway control then issues a highway timing signal HT to all the couplers, which causes the message to be strobed into the selected exit coupler.
The exit coupler produces a coupler accept signal CA to indicate that it has received the message. This signal is broadcast over a single line to all the couplers on the highway. The coupler which sent + message will respond to this accept signal by removing its request HR.
If for any reason the selected exit coupler is unable to receive the message (for example, if its buffer is full) no acceDt signal CA is produced. If the source coupler does not see an accept signal within the time slot- allocated to it, it will maintain its request HR, so as to initiate a further attempt to transmit the message. However, to stop -any coupler monopolishing the highway, no coupler is allowed to use the highway in two successive time slots.
PROCESSOR COUPLER Referring now to Figure 2, this shows one of the processor couplers PC in more detail.
Messages are received from the attached processor through a receiving circuit RX and stored in a first message buffer 20.
Messages received from the highway 6 are stored in a second message buffer 21 and transmitted to the processor through a line driving circuit TX.
When the processor has a message to send, it issues a request signal REQ which strobes the message into the buffer 20 and sets a request bistable 22, causing a highway request signal HR to be sent to the highway control. While this coupler is waiting for the request to be serviced, the destination port number DPN of the message is applied to the address input of a random access memory (RAM) 23 which holds the steering table for this coupler, so as to obtain the three-bit exit code identifying the exit coupler. This is decoded by a decoder 24 to produce a signal on one of seven output lines, depending on the identity of the exit coupler. (The dummy code "7" produces no output from the decoder).
When the coupler receives the highway control signal HC, the message in the buffer 20 is gated on to the highway 6, and at the same time the output of the decoder 24 is gated on to the coupler select lines, so as to send a coupler sheet signal CS to the exit coupler. At the same time, the port number PN of the source coupler (which is hardwired into it) is gated on to the SPN lines of the highway, so as to tag the message with an indication of its source.
If the coupler receives an accept signal CA within the time slot allocated to it (i.e. while HC is still present) the request bistable 22 is reset and HR is removed.
Referring now to Figure 3, this shows the circuit which controls entry of messages into the buffer 21 from the highway.
A bistable 30 indicates whether the buffer 21 is free or busy and a second bistable 31 indicates whether the buffer is primed or unprimed. Assuming that the buffer 21 is free, the bistable 31 will be set to its "primed" state upon receipt of a highway busy signal HB from the highway control.
An AND gate 32 is therefore enabled, permitting a STROBE signal to be generated for strobing the message into the buffer 21.
The STROBE signal is generated by the highway timing signal HT, provided that a coupler select signal CS is present on any of the seven incoming coupler select lines to this coupler.
The STROBE signal resets both the bistables 30, 31 to their "busy" and "unprimed" states respectively, and also generates an accept signal CA which is broadcast to all the couplers.
Referring again to Figure 2, the destination port number DPN in the received message is compared, in a comparator 26, with the hard-wired port number of the coupler. If these numbers are not equal, a system error is present, and an appropriate warning is generated.
The processor can now read the contents of the buffer 21, and when it has done so sends a RELEASE signal to the buffer control, which unsets the bistable 30 to show that it is once more free. (However, it is not primed to receive another message until the next highway busy signal HB).
STORE COUPLER Referring now to Figure 4, the store coupler SC is very similar to the processor coupler, except that it does not have a steering RAM 23; instead it has a register 40 which stores the source port number SPN of the incoming message, and subsequently uses this as the destination port number DPN of the reply message. The reason for this is that the store coupler never originates any requests, but only replies to requests from other couplers.
CHANNEL COUPLER The channel coupler CC may be of similar form to the processor coupler and it will therefore not be described further.
TRANSFER COUPLER A transfer coupler TC consists of a receiving section and a transmitting section.
Referring to Figure 5, this shows the transmitting section of one transfer coupler (referred to as coupler A) connected to a first highway A, and the receiving section of another transfer coupler B, connected to a second highway B, the two sections forming a path for transfer of messages from highway A to highway B. It will be appreciated that the couplers also include corresponding sections for transferring messages in the reverse direction from highway B to highway A.
Messages travelling from highway A to highway B pass from highway A into a buffer 50 in coupler A and are transmitted by a line driver TX to a receiver RX in coupler, where they are stored in a buffer 52 before being placed on highway B.
The buffer 50 has a buffer control circuit 51 similar to that shown in Figure 3, for controlling the entry of data into the buffer from highway A.
The buffer 52 has a bistable 53 which indicates whether or not this buffer is free.
The output of this bistable 53 is transmitted to transfer coupler A as a buffer register free signal BRF.
In coupler A, the signal BRF is combined in an AND Gate 54 with the BUSY output from the control circuit 51 to produce a transfer signal TRAN only if the buffer 50 is full and at the same time the buffer 52 is free.
The signal TRAN is sent to coupler B where it strobes the message from line 51 into the buffer 52, and sets the bistable 53 to the busy state. TRAN also sets a bistable 55 in coupler A producing a request signal REQ which is sent to coupler. This initiates a request HR to the highway control of highway B. The TRAN signal is also applied to the control circuit 51 as a RELEASE signal, which releases the buffer 50 so that it can accept another message from highway A.
When the bistable 53 is set, the signal BRF becomes false, and the AND gate 54 is therefore disabled, terminating the TRAN signal.
The procedure following a request signal HR to the highway control is the same as that described above in the case of the processor coupler. Tht highway control allocates a time slot to transfer coupler B, by sending it a control signal HC. This causes the message to be placed on highway B, and a coupler select signal CS to be sent to the destination coupler. (The CS signal is produced, as in the processor coupler, by a random access memory 56, and a decoder 57).
When the destination coupler accepts with a CA signal, the bistable 53 is reset to indi- cate than the buffer 52 is now free. The accept signal CA is also transmitted back to coupler A, as an accept signal ACC which resets the request bistable 55.
It can be seen that two messages can be queued in the transfer couplers for transfers from highway A to highway B. Similarly, a further two messages can be queued in the- opposite direction.
MESSAGE BROADCASTING In the system shown in Figure 1, if the processor 1 were connected only to one highway 6, the time taken for the processor to access an item of information held in a store unit attached to the other highway would be relatively long, as a result of the extra delay in passing messages through the trans fer couplers TC. To avoid this, the processor 1 is provided with a connection 9 to a processor coupler PC on the second highway as well as the first highway. The processor 1 can therefore broadcast all requests to both highways.
The steering tables in the two Drocessor couplers are initialised in such a manner that, when either coupler receives a message whose destination port number DPN india cates that it is directed to a coupler on the other highway, the output of the steering table is the dummy code "7" which, as mentioned previously, is ignored by the coupler.
MEMORY INTERLEAVING The system provides the facility for interleaving the addressing of two separate store units 2, connected to different highways, such that words with even word addresses are allocated to one store unit and those with odd word addresses to the other store unit.
In this way, the pair of stores appears as one single store of twice the width of a single unit. The advantage of interleaving is that it permits the access times of the two stores to be overlapped when accessing a sequence of consecutive words.
The interleaved mode of operation is controlled by an interleave bistable in each coupler.
Referring to Figure 2, when the interleave bistable 25 is set in a processor coupler (or a channel coupler) the destination port number DPN applied to the steering table is modified by "ORing" the last bit of the word address (which denotes whether the word address is even or odd) on line 27 with the third bit of the destination port number DPN (which determines whether the destination port is on an even or odd numbered highway), this latter bit normally being set to zero by the originating processor in this mode of operation.
Thus the message will be steered to a different highway (and hence to a different store unit) according to whether the word address is even or odd.
Referring to Figure 4, when the interleave bistable 41 is set in a store coupler, each address presented to the coup]er from the highway is shifted to the right by one place (the last significant bit being discarded) before being sent to the store unit. This is to take account of the fact that the system is mapping logically interleaved addresses on to the physically continuous store.
WHAT WE CLAIM IS:- 1. A data processing system comprising a plurality of functional units and a message exchange for conveying messages between the functional units, each message including a coded destination address specifying the intended destination of the message, wherein the message exchange comprises a data highway, a plurality of couplers connecting respective functional units to the highway, and a highway controf unit arranged to receive request signals from the couplers and to respond to each such request signal in turn by sending a control signal to the coupler which issued the request signal, granting that coupler the use of the highway, wherein each coupler is so arranged that when it has a message to send to another coupler it sends a request signal to the highway control unit and, while it is waiting for a control signal granting it the use of the highway, decodes the destination address of the message and then, when it receives the control signal, places the message on the highway and at the same time utilises the decoded destination address to send a select signal to the coupler specified by the decoded address, each coupler having a separate select line to each other coupler for this purpose, and wherein each coupler is so arranged that when it receives a select signal from another coupler it accepts the message which that other coupler has placed on the highway if it is free to do so.
2. A system according to Claim 1 wherein each coupler is so arranged that when it accepts a message from the highway it broadcasts an accept signal to all the other couplers and the coupler which sent the message is arranged to respond to the accept signal by withdrawing its request signal to the control unit.
3. A system according to either preceding claim wherein the functional units comprise at least one processor unit and a plurality of store units, wherein each message sent by the processor unit to one of the store units includes a store address specifying a location within the store unit, and wherein the coupler which connects the processor unit to the highway is operable in an interleaving mode in which it modifies the destination address of each message from the processor to the store units in accordance with the value of at least one of the least significant digits of the store address of that message, such that messages with numerically adjacent store addresses are directed to different store units.
4. A system according to any preceding claim wherein each coupler is operative to automatically attach a coded source address to each message placed on the highway by the coupler, specifying the identity of that coupler.
5. A system according to any preceding claim in which each coupler is removably connected to the highway and in which the interfaces between the highway and the respective couplers are all identical, so that any coupler can be connected to any position on the highway.
6. A system according to any preceding claim wherein the highway control unit is so arranged that, if it receives simultaneous
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **.
1 can therefore broadcast all requests to both highways.
The steering tables in the two Drocessor couplers are initialised in such a manner that, when either coupler receives a message whose destination port number DPN india cates that it is directed to a coupler on the other highway, the output of the steering table is the dummy code "7" which, as mentioned previously, is ignored by the coupler.
MEMORY INTERLEAVING The system provides the facility for interleaving the addressing of two separate store units 2, connected to different highways, such that words with even word addresses are allocated to one store unit and those with odd word addresses to the other store unit.
In this way, the pair of stores appears as one single store of twice the width of a single unit. The advantage of interleaving is that it permits the access times of the two stores to be overlapped when accessing a sequence of consecutive words.
The interleaved mode of operation is controlled by an interleave bistable in each coupler.
Referring to Figure 2, when the interleave bistable 25 is set in a processor coupler (or a channel coupler) the destination port number DPN applied to the steering table is modified by "ORing" the last bit of the word address (which denotes whether the word address is even or odd) on line 27 with the third bit of the destination port number DPN (which determines whether the destination port is on an even or odd numbered highway), this latter bit normally being set to zero by the originating processor in this mode of operation.
Thus the message will be steered to a different highway (and hence to a different store unit) according to whether the word address is even or odd.
Referring to Figure 4, when the interleave bistable 41 is set in a store coupler, each address presented to the coup]er from the highway is shifted to the right by one place (the last significant bit being discarded) before being sent to the store unit. This is to take account of the fact that the system is mapping logically interleaved addresses on to the physically continuous store.
WHAT WE CLAIM IS:- 1. A data processing system comprising a plurality of functional units and a message exchange for conveying messages between the functional units, each message including a coded destination address specifying the intended destination of the message, wherein the message exchange comprises a data highway, a plurality of couplers connecting respective functional units to the highway, and a highway controf unit arranged to receive request signals from the couplers and to respond to each such request signal in turn by sending a control signal to the coupler which issued the request signal, granting that coupler the use of the highway, wherein each coupler is so arranged that when it has a message to send to another coupler it sends a request signal to the highway control unit and, while it is waiting for a control signal granting it the use of the highway, decodes the destination address of the message and then, when it receives the control signal, places the message on the highway and at the same time utilises the decoded destination address to send a select signal to the coupler specified by the decoded address, each coupler having a separate select line to each other coupler for this purpose, and wherein each coupler is so arranged that when it receives a select signal from another coupler it accepts the message which that other coupler has placed on the highway if it is free to do so.
2. A system according to Claim 1 wherein each coupler is so arranged that when it accepts a message from the highway it broadcasts an accept signal to all the other couplers and the coupler which sent the message is arranged to respond to the accept signal by withdrawing its request signal to the control unit.
3. A system according to either preceding claim wherein the functional units comprise at least one processor unit and a plurality of store units, wherein each message sent by the processor unit to one of the store units includes a store address specifying a location within the store unit, and wherein the coupler which connects the processor unit to the highway is operable in an interleaving mode in which it modifies the destination address of each message from the processor to the store units in accordance with the value of at least one of the least significant digits of the store address of that message, such that messages with numerically adjacent store addresses are directed to different store units.
4. A system according to any preceding claim wherein each coupler is operative to automatically attach a coded source address to each message placed on the highway by the coupler, specifying the identity of that coupler.
5. A system according to any preceding claim in which each coupler is removably connected to the highway and in which the interfaces between the highway and the respective couplers are all identical, so that any coupler can be connected to any position on the highway.
6. A system according to any preceding claim wherein the highway control unit is so arranged that, if it receives simultaneous
request signals from more than one coupler, it issues control signals to those couplers in a predetermined order of priority.
7. A system according to Claim 6 when dependent upon Claim 5 wherein said predetermined order of priority is determined by the positions to which the couplers are connected on the highway.
8. A system according to any preceding claim in which each coupler has a first buffer for holding a message for sending ta another coupler, and a second buffer for receiving a message accepted from the highway.
9. A data processing system comprising a plurality of functional units and a message exchange for conveying messages between the functional units, each message including a destination address specifying the intended destination of the message, wherein the message exchange comprises at least two data highways each having a plurality of functional unit couplers connecting respective functional units to it and each highway having at least one transfer coupler linked to another such transfer coupler on another highway to permit messages to be transferred between those highways, wherein each functional unit coupler and transfer coupler is so arranged that when it has a message to place on the highway to which it is connected, it translates the destination address of the message into an exit port number specifying which coupler connected to the same highway the message should be routed to in order to reach the intended destination, and then utilises this exit port number to route the message to that coupler, and wherein each transfer coupler is so arranged that when it receives a message from the highway to which it is connected, it transfers the message to the transfer coupler to which it is linked, the system being such that any functional unit coupler can send a message to any other functional unit coupler in the system, either directly over the highway connecting those couplers, if both couplers are connected to the same highway, or else by way of the appropriate transfer couplers, if the two functional unit couplers are connected to different highways.
10. A system according to Claim 9 wherein at least one of the functional units is connected to at least two different functional unit couplers which are connected to different highways, so that it can send the same message simultaneously to the two couplers, each of the two couplers being arranged to determine whether or not the destination address of the message relates to the same highway as that to which the coupler is attached and, if it does not, to ignore the message.
11. A data processing system substantially as hereinbefore described with refer- ence to the drawings filed with the Provisional Specification.
GB17922/77A 1977-04-29 1977-04-29 Data processing systems Expired GB1561962A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB17922/77A GB1561962A (en) 1977-04-29 1977-04-29 Data processing systems
ZA00782032A ZA782032B (en) 1977-04-29 1978-04-10 Improvements in or relating to data processing systems
DE2815716A DE2815716C2 (en) 1977-04-29 1978-04-12 Circuit arrangement for transmitting addressed digital information
AU35289/78A AU513777B2 (en) 1977-04-29 1978-04-20 Message exchange for data processors
FR7812757A FR2389176B1 (en) 1977-04-29 1978-04-28 DATA TRANSMISSION DEVICE

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AU (1) AU513777B2 (en)
DE (1) DE2815716C2 (en)
FR (1) FR2389176B1 (en)
GB (1) GB1561962A (en)
ZA (1) ZA782032B (en)

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* Cited by examiner, † Cited by third party
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WO2000055737A2 (en) * 1999-03-17 2000-09-21 Infineon Technologies Ag Multiplexer bus comprising local bus nodes

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FR2538140B1 (en) * 1982-12-21 1988-06-24 Thomson Csf Mat Tel BUS COUPLING DEVICE FOR MULTIPLE BUS DATA PROCESSING SYSTEM

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US3427588A (en) * 1967-06-29 1969-02-11 Bell Telephone Labor Inc Distribution of messages to data station receivers on multistation lines
DE2555737A1 (en) * 1975-12-11 1977-06-16 Standard Elektrik Lorenz Ag Multiple channel data transmission system - derives channel from coded address using two translations combined with data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000055737A2 (en) * 1999-03-17 2000-09-21 Infineon Technologies Ag Multiplexer bus comprising local bus nodes
WO2000055737A3 (en) * 1999-03-17 2001-02-22 Infineon Technologies Ag Multiplexer bus comprising local bus nodes
US7061933B2 (en) 1999-03-17 2006-06-13 Infineon Technologies Ag Multiplexer bus with local bus nodes

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AU3528978A (en) 1979-10-25
AU513777B2 (en) 1980-12-18
DE2815716C2 (en) 1985-05-02
ZA782032B (en) 1979-03-28
FR2389176B1 (en) 1986-05-23
DE2815716A1 (en) 1978-11-02
FR2389176A1 (en) 1978-11-24

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