SE538783C2 - SiC SUPER-JUNCTIONS - Google Patents

SiC SUPER-JUNCTIONS Download PDF

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Publication number
SE538783C2
SE538783C2 SE1550821A SE1550821A SE538783C2 SE 538783 C2 SE538783 C2 SE 538783C2 SE 1550821 A SE1550821 A SE 1550821A SE 1550821 A SE1550821 A SE 1550821A SE 538783 C2 SE538783 C2 SE 538783C2
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sic region
doped
super
doped sic
junction structure
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SE1550821A
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SE1550821A1 (sv
Inventor
Schöner Adolf
Vieider Christian
Reshanov Sergey
Kaplan Wlodzimierz
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Ascatron Ab
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Priority to SE1550821A priority Critical patent/SE538783C2/sv
Priority to EP16728959.4A priority patent/EP3311411A1/en
Priority to PCT/EP2016/063607 priority patent/WO2016202786A1/en
Publication of SE1550821A1 publication Critical patent/SE1550821A1/sv
Publication of SE538783C2 publication Critical patent/SE538783C2/sv

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Description

538 783
[0006] Thus it is a problem in the prior art that the doping in a super-junction structure becomes non-homogeneous.
Summary
[0007]|t is an object of the present invention to obviate at least some of the disadvantages in the prior art and provide an improved method to manufacture SiC epitaxially grown super-junction structures. The inventors have realized that in particular for epitaxially grown SiC super-junction structures it is possible to make a compensation in the doped material when adding material layer by layer based on an estimate.
[0008]ln a first aspect there is provided a super-junction structure manufactured with an epitaxy process and having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench, said at least one trench comprising one of i) the first doped SiC region and ii) the second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, wherein the density of dopants outside said at least one trench is adapted to the density of dopants in said at least one trench for a plurality of planes perpendicular to the growth direction of the epitaxy process to achieve charge compensation in each plane, wherein the charge compensation ß is less than 1 calculated according to the formula n(><)*An(X)=ß'1*D(X)*Ap(><) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, An(x) is the area of the first doped SiC region in a plane at depth x, 538 783 p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X. [0OO9]|n a second aspect there is provided a method of manufacturing a super- junction structure, said super-junction structure having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench comprising one of i) said first doped SiC region and ii) said second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, said method comprising the steps of: a. estimating the density of ionized dopants in the at least one trench of the super-junction structure to be manufactured, wherein the density of ionized dopants is estimated for a plurality of planes perpendicular to the growth direction of the epitaxy process, each plane corresponding to a depth (x) from the surface of the super-junction structure to be manufactured, b. growing at least one layer of doped SiC by epitaxy, wherein the SiC is doped, and wherein the density of ionized dopants is adapted for each depth of the growing material to achieve charge compensation in the plane corresponding to that depth, wherein the charge compensation ß is less than 'l calculated according to the formula fl(><)*An(><)=ß'“*p(><)*Ap(X) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, 538 783 An(x) is the area of the first doped SiC region in a plane at depth x, p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X, c. creating at least one trench in the at least one layer grown in step b), and d. filling the at least one trench created in step c) with epitaxial growth of one of i) the first doped SiC region and ii) the second doped SiC region.
[0010]Further aspects and embodiments are defined in the appended claims, which are specifically incorporated herein by reference.
[0011]One advantage is that an improved charge compensation can be achieved in a SiC epitaxially grown super-junction structure with an efficient manufacturing method.
Brief description of the drawinqs
[0012] The invention is now described, by way of example, with reference to the accompanying drawings, in which:
[0013] Fig. 1 shows a SiC epitaxially grown super-junction structure where it is shown that different regions p1, p2 and p3 have different orientation of the crystal growth planes during epitaxial growth which gives different dopant incorporation (density p1>p3>p2 of ionized dopants in one embodiment).
[0014] Fig. 2 shows the same epitaxially grown super-junction structure as in fig 1 where a dotted line indicates a plane perpendicular to the epitaxy growth direction. The area An of the first doped SiC region in the plane is indicated together with the area Ap of the second doped SiC region in the plane. The depth of the trench d is indicated on the x-axis. 538 783
[0015] Fig. 3 shows the area An(x) of the first doped SiC region as a function of X, the area Ap(x) of the second doped SiC region as a function of x, the ionized dopant density n(x) of the first doped SiC region as a function of x, and the ionized dopant density p(x) of the second doped SiC region as a function of x. The curve n(x) is adapted during manufacture to achieve charge compensation. The parameter x corresponds to the distance from the surface.
[0016] Fig 4 shows four different embodiments illustrating different manufacturing methods. ln embodiment A a first n-type doped SiC is added with epitaxial growth. This first SiC is intended to surround the trenches. After trench etching a second p-type doped SiC is added to the trenches. ln embodiment B the p- type and n-type material have changed place compared to embodiment A, the inverted embodiment. ln embodiment C a second doped p-type SiC is added with epitaxial growth. After trench etching a first n-type doped SiC is added to the trenches. The substrate is n-type doped. ln embodiment D the p-type and n-type material have changed place compared to embodiment C, the inverted embodiment.
Detailed description
[0017]Before the invention is disclosed and described in detail, it is to be understood that this invention is not limited to particular compounds, configurations, method steps, substrates, and materials disclosed herein as such compounds, configurations, method steps, substrates, and materials may vary somewhat. lt is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting since the scope of the present invention is limited only by the appended claims and equivalents thereof.
[0018]lt must be noted that, as used in this specification and the appended claims, the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise. 538 783
[0019]lf nothing else is defined, any terms and scientific terminology used herein are intended to have the meanings commonly understood by those of skill in the art to which this invention pertains.
[0020]The term “trench” as used in the description and the claims should be interpreted broadly so that also other types of recesses or holes are encompassed. Thus the principles of the invention are applicable to other recesses than trenches such as holes or well and similar.
[0021]Acceptor doped as used in the description and the claims should be interpreted as p-type doped whereas donor doped should be interpreted as n- type doped.
[0022]ln a first aspect there is provided a super-junction structure manufactured with an epitaxy process and having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench, said at least one trench comprising one of i) the first doped SiC region and ii) the second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, wherein the density of dopants outside said at least one trench is adapted to the density of dopants in said at least one trench for a plurality of planes perpendicular to the growth direction of the epitaxy process to achieve charge compensation in each plane, wherein the charge compensation ß is less than 1 calculated according to the formula fl(><)*^~(><)=ß'1*p(><)*^p(><) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, An(x) is the area of the first doped SiC region in a plane at depth x, 538 783 p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X.
[OO23]|n a second aspect there is provided a method of manufacturing a super- junction structure, said super-junction structure having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench comprising one of i) said first doped SiC region and ii) said second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, said method comprising the steps of: a. estimating the density of ionized dopants in the at least one trench of the super-junction structure to be manufactured, wherein the density of ionized dopants is estimated for a plurality of planes perpendicular to the growth direction of the epitaxy process, each plane corresponding to a depth (x) from the surface of the super-junction structure to be manufactured, b. growing at least one layer of doped SiC by epitaxy wherein the SiC is doped, and wherein the density of dopants is adapted for each depth of the growing material to achieve charge compensation in the plane corresponding to that depth, wherein the charge compensation ß is less than 1 calculated according to the formula fl(><)*An(><)=ß'“*p(><)*Ap(X) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, 538 783 An(x) is the area of the first doped SiC region in a plane at depth x, p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X, c. creating at least one trench in the at least one layer grown in step b), and d. filling the at least one trench created in step c) with epitaxial growth of one of i) the first doped SiC region and ii) the second doped SiC region.
[0024]When the ionized dopant density is estimated in step a) an exact determination of the ionized dopant density with high precision is not necessary. A skilled person realizes that the accuracy of the estimate is dependent on the required precision for the charge compensation ß. ln one embodiment it is sufficient to make an estimate within 110% of the true value.
[0025]|n one embodiment the estimate in step a) is performed using a theoretic calculation. A skilled person can make assumptions how the orientation of the growth planes in the growing SiC will be and use that as a starting point to calculate the charge density in the doped filled trenches. ln an alternative embodiment the estimate in step a) is performed by measurement. A filled trench can be manufactured and after appropriate slicing the dopant density can be measured and used to estimate the charge density for each plane.
[0026]|n one embodiment the first doped SiC region is donor-doped and wherein the second doped SiC region is acceptor-doped. ln an alternative embodiment the first doped SiC region is acceptor-doped and wherein the second doped SiC region is donor-doped.
[0027]|n one embodiment the at least one trench in step c) is created by etching. 538 783
[0028]|n one embodiment the charge compensation ß is at least 0.75.
[0029]|t should be noted that in the formula n(x)*An(x)=ß-1*p(x)*Ap(x) the density of ionized dopants in the first doped SiC region, the area of the first doped SiC region in a plane at depth x, the density of ionized dopants in the second doped SiC region and the area of the second doped SiC region, are defined so that in one embodiment the trenches/recesses are the second doped SiC region, while the material surrounding the trenches/recesses are referred to as the first doped SiC region. lt can be seen from the limits for ß (less than 1) that the second region has a lower value for p(x)*Ap(x). Thus for a manufactured component in “on-state” current is lead through the first region. The second region is in one embodiment in the trenches. ln an alternative embodiment the second region is instead the region surrounding the trenches. ln the former embodiment the first region is then surrounding the trenches and in the latter embodiment the first region is in the trenches.
[O030]Various embodiments are depicted in Figs 1, 2, and 4. ln one embodiment as depicted in Figs 1 and 2 the first doped SiC region, i.e. the surrounding material is donor-doped, while the material in the trenches is acceptor-doped.
Thus in this embodiment n(x)*An(x) relates to the donor doped first doped region and p(x)*Ap(x) refers to the acceptor doped second doped region.
[0031]ln an alternative embodiment also indicated in Fig 4 the first doped SiC region, i.e. the surrounding material is acceptor-doped, while the material in the trenches is donor-doped. This embodiment may also be referred to as an inverted embodiment. Thus in this embodiment n(x)*An(x) relates to the acceptor doped first doped region and p(x)*Ap(x) refers to the donor-doped second doped region.
[0032]|n one embodiment the first doped SiC region has the same doping as the substrate. Various examples are given in Fig 4a-4d. ln this context it is important to note that when the first doped SiC region is in the trenches, then the substrate has to have the same type of doping. For instance if the first doped SiC is in the trenches and is donor-doped, then the substrate also has to 538 783 be donor-doped. Further the depth of the trenches should exceed the thickness of the second doped SiC region so that the trench and the substrate are in contact with each other.
[0033]|n one embodiment the fi||ing of the at least one trench step d) comprises a first fi||ing followed by planarization and a second fi||ing. By using this method deeper trenches can be filled without the need for adding several layers and position the additional trenches with high precision on top of the existing trenches. For very deep trenches this process can be repeated several times. ln one embodiment the fi||ing comprises several cycles of fi||ing and planarizing.
[O034]|n one embodiment the super-junction structure is planarized after step d).
[0035]|t is conceived that the manufactured super-junction structure is cut in a suitable size and made into a component by appropriate connections and encapsulation known to a person skilled within the art.
[0036]|n yet another aspect there is provided a wafer comprising super-junction structures as described above, wherein the super-junction structures cover the entire wafer. This has the advantage that the wafers can be utilized for any application and do not have to be tailored for a specific device. Normally the layout of the super-junction structures are dependent on the particular device to be manufactured. However using this approach one general type of wafers can be used for manufacturing many components different in size and design.
[O037]All the described alternative embodiments above or parts of an embodiment can be freely combined without departing from the inventive idea as long as the combination is not contradictory.
[0038]Other features and uses of the invention and their associated advantages will be evident to a person skilled in the art upon reading the description and the examples. 10 538 783
[0039]|t is to be understood that this invention is not limited to the particular embodiments shown here. The embodiments are provided for illustrative purposes and are not intended to limit the scope of the invention since the scope of the present invention is limited only by the appended claims and equivalents thereof. One example of a component is a power MOSFET 11

Claims (19)

538 783 CLAIMS
1. A super-junction structure manufactured with an epitaxy process and having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench, said at least one trench comprising one of i) the first doped SiC region and ii) the second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, wherein the density of dopants outside said at least one trench is adapted to the density of dopants in said at least one trench for a plurality of planes perpendicular to the growth direction of the epitaxy process to achieve charge compensation in each plane, wherein the charge compensation ß is less than 1 calculated according to the formula fl(><)*^~(><)=ß'1*D(X)*AP(X) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, An(x) is the area of the first doped SiC region in a plane at depth x, p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X.
2. The super-junction structure according to claim 1, wherein the first doped SiC region is donor-doped and wherein the second doped SiC region is acceptor-doped. 12 538 783
3. _ The super-junction structure according to claim 1, wherein the first doped SiC region is acceptor-doped and wherein the second doped SiC region is donor-doped.
4. _ The super-junction structure according to any one of claims 1-3, wherein the charge compensation ß is at least 0.5.
5. _ The super-junction structure according to any one of claims 1-4, wherein the charge compensation ß is at least 0.75.
6. _ The super-junction structure according to any one of claims 1-5, wherein the super-junction structure is planarized.
7. _ The super-junction structure according to any one of claims 1-6, wherein the first doped SiC region has the same doping as the substrate.
8. _ A method of manufacturing a super-junction structure, said super-junction structure having at least one surface, said super-junction structure comprises a first doped SiC region and a second doped SiC region, and said super-junction structure comprising at least one trench comprising one of i) said first doped SiC region and ii) said second doped SiC region, wherein the ionized dopants of the first doped SiC region and the ionized dopants of the second doped SiC region have the opposite sign of the charge, said method comprising the steps of: a. estimating the density of ionized dopants in the at least one trench of the super-junction structure to be manufactured, wherein the density of ionized dopants is estimated for a plurality of planes perpendicular to the growth direction of the epitaxy process, each plane corresponding to a depth (x) from the surface of the super-junction structure to be manufactured, b. growing at least one layer of doped SiC by epitaxy wherein the SiC is doped, and wherein the density of dopants is adapted for each depth of the growing material to achieve charge compensation in the plane 13 538 783 corresponding to that depth, wherein the charge compensation ß is less than 1 calculated according to the formula fl(><)*An(X)=ß'1*D(X)*Ap(><) wherein n(x) is the density of ionized dopants in the first doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, An(x) is the area of the first doped SiC region in a plane at depth x, p(x) is the density of ionized dopants in the second doped SiC region as a function of the depth x from the surface of the super-junction structure to be manufactured, Ap(x) is the area of the second doped SiC region in a plane at depth X! c. creating at least one trench in the at least one layer grown in step b), d. filling the at least one trench created in step c) with epitaxial growth of one of i) the first doped SiC region and ii) the second doped SiC region.
9. The method according to claim 8, wherein the estimate in step a) is performed using a theoretical calculation.
10.The method according to claim 8, wherein the estimate in step a) is performed by measurement.
11. .The method according to any one of claims 8-10, wherein the first doped SiC region is donor-doped and wherein the second doped SiC region is acceptor-doped. 14 538 783
12.The method according to any one of claims 8-10, wherein the first doped SiC region is acceptor-doped and wherein the second doped SiC region is donor-doped.
13.The method according to any one of claims 8-12, wherein the at least one trench in step c) is created by etching.
14.The method according to any one of claims 8-12, wherein the charge compensation ß is at least 0.5.
15.The method according to any one of claims 8-12, wherein the charge compensation ß is at least 0.75.
16.The method according to any one of claims 8-15, wherein the fi||ing of the at least one trench step d) comprises a first fi||ing followed by planarization and a second filling.
17.The method according to claim 16, wherein the fi||ing comprises several cycles of fi||ing and planarizing.
18.The method according to any one of claims 8-17, wherein the super- junction structure is planarized after step d).
19.A wafer comprising super-junction structures according to any one of claims 1-7, wherein the super-junction structures cover the entire wafer. 15
SE1550821A 2015-06-16 2015-06-16 SiC SUPER-JUNCTIONS SE538783C2 (sv)

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Application Number Priority Date Filing Date Title
SE1550821A SE538783C2 (sv) 2015-06-16 2015-06-16 SiC SUPER-JUNCTIONS
EP16728959.4A EP3311411A1 (en) 2015-06-16 2016-06-14 Sic superjunction structures
PCT/EP2016/063607 WO2016202786A1 (en) 2015-06-16 2016-06-14 Sic superjunction structures

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SE538783C2 true SE538783C2 (sv) 2016-11-22

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SE1550821A1 (sv) 2016-11-22
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