SE0201707D0 - Arrangement for reducing current density in a transistor - Google Patents

Arrangement for reducing current density in a transistor

Info

Publication number
SE0201707D0
SE0201707D0 SE0201707A SE0201707A SE0201707D0 SE 0201707 D0 SE0201707 D0 SE 0201707D0 SE 0201707 A SE0201707 A SE 0201707A SE 0201707 A SE0201707 A SE 0201707A SE 0201707 D0 SE0201707 D0 SE 0201707D0
Authority
SE
Sweden
Prior art keywords
transistor
current density
arrangement
reducing current
fingers
Prior art date
Application number
SE0201707A
Other languages
English (en)
Other versions
SE522910C2 (sv
SE0201707L (sv
Inventor
Andrej Litwin
David Andersson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE0201707A priority Critical patent/SE522910C2/sv
Publication of SE0201707D0 publication Critical patent/SE0201707D0/sv
Priority to CN03812742.3A priority patent/CN1708854A/zh
Priority to AU2003228185A priority patent/AU2003228185A1/en
Priority to PCT/SE2003/000741 priority patent/WO2003103055A1/en
Priority to EP03725942A priority patent/EP1509954A1/en
Publication of SE0201707L publication Critical patent/SE0201707L/sv
Publication of SE522910C2 publication Critical patent/SE522910C2/sv
Priority to US11/002,018 priority patent/US20050077578A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
SE0201707A 2002-06-03 2002-06-03 Integrerad krets för reducering av strömdensitet i en transistor innefattande sammanflätade kollektor-, emitter- och styrfingrar SE522910C2 (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE0201707A SE522910C2 (sv) 2002-06-03 2002-06-03 Integrerad krets för reducering av strömdensitet i en transistor innefattande sammanflätade kollektor-, emitter- och styrfingrar
CN03812742.3A CN1708854A (zh) 2002-06-03 2003-05-07 一种用于降低集成电路中晶体管内电流密度的布局
AU2003228185A AU2003228185A1 (en) 2002-06-03 2003-05-07 Arrangement for reducing current density in a transistor in an ic
PCT/SE2003/000741 WO2003103055A1 (en) 2002-06-03 2003-05-07 Arrangement for reducing current density in a transistor in an ic
EP03725942A EP1509954A1 (en) 2002-06-03 2003-05-07 Arrangement for reducing current density in a transistor in an ic
US11/002,018 US20050077578A1 (en) 2002-06-03 2004-12-02 Arrangement for reducing current density in transistor in an IC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0201707A SE522910C2 (sv) 2002-06-03 2002-06-03 Integrerad krets för reducering av strömdensitet i en transistor innefattande sammanflätade kollektor-, emitter- och styrfingrar

Publications (3)

Publication Number Publication Date
SE0201707D0 true SE0201707D0 (sv) 2002-06-03
SE0201707L SE0201707L (sv) 2003-12-04
SE522910C2 SE522910C2 (sv) 2004-03-16

Family

ID=20288081

Family Applications (1)

Application Number Title Priority Date Filing Date
SE0201707A SE522910C2 (sv) 2002-06-03 2002-06-03 Integrerad krets för reducering av strömdensitet i en transistor innefattande sammanflätade kollektor-, emitter- och styrfingrar

Country Status (6)

Country Link
US (1) US20050077578A1 (sv)
EP (1) EP1509954A1 (sv)
CN (1) CN1708854A (sv)
AU (1) AU2003228185A1 (sv)
SE (1) SE522910C2 (sv)
WO (1) WO2003103055A1 (sv)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951788A (zh) * 2019-12-10 2021-06-11 圣邦微电子（北京）股份有限公司 功率管

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2145559A (en) * 1983-08-26 1985-03-27 Philips Electronic Associated Interdigitated semiconductor device
US6150722A (en) * 1994-11-02 2000-11-21 Texas Instruments Incorporated Ldmos transistor with thick copper interconnect
DE69415987T2 (de) * 1994-11-08 1999-06-24 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Integrierte Anordnung mit einer Struktur zum Schutz gegen hohe elektrische Felder
DE69520281T2 (de) * 1995-12-22 2001-08-09 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Hochgeschwindigkeit-MOS-Technologie-Leistungsanordnung in integrierter Struktur mit reduziertem Gatewiderstand
FR2759493B1 (fr) * 1997-02-12 2001-01-26 Motorola Semiconducteurs Dispositif de puissance a semiconducteur
US6737301B2 (en) * 2000-07-13 2004-05-18 Isothermal Systems Research, Inc. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
US20020106587A1 (en) * 2000-11-21 2002-08-08 Advanced Micro Devices, Inc. Two mask via pattern to improve pattern definition

Also Published As

Publication number Publication date
WO2003103055A1 (en) 2003-12-11
EP1509954A1 (en) 2005-03-02
US20050077578A1 (en) 2005-04-14
CN1708854A (zh) 2005-12-14
SE522910C2 (sv) 2004-03-16
AU2003228185A1 (en) 2003-12-19
SE0201707L (sv) 2003-12-04

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Legal Events

Date Code Title Description
NUG Patent has lapsed