RU2025822C1 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit Download PDF

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Publication number
RU2025822C1
RU2025822C1 SU914920371A SU4920371A RU2025822C1 RU 2025822 C1 RU2025822 C1 RU 2025822C1 SU 914920371 A SU914920371 A SU 914920371A SU 4920371 A SU4920371 A SU 4920371A RU 2025822 C1 RU2025822 C1 RU 2025822C1
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RU
Russia
Prior art keywords
integrated circuit
hybrid integrated
crystals
semiconductor crystals
metallized holes
Prior art date
Application number
SU914920371A
Other languages
Russian (ru)
Inventor
В.А. Иовдальский
Э.И. Рыжик
Б.А. Тархов
Original Assignee
Государственное научно-производственное предприятие "Исток"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Государственное научно-производственное предприятие "Исток" filed Critical Государственное научно-производственное предприятие "Исток"
Priority to SU914920371A priority Critical patent/RU2025822C1/en
Application granted granted Critical
Publication of RU2025822C1 publication Critical patent/RU2025822C1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

FIELD: electronics. SUBSTANCE: metal plated stepped recession which houses crystals is manufactured in hybrid integrated circuit. EFFECT: simplified manufacturing process, enhanced reliability of hybrid integrated circuit. 2 cl, 2 dwg

Description

Изобретение относится к электронной технике, а именно к конструкции гибридных интегральных схем СВЧ. The invention relates to electronic equipment, namely to the design of hybrid microwave integrated circuits.

Целью изобретения является уменьшение габаритов и увеличение мощности. The aim of the invention is to reduce the size and increase power.

На фиг. 1 изображена интегральная схема, продольный разрез, где 1 - диэлектрическая плата, 2 - металлизация лицевой стороны платы 1, 3 - металлизация обратной стороны платы 1, 4 - полупроводниковые кристаллы, 5 - соединительные проводники, 6 - металлизированные отверстия, 7 - металлическое основание 7, 8 - ступенчатая выемка, 9 - связующее вещество, 10 - контактные площадки полупроводниковых кристаллов 4; на фиг.2 - та же схема в плане. In FIG. 1 shows an integrated circuit, a longitudinal section, where 1 is the dielectric board, 2 is the metallization of the front side of the board 1, 3 is the metallization of the back side of the board 1, 4 are semiconductor crystals, 5 are the connecting conductors, 6 are metallized holes, 7 is the metal base 7 , 8 - step recess, 9 - binder, 10 - contact pads of semiconductor crystals 4; figure 2 is the same diagram in plan.

Расстояние между кристаллами 4 выбрано равным 20-100 мкм. Расстояние между плоскостью лицевой поверхности 11 кристалла 4 и плоскостью 12 среза ступенчатой выемки 8 выбрано равным 1-20 мкм. The distance between the crystals 4 is chosen equal to 20-100 microns. The distance between the plane of the front surface 11 of the crystal 4 and the plane 12 of the cut stepped recess 8 is selected equal to 1-20 μm.

Размещение кристаллов 4 в ступенчатой выемке 8 позволяет уменьшить длину проводников 5 и, как следствие, их индуктивность. Это позволяет расширить частотный диапазон работы схемы. Соединение металлизированными отверстиями 6 с металлизацией 3 платы 1 и основания кристалла 4 позволяет улучшить теплоотвод. The placement of the crystals 4 in the stepped recess 8 allows to reduce the length of the conductors 5 and, as a consequence, their inductance. This allows you to expand the frequency range of the circuit. The connection metallized holes 6 with metallization 3 of the board 1 and the base of the crystal 4 can improve heat dissipation.

Таким образом, применение изобретения позволяет улучшить теплоотвод и уменьшить габариты схемы. Thus, the application of the invention improves the heat sink and reduce the dimensions of the circuit.

Claims (2)

1. ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА, содержащая диэлектрическую плату с разводкой, экранной металлизацией и вертикальными металлизированными отверстиями, полупроводниковые кристаллы, отличающаяся тем, что, с целью уменьшения габаритов и улучшения электрических параметров, в плате выполнена ступенчатая выемка с металлизированным дном, в которой над металлизированными отверстиями установлены полупроводниковые кристаллы, при этом расстояние между кристаллами 20 - 100 мкм, а расстояние между плоскостями лицевой поверхности полупроводниковых кристаллов и среза выемки 1 - 20 мкм. 1. HYBRID INTEGRAL CIRCUIT, containing a dielectric board with wiring, screen metallization and vertical metallized holes, semiconductor crystals, characterized in that, in order to reduce dimensions and improve electrical parameters, a step recess is made in the board with a metallized bottom, in which above the metallized holes semiconductor crystals are installed, while the distance between the crystals is 20-100 microns, and the distance between the planes of the front surface of the semiconductor crystals and a slit of the notch 1 - 20 microns. 2. Интегральная схема по п.1, отличающаяся тем, что суммарная площадь металлизированных отверстий равна 10 - 70% площади дна ступенчатой выемки. 2. The integrated circuit according to claim 1, characterized in that the total area of metallized holes is 10 - 70% of the bottom area of the stepped recess.
SU914920371A 1991-03-19 1991-03-19 Hybrid integrated circuit RU2025822C1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU914920371A RU2025822C1 (en) 1991-03-19 1991-03-19 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU914920371A RU2025822C1 (en) 1991-03-19 1991-03-19 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
RU2025822C1 true RU2025822C1 (en) 1994-12-30

Family

ID=21565722

Family Applications (1)

Application Number Title Priority Date Filing Date
SU914920371A RU2025822C1 (en) 1991-03-19 1991-03-19 Hybrid integrated circuit

Country Status (1)

Country Link
RU (1) RU2025822C1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998015981A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Microwave-frequency hybrid integrated circuit
WO1998015980A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Hybrid high-power integrated circuit
WO1998015977A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Hybrid high-power microwave-frequency integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Applied microwave magazine, 1990, V. 2, N 3, p.4. *
Hyperworld, 1990, N 2, p.79. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998015981A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Microwave-frequency hybrid integrated circuit
WO1998015980A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Hybrid high-power integrated circuit
WO1998015977A1 (en) * 1996-10-10 1998-04-16 Samsung Electronics Co., Ltd. Hybrid high-power microwave-frequency integrated circuit

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