UNIDIRECTIONAL UNIFIL COMMUNICATION INTERFACE
FIELD OF THE INVENTION
The present disclosure relates to a device for the transmission of signals between two data processors. More particularly, the description relates to a device for exchanging data between a central processor and a slave processor. A connection between the two processors is provided by a single data line, and communications are carried out in one direction, from the slave processor to the central processor.
BACKGROUND OF THE INVENTION
For portable electronic devices, such as for example cell phones, personal digital assistants and recording cameras, architectures / protocols have been developed to connect various components of portable electronic devices to each other, in such a way that they can communicate. A simple example is a battery pack (a "slave" component) that can be connected, removably to a portable electronic device (a "central" device). At least the battery pack
i electronic portable to inform the recording camera, the amount of energy contained in the battery. Preferably the communication architecture is designed with as few connections as possible. Currently one of the most used architectures is the system management bus (SM) which includes three cables to interconnect central devices and slave components. Devices and components communicate to
10 through one of the cables, while a clock signal is provided through the second cable, and the third cable is used as a ground connection. A currently popular protocol for use through the SM bus is the Inter-Integrated Circuit (I2C), the
15 which was originally developed by Philips Semiconductor. The protocol uses a synchronous signal and has the advantage of housing multiple master components and multiple slave components (including multiple batteries, where the system monitors various aspects of the
20 condition of each battery). However, cell phone manufacturers have emphasized using a communication architecture that includes only two cables. An architecture / protocol that has been adopted by most
25 cell phone companies is the "DQ" system
developed by Dallas Semiconductor, Benchmarq, Unitrode, and Texas Instrument. The DQ system uses a single cable and a ground wire to connect a central device to multiple slave components. The data is transmitted in two directions by the cable that is not grounded. The architecture includes an actuation resistor that keeps the line in a high level state, and allows the data to be transmitted by putting the line in a low state, so that the state of the line is up or down for each transmitted bit . A disadvantage of the bidirectional monofilar bus is that with multiple slave components connected to a master device, the connection agreement becomes complicated, and the central device must interrogate each slave component separately. Another disadvantage of the bidirectional monofilar bus is that it requires some use of temporal domain or frequency domain relationships to track the two half-channels of communication. In an effort to minimize the expense of the system, an imprecise time base is provided using an unstable oscillator. This imprecise time base, together with the electrical relationships, provides the necessary references for bi-directional communication through a monofilar bus. An additional disadvantage of the monofilar bus,
t?.? j .. t .a- .. ???. I4 bidirectional, is that, due to the bidirectional nature of communications, the slave component must require the ability to sample the data line and receive messages from the central device. A slave component of an I2C system will then, in most cases, require the architecture necessary to allow the slave to receive messages, thus increasing the cost and complexity of the slave. Accordingly, what is still desired is a new and improved communications architecture / protocol for connecting a processor of a slave component to a processor of a central component. Preferably the new architecture / protocol will be simple and inexpensive compared to the I2C and DQ systems described above.SUMMARY OF THE INVENTION
As an answer the present disclosure provides a data communication interface for transferring at least one bit of data to a central processor. The interface includes a data line, monofilar, and a slave processor connected to the data line, and includes a descent circuit to vary the voltage on the data line. The slave processor is unable to sample data from the data line, but is programmed to vary
The communication format is simple and does not require continuous monitoring, resulting in a reduction in power consumption for both the central device and the slave, which is of course important in portable electronic devices. The unidirectional monofilar communication interface described herein is therefore particularly attractive for handheld electronic devices or other portable low energy consumption electronic devices, such as for example cell phones, personal digital assistants and recording cameras.
BRIEF DESCRIPTION OF THE DRAWINGS
The present description is described with reference to the accompanying drawings, wherein: Figure 1 is a simplified schematic view illustrating a communication interface in accordance with the present disclosure, which includes a slave component connected to a central device through a monofilar, unidirectional bus; Figure 2 shows graphs of the data line voltage, versus time, illustrating unidirectional communication in accordance with the present disclosure, for use with the interface of Figure 1;
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Figure 3 shows a flow chart illustrating a "data start" algorithm in accordance with the present disclosure, for use by the central device of Figure 1; Figure 4 shows a flow diagram illustrating a "data delivery" algorithm according to the present description, for use by the slave component of Figure 1; Figure 5 shows a flow chart that
10 illustrates a "data delivery" algorithm in accordance with the present disclosure, for use by the central device of Figure 1; Figure 6 is a simplified schematic view illustrating a communications interface in accordance with
15 the present description, which includes a single-wire, unidirectional bus, which connects a slave component comprising a battery pack, to a central device comprising a portable electronic product; Figure 7 is a simplified schematic view
20 illustrating a computer processing unit, in accordance with the present disclosure, adapted to be connected in series with other, similar computer processing units, for sequential communications with a central device; and 25 Figure 8 is a simplified schematic view
illustrating a battery pack constructed in accordance with the present disclosure and including a plurality of computer processing units of Figure 7, connected together, in series, for sequential communication with a central device. Similar reference characters designate identical or corresponding components and units in all different views.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Figures 1 to 4, the present disclosure provides a method for sending the signal of at least one data bit to a central processor, from a slave processor, through a monofilar data line. The method includes providing a slave processor that is unable to sample data from the data line. The method also includes energizing the data line using a central processor, when at least one data bit of the slave processor is desired, varying the data line voltage, energized, using the slave processor, and sampling the line voltage. of data energized using the central processor to determine the value of a bit signaled by the slave processor. When the desired data bit is signaled
by the slave processor, the central processor de-energizes the data line. Preferably the slave processor does not initiate the voltage variation in the energized data line to signal the data bit until a preselected time period after the line is energized by the central device, such that the central device is prepared for receive the complete data signal. As best shown in Figure 2, the central processor energizes the data line, raising the data line to a high logical level. Then the slave processor lowers the voltage on the energized data line to send a "0" signal and raises the high voltage on the energized data line to send a signal of a "1". The communication method is preferably designed to minimize the transfer of charge out of the battery in the module. In this way the slave processor never supplies power to the data line, but only consumes current. As shown in Figure 1, a central device that has a computer processing unit
(CPU) includes the central processor. The CPU also includes a descent transistor, controlled by the central processor to vary the voltage in the data line. A slave component has a CPU that includes the processor
JL? ? H. *. t * --- ±, * - * - *. < ? slave and also includes a very high impedance drop resistor to vary the voltage on the data line. (A very high impedance drop resistor is used in the slave component only to avoid the risk of floating nodes). As shown, the system also includes an electrical power line and a ground connection line that extends between the device and the component. All the lines are connected in a divided way between the slave component and the central component, so that the lines can be reconnected when desired, whereby the slave component can be connected in the central component (for example as a battery pack). to connect to a cell phone). Figure 3 shows a "data initialization" algorithm according to the present description, for use by the central processor of Figure 1, while Figure 4 shows a "data delivery" algorithm in accordance with the present description, for use by the slave processor of Figure 1. With the (send data) algorithm of Figure 4, the slave processor does not act until it is energized by the central processor when the central processor powers the line of data. Figure 5 shows an alternative "data delivery" algorithm, in accordance with this
Ajeft 11 description, for use by the central device of Figure 1. Using the alternative algorithm, the slave processor simply attempts to send the data signal at preselected intervals, even if the data line 5 has not been energized by the device central. Figure 6 shows a slave component comprising a battery pack, including the slave CPU of Figure 1. In addition to the slave CPU, the battery pack includes a battery, at least one device
10 measurement for measuring a variable property of the battery and for producing an analog signal indicating the measurement, and an analog-to-digital converter for converting the analog signal indicating the measurement, for at least one data bit. The slave CPU is connected to the converter e
15 includes a memory (not shown) for receiving the at least one data bit of the converter, and storing the at least one data bit until the data line is energized. As shown in Figure 6, the at least one measuring device of the battery pack comprises
20 means for measuring voltage level, current, temperature, and current usage. As shown also, the battery pack can be connected to a portable product (for example a cell phone) including the central CPU of Figure 1. 25 Referring to Figure 7, another slave CPU including a line is shown. , a data output line, and a signal output line. The slave CPU also includes a processor that includes a descent circuit to vary the voltage on the signal output line. The processor is connected to the signal input line and the data output line, and is programmed to transfer at least one bit of data through the data output line, when the voltage of the input line is varied of signals. The processor is also programmed to vary the voltage in the signal output line when the transfer of the at least one data bit is completed through the data line. The slave CPU of Figure 7 is adapted to be connected in series with other slave components for sequential communications with a central device. Figure 8 shows a battery pack constructed in accordance with the present disclosure and includes a plurality of the slave components of Figure 7 connected together, in series, for sequential communication with a central device. Each of the slave components is connected to a battery. Although not shown, each slave component includes at least one measuring device for measuring a variable property of the battery, and an analog-to-digital converter for converting an analog signal produced by the device.
measurement in a digital signal. As shown, the signal input lines and the signal output lines of the slave CPUs are connected in series. The assembly also includes an assembly CPU having a processor, a monofilar data line for connection to a central component (not shown), an information line arranged to receive signals from each of the data output lines of the slave components and an instruction line connected to the signal input line of a first of the connected slave components. The assembly processor is connected to the assembly data line and includes a first descent circuit to vary the voltage on the data line, to send a signal to a central component connected to the data line. The processor is also connected to an instruction line and includes a second descent circuit to vary the voltage in the instruction line. The processor is also connected to the information line. The processor is programmed to vary the voltage in the instruction line, using the second down-cycle when the data line is energized to send a signal to the first slave CPU to report the information. The assembly processor is also programmed to vary the voltage in the data line, using
.? J, J *? »* ..? J * ^ .... Ji. , -., ... jzfcfc ^ the first descent circuit, when at least one data bit, coming from the slave components, is received in the information line, to send the information signal through the line of data, including the identification of the slave component (ie, first slave, second slave ...) and the at least one data bit of the particular slave component (i.e., information about the respective battery of the slave). In this way, when a central component energizes the assembly data line, the assembly processor lowers the voltage in the instruction line to instruct the first slave CPU to send an information signal concerning the first battery, to the assembly CPU, through the information line. The assembly processor then sends signals of the number and information of the battery to the central component through the data line, using the protocol of Figure 2. The second, third and fourth slaves then sequentially report their battery information, to the assembly CPU, which in turn sequentially reports the battery identifier and the battery information, to the central component. The signal output line of the last of the slave CPUs (the fourth slave in the particular mode) is also connected to the information line
J. ?£l t. i. . fe ^ *** Ai of the assembly processor. When the last slave has finished reporting the information to the assembly CPU, the last slave sends signal to the assembly to which the last slave has reported through the signal output line of the slave and the information line of the CPU. assemble The assembly CPU can then send signals to the central component to which all the slaves in the assembly have reported. The signal input and signal output lines of the slave CPUs are preferably connected via voltage level shifters, and the data output lines are preferably connected to the information line of the assembly CPU via optical isolators. In addition, the signal output line of the slave and the information line of the assembly CPU are connected through an optical isolator. In this way the present disclosure provides a new and improved communications architecture and protocol, which includes connecting a single data cable, between a central processor and a slave processor. In this approach the central processor (which may be in a portable electronic component, such as a cell phone, personal digital assistant (PDA), or recording camera) contains a switch to connect a positive voltage in the data line. The slave processor (which
can be contained within a battery pack to monitor the battery) then sends data signals at a fixed speed, using a predetermined protocol, but only in one direction along the data line. Accordingly, when the central processor needs information, the central component energizes the data line and the slave processor is able to send information to the central component. When the slave processor data transmission has been completed, or even before the transmission is complete (ie, at the discretion of the core processor), the central processor can remove the voltage source from the data line, causing the line of data lower level. The slave can be programmed to become activated and only send data when the data line is energized, or it can send data continuously regardless of the status of the data line. In a device containing multiple slave processors in accordance with the present invention, interrogation of each slave by the central processor is performed sequentially and periodically. In one embodiment (not shown) each slave can include a storage device, such as a shift recorder, which can be updated continuously in real time with the desired information for transmission to the central component. Later, when
MM .-. T.h., .. ...? ^. , ^^. ^,, ^? ^? ^^^^^ .. í? ^^? tMáu? í & ^^? is activated by the central component, the slave provides the most recently updated information, to the central component. An additional embodiment (not shown) could comprise a system for monitoring multiple batteries with 5 periodic and staggered time delays, or a wired OR logic array, to determine which slave is being interrogated. You can also use several arbitrary schemes, or logical arrays, to determine if one slave or another is using a single cable for data transmission.
Those skilled in the art will recognize that the embodiments described above are only illustrative. These examples can help show part of the scope of the inventive concepts, but these examples do not exhaust the full scope of variations in concepts
15 novelties described. In this way, the scope of the innovative concepts described in the present description is not limited except by the appended claims.
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