KR970077383A - 전자장치의 패키지화 방법 및 전자장치 및 패키지 - Google Patents

전자장치의 패키지화 방법 및 전자장치 및 패키지 Download PDF

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KR970077383A
KR970077383A KR1019970008776A KR19970008776A KR970077383A KR 970077383 A KR970077383 A KR 970077383A KR 1019970008776 A KR1019970008776 A KR 1019970008776A KR 19970008776 A KR19970008776 A KR 19970008776A KR 970077383 A KR970077383 A KR 970077383A
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electronic device
substrate
electrically conductive
single layer
coating
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KR1019970008776A
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KR100272069B1 (ko
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제임스 워렌 윌슨
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포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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Abstract

볼 그리드 어레이 패키지의 형태의 전자장치 패키지는 함께 전기적으로 접속된 트레이스 라인, 와이어 본드 패드 및 솔더 볼 패드를 갖는 회로를 포함한 전도성 재료의 단일층을 부가하는 것에 의하여 형성된다. 폴리이미드 라미네이트 기판상에서 박막 회로화 기술을 사용하여, 단일층에 전자장치의 100개 이상의 입력/출력 접점을 수용한다. 따라서, 이러한 전자장치 패키지는 다중 전도성 층의 볼 그리드 어레이 패키지에 존재하는 것과 같은 비아 또는 다른 전도성 형태의 관통 구멍을 구비하지 않는다.

Description

전자장치의 패키지화 방법 및 전자장치 및 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 볼 그리드 어레이(BGA) 패키지의 부분 절결도.

Claims (33)

  1. 전자장치를 패키지화하는 방법에 있어서, ① 제1표면 및 반대의 제2표면을 구비한 기판을 제공하는 단계와, ② 상기 기판의 제1표면상에 전기 전도성 회로의 단일층(a single layer of electrically conductive circuitry)을 형성하는 단계와, ③ 상기 기판내에 개구부를 제공하는 단계와, ④ 상기 기판의 제2표면에 열전도성 부재를 고정하는 단계와, ⑤ 상기 전자장치가 기판의 개구부내에 위치되도록 상기 전자장치를 상기 열도성 부재에 고정하는 단계와, ⑥ 상기 전자장치를 와이어 본드 패드에 전기적으로 접속하는 단계를 포함하는 전자 장치의 패키지화 방법.
  2. 제1항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 진공 금속화법(a vacuum metallization process)을 이용하여 상기 기판의 제1표면상에 전기 전도성 재료를 침착하는 단계를 포함하는 전자장치의 패키지화 방법.
  3. 제2항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 상기 진공 금속화법에 의해 침착된 전기 전도성 재료의 두께를 증가시키기 위해서 전기 도금법을 이용하여 부가적인 전기 전도성 재료를 침착하는 단계를 포함하는 전자장치의 패키지화 방법.
  4. 제2항 또는 제3항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 트레이스 라인(trace lines), 솔더 볼 패드(solder ball pads) 및 와이어 본드 패드(wire bond pads)를 형성하도록 상기 전기 전도성 재료의 부분을 제거하는 단계를 포함하는 전자장치의 패키지화 방법.
  5. 제2항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 상기 제1표면상에 단일체의 Cr/Cu/Cr층을 형성하기 위해서 상기 제1표면상에 제1Cr 피복물을 스퍼터링하는 단계와, 상기 제1Cr 피복물상에 Cu 피복물을 스퍼터링하는 단계와, 상기 Cu 피복물상에 제2Cr 피복물을 스퍼터링하는 단계를 포함하는 전자장치의 패키지화 방법.
  6. 제1항에 있어서, 상기 기판을 제공하는 단계는 유기 재료로 형성된 기판을 제공하는 단계를 포함하는 전자장치의 패키지화 방법.
  7. 제1항에 있어서, 상기 기판을 제공하는 단계는 폴리이미드 재료로 형성된 기판을 제공하는 단계를 포함하는 전자장치의 패키지화 방법.
  8. 제1항에 있어서, 상기 개구부를 제공하는 단계는 펀칭에 의해 상기 개구부를 제공하는 단계를 포함하는 전자장치의 패키지화 방법.
  9. 제1항에 있어서, 상기 열전도성 부재를 고정하는 단계는 접착제를 이용하여 상기 기판의 제2표면에 상기 열전도성 부재를 고정하는 단계를 포함하는 전자장치의 패키지화 방법.
  10. 제1항에 있어서, 상기 전자장치를 고정하는 단계는 접착제를 이용하여 상기 열전도성 부재에 상기 전자장치를 고정하는 단계를 포함하는 전자장치의 패키지화 방법.
  11. 제1항에 있어서, 상기 전자장치를 접속하는 단계는 와이어 본딩에 의해 상기 전자장치를 상기 전기 전도성 회로의 단일층에 전기적으로 접속하는 단계를 포함하는 전자장치의 패키지화 방법.
  12. 제1항에 있어서, 각 솔더 볼 패드상에 솔더 볼을 형성하는 단계를 더 포함하는 전자장치의 패키지화 방법.
  13. 제1항에 있어서, 상기 전자장치를 전기 절연재로 밀봉화하는 단계를 더 포함하는 전자장치의 패키지화 방법.
  14. 제1항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 1밀(mil) 이하의 폭을 갖는 전기 전도성 트레이스 라인을 형성하는 단계를 포함하는 전자장치의 패키지화 방법.
  15. 제14항에 있어서, 상기 기판을 제공하는 단계는 크기가 15mm 내지 50mm×15mm 내지 50mm 범위인 기판을 제공하는 단계를 포함하는 전자장치의 패키지화 방법.
  16. 제15항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 100개 이상의 트레이스 라인을 형성하는 단계를 포함하는 전자장치의 패키지화 방법.
  17. 제1항에 있어서, 상기 전기 전도성 회로의 단일층을 형성하는 단계는 0.5밀 이하의 두께를 갖는 전기 전도성 회로의 단일층을 형성하는 단계를 포함하는 전자장치의 패키지화 방법.
  18. 전자장치 패키지에 있어서, ① 제1표면 및 반대의 제2표면과, 개구부를 구비한 기판과, ② 상기 제1표면상에 진공 금속화된 전기 전도성 회로의 단일층과, ③ 상기 제2표면에 고정된 열전도성 부재와, ④ 상기 기판의 상기 개구부내에 위치되도록 상기 열전도성 부재에 고정되고, 또 와이어 본드 패드에 전기적으로 접속된 전자장치를 포함하는 전자장치 패키지.
  19. 제18항에 있어서, 상기 기판은 유기 재료로 형성되는 전자장치 패키지.
  20. 제18항에 있어서, 상기 기판은 폴리이미드로 형성되는 전자장치 패키지.
  21. 제18항에 있어서, 상기 전기 전도성 회로의 단일층은 상기 제1표면상에 단일체의 Cr/Cu/Cr층을 형성하기 위해서 상기 제1표면상에 제1Cr 피복물, 상기 제1Cr 피복물상에 Cu 피복물 및 상기 Cu 피복물 및 상기 Cu 피복물상의 제2Cr 피복물을 포함하는 전자장치 패키지.
  22. 제18항에 있어서, 상기 전기 전도성 회로의 단일층의 두께는 0.5밀 이하인 전자장치 패키지.
  23. 제18항에 있어서, 상기 전기 전도성 회로의 단일층은 1밀 이하의 폭을 갖는 전기 전도성 트레이스 라인을 포함하는 전자장치 패키지.
  24. 제23항에 있어서, 상기 기판의 크기는 15mm 내지 50mm×15mm 내지 50mm 범위에 있는 전자장치 패키지.
  25. 제24항에 잇어서, 상기 전기 전도성 회로의 단일층은 100개 이상의 트레이스라인을 포함하는 전자장치 패키지.
  26. 제18항에 있어서, 상기 기판의 두께가 15밀인 전자장치 패키지.
  27. 제18항에 있어서, 상기 열전도성 부재를 상기 제2표면에 고정하기 위해 그리고 상기 전자장치를 열전도성 부재에 고정하기 위한 열 접착제를 더 포함하는 전자장치 패키지.
  28. 제18항에 있어서, 상기 열전도성 회로의 단일층은 함께 전기적으로 접속된 트레이스 라인, 와이어 본드 패드 및 솔더 볼 패드를 포함하는 전자장치의 패키지.
  29. 제18항에 있어서, 상기 전자장치는 100개 이상의 입력/출력 접점을 포함하는 전자장치 패키지.
  30. 제29항에 있어서, 상기 접점은 상기 와이어 본드 패드에 와이어 본딩된 전자장치 패키지.
  31. 제28항에 있어서, 각 솔더 볼 패드에 전기적으로 접속된 솔더 볼을 더 포함하는 전자장치 패키지.
  32. 제18항에 있어서, 상기 전자장치, 상기 개구부 및 상기 기판의 상기 제1표면의 일부분을 덮는 밀봉재(anencapsulant)를 더 포함하는 전자장치 패키지.
  33. 제18항에 있어서, 상기 열전도성 부재는 Cu를 포함하는 전자장치 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970008776A 1996-05-31 1997-03-14 전자장치의 패키지화 방법 및 전자장치 패키지 KR100272069B1 (ko)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6164993A (en) * 1999-02-12 2000-12-26 Micron Technology, Inc. Zero insertion force sockets using negative thermal expansion materials
US6198166B1 (en) * 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
US6643918B2 (en) * 2000-04-17 2003-11-11 Shielding For Electronics, Inc. Methods for shielding of cables and connectors
US6471525B1 (en) * 2000-08-24 2002-10-29 High Connection Density, Inc. Shielded carrier for land grid array connectors and a process for fabricating same
US6673710B1 (en) 2000-10-13 2004-01-06 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip
TW579581B (en) * 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
AU2007246215B2 (en) * 2001-03-21 2010-05-27 United Test Center Inc Semi Conductor Device and Method for Fabricating The Same
WO2014114003A1 (en) * 2013-01-28 2014-07-31 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including embedded controller die and method of making same
US9245835B1 (en) 2013-07-31 2016-01-26 Altera Corporation Integrated circuit package with reduced pad capacitance

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118209A (en) * 1980-02-20 1981-09-17 Hitachi Ltd Conductor
US4517051A (en) * 1982-12-27 1985-05-14 Ibm Corporation Multi-layer flexible film module
JPH04256342A (ja) * 1991-02-08 1992-09-11 Toshiba Corp 半導体パッケージ
US5209817A (en) * 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
JPH05160290A (ja) * 1991-12-06 1993-06-25 Rohm Co Ltd 回路モジュール
US5216806A (en) * 1992-09-01 1993-06-08 Atmel Corporation Method of forming a chip package and package interconnects
US5468994A (en) * 1992-12-10 1995-11-21 Hewlett-Packard Company High pin count package for semiconductor device
US5340771A (en) * 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
WO1996008037A1 (en) * 1994-09-06 1996-03-14 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture

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