KR970072669A - Reset delay device for stable system - Google Patents

Reset delay device for stable system Download PDF

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Publication number
KR970072669A
KR970072669A KR1019960011969A KR19960011969A KR970072669A KR 970072669 A KR970072669 A KR 970072669A KR 1019960011969 A KR1019960011969 A KR 1019960011969A KR 19960011969 A KR19960011969 A KR 19960011969A KR 970072669 A KR970072669 A KR 970072669A
Authority
KR
South Korea
Prior art keywords
microprocessor
reset
flip
inputting
signal
Prior art date
Application number
KR1019960011969A
Other languages
Korean (ko)
Inventor
김규택
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960011969A priority Critical patent/KR970072669A/en
Publication of KR970072669A publication Critical patent/KR970072669A/en

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Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

리셋장치에 관한 것이다.Reset device.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

전원이 온될 시 마이크로 프로세서의 리셋을 지연시켜주는 안정된 시스템을 위한 리셋 지연 장치를 제공한다.And a reset delay for a stable system that delays the reset of the microprocessor when the power is turned on.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

인가되는 전원에 의해 발생되는 클럭에 동기되는 다수의 시스템과, 상기 시스템을 리드 및 라이트하는 마이크로프로세서에서, 상기 마이크로프로세서를 동작할 수 있도록 상기 전원을 공급하는 장치는 인가되는 상기 전원을 소정시간 지연하여 상기 마이크로 프로세서로 리셋신호를 출력하는 지연수단을 구비한다.A plurality of systems synchronized with a clock generated by an applied power supply; and a microprocessor for reading and writing the system, wherein the apparatus for supplying power to operate the microprocessor is configured to delay the applied power by a predetermined time delay And a delay means for outputting a reset signal to the microprocessor.

4. 발명의 중요한 용도.4. An important use of the invention.

안정된 시스템을 위한 마이크로 프로세서의 리셋을 지연하는 장치를 구비한다.And a device for delaying a reset of the microprocessor for a stable system.

Description

안정된 시스템을 위한 리셋 지연 장치Reset delay device for stable system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따른 안정된 시스템을 위한 리셋 지연 장치를 보여주는 도면.Figure 2 shows a reset delay device for a stable system according to the invention;

Claims (2)

인가되는 전원에 의해 발생되는 클럭에 동기되는 다수의 시스템과, 상기 시스템을 리드 및 라이트하는 마이크로프로세서에서, 상기 마이크로프로세서를 동작할 수 있도록 상기 전원을 공급하는 장치에 있어서, 인가되는 상기 전원을 소정시간 지연하여 상기 마이크로 프로세서로 리셋신호를 출력하는 지연수단을 구비함을 특징으로 하는 안정된 시스템을 위한 리셋 지연 장치.A plurality of systems synchronized with a clock generated by an applied power supply; and a microprocessor for reading and writing the system, the apparatus supplying the power to operate the microprocessor, And outputting a reset signal to the microprocessor with a time delay. 제1항에 있어서, 상기 지연수단은, 클럭단으로 상기 클럭을 입력하며, 입력단으로 반전출력단의 반전신호를 입력하며, 상기 반전출력단의 반전신호를 다음단의 클럭단으로 출력하며, 클리어단에 상기 전원을 입력하는 다수의 디플립플롭과, 최종단에 위치하여 입력단으로 상기 전원을 입력하며, 클럭단으로 전단의 디플립플롭의 반전출력단의 반전신호를 입력하며, 클리어단에 상기 전원을 입력하는 디플립플롭으로 구성됨을 특징으로 하는 안정된 시스템을 위한 리셋 지연 장치.2. The semiconductor memory device according to claim 1, wherein the delay means inputs the clock signal at the clock terminal, inputs the inverted signal of the inverted output terminal to the input terminal, outputs the inverted signal of the inverted output terminal to the clock terminal of the next stage, A plurality of flip-flops for inputting the power source; a plurality of flip-flops for inputting the power source, the flip-flops inputting the power source to an input terminal and inputting an inverted signal of an inverted output terminal of the flip- And a D flip-flop for delaying the reset signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960011969A 1996-04-19 1996-04-19 Reset delay device for stable system KR970072669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960011969A KR970072669A (en) 1996-04-19 1996-04-19 Reset delay device for stable system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960011969A KR970072669A (en) 1996-04-19 1996-04-19 Reset delay device for stable system

Publications (1)

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KR970072669A true KR970072669A (en) 1997-11-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960011969A KR970072669A (en) 1996-04-19 1996-04-19 Reset delay device for stable system

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KR (1) KR970072669A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR860011123U (en) * 1985-02-25 1986-09-10 삼성전자 주식회사 Reset delay circuit
JPH05275982A (en) * 1992-03-26 1993-10-22 Nec Ic Microcomput Syst Ltd Delay flip flop circuit with reset
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
JPH07235863A (en) * 1994-02-21 1995-09-05 Toko Inc Delay circuit
EP0673117A1 (en) * 1994-03-17 1995-09-20 Advanced Micro Devices, Inc. A delay line circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR860011123U (en) * 1985-02-25 1986-09-10 삼성전자 주식회사 Reset delay circuit
JPH05275982A (en) * 1992-03-26 1993-10-22 Nec Ic Microcomput Syst Ltd Delay flip flop circuit with reset
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
JPH07235863A (en) * 1994-02-21 1995-09-05 Toko Inc Delay circuit
EP0673117A1 (en) * 1994-03-17 1995-09-20 Advanced Micro Devices, Inc. A delay line circuit

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