KR970049370A - Controller of HIPSS - Google Patents

Controller of HIPSS Download PDF

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Publication number
KR970049370A
KR970049370A KR1019950047873A KR19950047873A KR970049370A KR 970049370 A KR970049370 A KR 970049370A KR 1019950047873 A KR1019950047873 A KR 1019950047873A KR 19950047873 A KR19950047873 A KR 19950047873A KR 970049370 A KR970049370 A KR 970049370A
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KR
South Korea
Prior art keywords
bus
disk
pci
processor
means connected
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KR1019950047873A
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Korean (ko)
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KR0170492B1 (en
Inventor
김진표
김중배
안대영
박윤옥
최창열
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양승택
한국전자 통신연구원
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Priority to KR1019950047873A priority Critical patent/KR0170492B1/en
Publication of KR970049370A publication Critical patent/KR970049370A/en
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Publication of KR0170492B1 publication Critical patent/KR0170492B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 디스크 어레이(Disk Array)시스템인 HIPSS(High Performance Storage System)의 제어기 구조에 관한 것으로,그 특징은 프로세서와 지역 메모리와 실시간 클럭 발생기와 직렬 입출력 수단을 프로세서버스로 접속하여 구비하고 있는 HIPSS의 제어기에 있어서, 프로세서 버스에 접속되어 플로피 디스크 드라이버를 제어하는 플로피 디스크 제어수단과, 프로세서 버스와 접속되어 있고 제1PCI버스와 접속되어 데이터 전송을 정합시키는 제1PCI브리지 수단과, 프로세서 버스와 접속되어 있고 제2PCI버스와 접속되어 데이터 전송을 정합시키는 제2PCI 브리지 수단과, 제1PCI버스와 접속되어 데이터를 임시로 저장하는 제2디스크 캐쉬 기억수단과, 제1디스크 캐쉬 기억수단과 접속되어 제1디스크 캐쉬 기억수단에 저장되는 데이터의 패리티를 갱신하고 제1디스크 캐쉬 기억수단과 함께 독립적인 패리티 연산과 디스트 액세스를 보장하는 제1패리티 갱신수단과, 제2디스크 캐쉬 기억수단과 제2디스크 캐쉬 기억수단과 함께 독립적인 패리티 연산과 디스트 액세스를 보장하는 제2패리티 갱신수단과, 제1PCI버스에 접속되어 빠른 SCSI정합을 수행하는 소정 개수의 제2SCSI 정합수단 및 제1PCI버스와 제2PCI버스와 접속되어 넓은 SCSI정합수단을 수행하는 호스트 정합수단을 포함하여, 두 개의 대칭적 PCI버스를 가지는 데에 있으므로, 상술한 바와 같은 본 발명은 대용량의 저장기능,데이터 가용성 향상, 고성능 입출력 성능을 얻을 수 있다는 데에 그 효과가 있다.The present invention relates to a controller structure of a HIPSS (High Performance Storage System), which is a disk array system. The present invention is characterized by a HIPSS having a processor, a local memory, a real time clock generator, and a serial input / output means connected to a processor bus. A controller of claim 1, comprising: floppy disk control means connected to a processor bus to control a floppy disk driver, first PCI bridge means connected to a processor bus and connected to a first PCI bus to match data transfer, and connected to a processor bus A second PCI bridge means connected to the second PCI bus to match data transfer, a second disk cache storage means connected to the first PCI bus to temporarily store data, and a first disk connected to the first disk cache storage means. Update the parity of the data stored in the cache storage means and store the first disk cache First parity updating means for ensuring independent parity operation and disk access, and second parity updating means for guaranteeing independent parity operation and disk access together with second disk cache storage means and second disk cache storage means; Two symmetrical PCI, including a predetermined number of second SCSI matching means connected to the first PCI bus to perform fast SCSI matching, and host matching means connected to the first PCI bus and the second PCI bus to perform wide SCSI matching means. Since the present invention has a bus, the present invention as described above has an effect that a large capacity storage function, improved data availability, and high performance input / output performance can be obtained.

Description

HIPSS의 제어기Controller of HIPSS

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 HIPSS(High Performance Storage System)의 제어기의 블록도.3 is a block diagram of a controller of a high performance storage system (HIPSS) according to the present invention.

Claims (4)

프로세서와 지역 메모리와 실시간 클럭 발생기와 직렬 입출력 수단을 프로세서 버스로 접속하여 구비하고 있는 HIPSS의 제어기에 있어서, 상기 프로세서 버스에 접속되어 플로피 디스크 드라이버를 제어하는 플로피 디스크 제어수단과; 상기프로세서 버스와 접속되어 있고 제1PCI버스와 접속되어 데이터 전송을 정합시키는 제1PCI버스와 접속되어 데이터 전송을 정합시키는 제1PCI브리지 수단과; 상기 프로세서 버스와 접속되어 있고 제2PCI버스와 접속되어 데이터 전송을 정합시키는 제2PCI 브리지 수단과; 상기 1PCI버스와 접속되어 데이터를 임시로 저장하는 제1디스크 캐쉬 기억수단과; 상기 2PCI버스와 접속되어 데이터를 임시로 저장하는 제2디스크 캐쉬 기억수단과; 상기 제1디스크 캐쉬 기억수단과 접속되어 상기 제1디스크 캐쉬 기억수단에 저장되는 데이터의 패리티를 갱신하고 상기 제1디스크 캐쉬 기억수단과 함께 독립적인 패리티 연산과 디스트 액세스를 보장하는 제1패리티 갱신수단과; 상기 제2디스크 캐쉬 기억수단과 접속되어 상기 제2디스크 캐쉬 기억수단에 저장되는 데이터의 패리티를 갱신하고 상기 제2디스크 캐쉬 기억수단과 함께 독립적인 패리티 연산과 디스트 액세스를 보장하는 제2패리티 갱신수단과; 제1PCI 버스에 접속되어 빠른 SCSI 정합을 수행하는 소정 개수의 제2 SCSI 정합수단; 및 상기 제1 PCI 버스와 상기 제2 PCI 버스와 접속되어 넓은 SCSI 정합을 수행하는 호스트 정합수단을 포함하여; 두 개의 대칭적 PCI버스를 가지는것을 특징으로 하는 HIPSS의 제어기.11. A HIPSS controller comprising a processor, a local memory, a real-time clock generator, and a serial input / output means connected to a processor bus, said controller comprising: floppy disk control means connected to said processor bus to control a floppy disk driver; First PCI bridge means connected to said processor bus and connected to a first PCI bus for matching data transmission and for matching data transmission; Second PCI bridge means connected to the processor bus and coupled to a second PCI bus to match data transmission; First disk cache storage means for being connected to said 1PCI bus and temporarily storing data; Second disk cache storage means for being connected to said 2PCI bus and temporarily storing data; First parity updating means connected to said first disk cache storage means for updating the parity of data stored in said first disk cache storage means and ensuring independent parity operation and disk access with said first disk cache storage means; and; Second parity updating means connected to said second disk cache storage means for updating the parity of data stored in said second disk cache storage means and ensuring independent parity calculation and disk access with said second disk cache storage means; and; A predetermined number of second SCSI matching means connected to the first PCI bus for fast SCSI matching; And host matching means connected to the first PCI bus and the second PCI bus to perform wide SCSI matching. Controller of HIPSS characterized by having two symmetrical PCI buses. 프로세서와 지역 메모리와 실시간 클럭 발생기와 직렬 입출력 수단을 프로세서 버스로 접속하여 구비하고 있는 HIPSS의 제어기에 있어서, 다수의 SCSI 인터페이스를 프로세서 버스에 직접 접속하지 않고 두개의 그룹으로 나누어 2개의 PCI버스에 접속한 것을 특징으로 하는 HIPSS의 제어기.In the HIPSS controller, which has a processor, a local memory, a real-time clock generator, and a serial input / output means connected to a processor bus, a plurality of SCSI interfaces are connected to two PCI buses without being directly connected to the processor bus. The controller of the HIPSS characterized in that. 프로세서와 지역 메모리와 실시간 클럭 발생기와 직렬 입출력 수단을 프로세서 버스로 접속하여 구비하고 있는 HIPSS의 제어기에 있어서, 호스트 인터페이스를 프로세서 버스에 직접 접속한 것을 특징으로 하는 HIPSS의 제어기.A controller of a HIPSS comprising a processor, a local memory, a real time clock generator, and a serial input / output means connected to a processor bus, wherein the host interface is directly connected to the processor bus. 프로세서와 지역 메모리와 실시간 클럭 발생기와 직렬 입출력 수단을 프로세서 버스로 접속하여 구비하고 있는 HIPSS의 제어기에 있어서, 디스크 액세스를 최소한으로 하기 위해 대용량의 디스크 캐쉬를 사용하고 패리티 데이터 갱신 부담을 최소화하기 위해 설계된 패리티 엔진을 사용한 것을 특징으로 하는 HIPSS의 제어기.HIPSS controller with processor, local memory, real-time clock generator and serial I / O means connected to processor bus. Controller of HIPSS characterized by using a parity engine. ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019950047873A 1995-12-08 1995-12-08 Hipss controller KR0170492B1 (en)

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KR1019950047873A KR0170492B1 (en) 1995-12-08 1995-12-08 Hipss controller

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Application Number Priority Date Filing Date Title
KR1019950047873A KR0170492B1 (en) 1995-12-08 1995-12-08 Hipss controller

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KR970049370A true KR970049370A (en) 1997-07-29
KR0170492B1 KR0170492B1 (en) 1999-03-30

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