KR970030748A - 히트싱크의 표면 처리방법 및 이를 이용한 반도체 패키지 구조 - Google Patents

히트싱크의 표면 처리방법 및 이를 이용한 반도체 패키지 구조 Download PDF

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Publication number
KR970030748A
KR970030748A KR1019950044554A KR19950044554A KR970030748A KR 970030748 A KR970030748 A KR 970030748A KR 1019950044554 A KR1019950044554 A KR 1019950044554A KR 19950044554 A KR19950044554 A KR 19950044554A KR 970030748 A KR970030748 A KR 970030748A
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KR
South Korea
Prior art keywords
heat sink
semiconductor package
palladium
nickel
package structure
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Application number
KR1019950044554A
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English (en)
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KR0180604B1 (ko
Inventor
서성민
이원균
Original Assignee
황인길
아남산업 주식회사
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Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950044554A priority Critical patent/KR0180604B1/ko
Priority to US08/749,450 priority patent/US5854511A/en
Priority to JP8320732A priority patent/JP3010525B2/ja
Publication of KR970030748A publication Critical patent/KR970030748A/ko
Application granted granted Critical
Publication of KR0180604B1 publication Critical patent/KR0180604B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 히트싱크의 표면 처리방법 및 이를 이용한 반도체 패키지 구조에 관한 것으로, 반도체 패키지에 열방출을 목적으로 내장된 히트싱크 상면의 반도체 칩이 부착되는 영역에만 블랙 산화(Black Oxidation) 처리하여 에폭시와 히트싱크 사이에 접착력을 향상시켜 계면박리 및 크랙을 방지하고, 나머지 부분은 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)으로 도금하여 원활한 그라운드 본딩할 수 있도록 된 히트싱크의 표면 처리방법 및 이를 이용한 반도체 패키지 구조이다.

Description

히트싱크의 표면 처리방법 및 이를 이용한 반도체 패키지 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명의 히트싱크가 적용된 상태의 반도체 패키지 구조를 나타낸 단면도.
제 3도는 본 발명의 제조공정을 설명하기 위한 히트싱크의 평면도.

Claims (3)

  1. 히트싱크의 재질인 구리(Cu)의 표면에 반도체 칩이 부착되는 영역을 마스킹(Masking)하는 단계와, 상기 마스킹(Masking)된 구리(Cu) 표면에 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)층을 도금하는 단계와, 상기 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)층을 도금한 후, 마스킹(Masking)된 부위를 스트립핑(Stripping)하는 단계와, 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)층이 도금된 부위를 제외한 마스킹(Masking)되었던 부위에만 블랙 산화(Black Oxidation) 처리하는 단계와, 상기 단계를 거친 구리(Cu)를 적절한 크기로 절단하는 단계로 이루어진 것을 특징으로 하는 히트싱크 표면 처리방법.
  2. 히트싱크의 상면 외측으로는 다수의 리드가 접착테이프에 의해 부착되고, 상기 히트싱크의 상면 중심부에는 에폭시에 의해 반도체 칩이 부착되며, 상기 반도체 칩과 리드는 와이어 본딩되고, 외부에는 컴파운드로 몰딩된 반도체 패키지에 있어서, 상기 히트싱크의 상면중 반도체 칩이 부착되는 영역에는 블랙 산화(Black Oxidation) 처리하고, 그 외의 나머지 부분에는 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)으로 도금된 것을 특징으로 하는 반도체 패키지 구조.
  3. 제 2항에 있어서, 상기 히트싱크의 은(Ag) 또는 니켈(Ni)/팔라디움(Pd)층이 도금된 표면에 그라운드 본딩하는 것을 특징으로 하는 반도체 패키지 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950044554A 1995-11-17 1995-11-29 히트싱크의 표면처리방법 및 이를 이용한 반도체 패키지 구조 KR0180604B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950044554A KR0180604B1 (ko) 1995-11-29 1995-11-29 히트싱크의 표면처리방법 및 이를 이용한 반도체 패키지 구조
US08/749,450 US5854511A (en) 1995-11-17 1996-11-14 Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads
JP8320732A JP3010525B2 (ja) 1995-11-17 1996-11-15 ヒートシンクが内装された半導体パッケージ及びヒートシンクの表面処理方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950044554A KR0180604B1 (ko) 1995-11-29 1995-11-29 히트싱크의 표면처리방법 및 이를 이용한 반도체 패키지 구조

Publications (2)

Publication Number Publication Date
KR970030748A true KR970030748A (ko) 1997-06-26
KR0180604B1 KR0180604B1 (ko) 1999-03-20

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KR1019950044554A KR0180604B1 (ko) 1995-11-17 1995-11-29 히트싱크의 표면처리방법 및 이를 이용한 반도체 패키지 구조

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030023985A (ko) * 2001-09-14 2003-03-26 주동욱 산화처리된 방열판을 이용하여 피비쥐에이 패키지에전기적 안정성을 확보하는 방법
KR20030023986A (ko) * 2001-09-14 2003-03-26 주동욱 피비쥐에이 방열판에 부착성과 도전성을 확보하는 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030023985A (ko) * 2001-09-14 2003-03-26 주동욱 산화처리된 방열판을 이용하여 피비쥐에이 패키지에전기적 안정성을 확보하는 방법
KR20030023986A (ko) * 2001-09-14 2003-03-26 주동욱 피비쥐에이 방열판에 부착성과 도전성을 확보하는 방법

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Publication number Publication date
KR0180604B1 (ko) 1999-03-20

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