KR960042942A - 반도체 디바이스 형성 방법 - Google Patents

반도체 디바이스 형성 방법 Download PDF

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KR960042942A
KR960042942A KR1019960012566A KR19960012566A KR960042942A KR 960042942 A KR960042942 A KR 960042942A KR 1019960012566 A KR1019960012566 A KR 1019960012566A KR 19960012566 A KR19960012566 A KR 19960012566A KR 960042942 A KR960042942 A KR 960042942A
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케이. 올로우스키 마시우스
켈시 베이커 2세 프랑크
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빈센트 비.인그라시아
모토로라 인코포레이티드
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Abstract

불균일하게 도핑된 채널 영역이 있는 트랜지스터(85)를 포함하는 반도체 디바이스(83)가 높은 주입량 또는 부가적열(heat) 주기를 이용할 필요없이 비교적 간단한 처리로 형성될 수 있다. 한 실시예에서 폴리실리콘층(14)과 질화실리콘 층(16)은 최소 레절류션 경계로 패터닝된다. 폴리실리콘 층은 윙 게이트 구조(32)를 형성하도록 등방성으로 에칭된다. 선택적 채널 주입 단계는 이온이 폴리실리콘 층(14)을 통해 주입되지 않고 윙게이트 구조(32)의 질화물 윙중 최소한 하나를 통해 주입되는 곳에서 실행된다. 다른 폴리실리콘 층(64)은 적합하게 디포지트되고 폴리실리콘(74)이 질화물 윙의 에지를 넘어 확장되지 않도록 에칭된다.

Description

반도체 디바이스 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제9도는 대체로 완성된 디바이스를 형성시킨 후의 제7도의 기판을 도시하는 단면도.

Claims (3)

  1. 반도체 디바이스(83)를 형성하는 방법에 있어서, 제1전도 타입을 갖는 기판(10)상에 제1층(14)을 형성하는 단계와, 상기 제1층(14)위에 마스킹 부재(26)를 형성하는 단계와, 상기 마스킹 부재(18)보다 더 좁은 제1부재(34)를 형성하여 상기 마스킹 부재(26)의 연장 부분이 상기 제1부재위에 놓이지 않게 하도록 상기 제1층(14)을 에칭하는 단계와, 상기 기판(10)의 제1부분이 도핑되어 상기 연장 부분 아래에 높이고 상기 기판(10)의 제2부분은 상기 제1부재의 아래에 놓이며 이 단계동안 도핑하지 않고 여기서 상기 제2부분은 상기 제1부분(44)과 다르게 상기 제1도전 타입의 불순물로 상기 기판(10)을 선택적으로 도핑하는 단계와, 상기 기판(10)상 및 상기 제1부재(34)와 상기 마스킹부재(26)에 인접한 곳에 제2층(64)을 형성하는 단계와, 게이트 전극이 상기 제1부재(34)와 상기 제2층의 나머지 부분(74)을 포함하는 상기 제2층(64)의 일부를 제거하도록 상기 제2층(64)을 에칭하는 단계와, 상기 제1도전 타입과 반대인 제 2도전 타입의 불순물을 이용하여 실행되며, 상기 제 1부분(44)에 인접하고 상기 제1부재(34) 및 상기 제2층의 상기 나머지 부분(74)으로 덮이지 않은 상기 기판(10)의 제3부분(76)을 도핑하는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스(83)형성 방법.
  2. 반도체 디바이스(83)를 형성하는 방법에 있어서, 제1도전 타입의 기판(10)상에 제1층(14)을 형성하는 단계와, 상기 제1층(14)상에 마스킹 부재(26)를 형성하는 단계와, 상기 마스킹 부재(26)보다 더 좁은 제1부재(34)를 형성하기 위해 상기 제1층(14)을 에칭하는 단계와, 상기 마스킹 부재(26)의 아래에 놓이는 상기 기판(10)의 제1부분은 토핑되지만 상기 제1부분(34)의 아래에 놓이는 상기 기판(10)의 제2부분은 이 단계동안 도핑되지 않게 하며 상기 제2부분은 상기 제1부분(44)과다르게 상기 제1도전 타입의 불순물로 상기 기판(10)을 선택적으로 도핑하는 단계와, 게이트 전극이 상기 제1부재(34)와 상기 제2층(74)을 포함하는 상기 기판(10)상 및 상기 제1부재(34)의 근접한 곳에 제2층(64)을 선택적으로 형성하는 단계와, 상기 제1도전 타입과 반대인 제2도전 타입의 불순물을 이용하여 실행되며, 상기 제1부분(44)에 인접하고, 상기 제1부재(34) 및 상기 제2층(74)으로 덮이지 않은 상기 기판(10)의 제3부분(76)을 도핑하는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스(83) 형성 방법.
  3. 반도체 디바이스(83)를 형성하는 방법에 있어서, 제1도전 타입인 상기 기판(10)상에 게이트 유전체 충(12)을 형성하는 단계와, 상기 게이트 유전체 층(12)상에 실리콘 및 금속 함유 물질로 이루어지는 한 그룹에서 선택된 물질을 포함하는 제1층(14)을 형성하는 단계와, 상기 제1층(14)상에 절연층(16)을 형성하는 단계와, 상기 제1층(24)과 상기 절연층(26)을 이방성(anisotropically)으로 에칭하는 단계와, 상기 절연층(26)보다 더 좁도록 상기 제1층(34)을 등방성(isotropically)으로 에칭하는 단계와, 상기 기판(10)의 제1부분이 도핑되고 상기 절연층(26) 아래에 높이며 상기 제1층(34)아래에 놓인 상기 기판(10)의 제2부분이 이 단계동안 도핑되지않도록 하여, 여기서 상기 제2부분이 상기 제1부분(44)과 다르도록 제1도전 타입의 불순물로 상기 기판(10)을 선택적으로 도핑하는 단계와, 상기 기판(10) 및 상기 제1층(34)의 인접한 곳에 실리콘 및 금속 함유 물질로 이루어지는 한 그룹으로부터 선택된 물질을 포함하는 제2층(64)을 형성하는 단계와, 게이트 전극이 상기 제1층(34)과 상기 제2층(74)을 포함하는 제2층의 일부를 제거하기 위해 제2층(74)을 에칭하는 단계와, 소스 영역(76)과 드레인 영역(78)을 형성하기 위해 제1층(34)과 제2층(74)으로 덮이지 않은 상기 기판(10)의 일부를 도핑하며, 여기서 이 단계는 상기 제1도전 타입과 반대인 제2도전 타입의 불순물을 이용하여 실행되고 상기 소스 및 드레인영역(76과 78)은 상기 게이트 전극의 반대편 인접한 곳에 위치하며, 채널 영역은 상기 소드 및 드레인 영역(76과 78) 사이에 위치하며, 상기 제1부분(44)은 상기 소스 영역(76)에 인접한 곳에 위치하여 상기 채널 영역으로 확장하는 것을 특징으로 하는 반도체 디바이스 형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960012566A 1995-05-04 1996-04-24 반도체 디바이스 형성 방법 KR960042942A (ko)

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