KR960036041A - 고내압 트랜지스터 및 그 제조방법 - Google Patents
고내압 트랜지스터 및 그 제조방법 Download PDFInfo
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- KR960036041A KR960036041A KR1019950005145A KR19950005145A KR960036041A KR 960036041 A KR960036041 A KR 960036041A KR 1019950005145 A KR1019950005145 A KR 1019950005145A KR 19950005145 A KR19950005145 A KR 19950005145A KR 960036041 A KR960036041 A KR 960036041A
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- 239000004065 semiconductor Substances 0.000 claims abstract 16
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- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims 7
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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Abstract
드레쉬홀드(threshold) 전압과 소오스와 드레인간의 펀치쓰루(punch through) 특성 및 접합파괴 전압특성을 동시에 개선시킬 수 있는 고내압 트랜지스터 및 그 제조방법에 관해 개시한다. 본 발명은 반도체기판과 상기 반도체기판상에 형성된 필드산화막과 상기 기판상에 형성된 영역별로 다른농도를 갖는 제1 및 제2채널영역으로 형성된 채널영역과 상기 채널영역상에서 단차를 갖는 게이트절연층과, 상기 게이트절연층상에 형성된 단차를 갖는 게이트전극과 상기 제1채널영역과 인접한 저 농도의 제1 및 제2불순물영역과 고 농도의 제3불순물영역으로 형성된 드레인영역과 상기 제2채널영역과 인접한 저 농도의 제1불순물영역과 고 농도의 제3불순물영역으로 형성된 소오스영역과 상기 게이트전극의 측벽에 형성된 스페이서와 상기 결과물을 포함하는 기판상에 형성된 컨택홀을 갖는 층간절연막과 상기 컨택홀을 매립하여 형성된 금속전극으로 구성된다.
본 발명에 의하면 드레쉬홀드전압을 적정수준으로 유지할 수 있고, 접합파괴전압을 증기시킬 수 있으며 펀치쓰루(punch thorugh) 특성을 동시에 향상시킬 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4I도는 본 발명을 이용한 고내압 트랜지스터 및 그 제조방법을 단계별로 나타낸 도면들이다.
Claims (18)
- 반도체 기판; 상기 반도체 기판에 형성되고 기판과 동일한 형태의 불순물로 이루어진 채널스톱(stop)영역; 상기 채널스톱(stop)영역상에 형성된 필드산화막; 상기 필드산화막사이의 기판에 영역별로 다른 불순물농도를 갖는 채널영역; 상기 채널영역의 반도체기판상에 단차를 갖는 게이트절연층; 상기 채널영역양쪽에 서로 비대칭적인 불순물분포형태를 갖는 소오스 및 드레인 영역; 상기 게이트 절연층상에 소오스 및 드레인 영역의 일부까지 확장되고 단차를 갖는 게이트전극; 상기 게이트전극의 측벽에 형성된 스페이서; 상기 기판전면에 형성된 컨택홀을 갖는 층간절연막; 및 상기 컨택홀을 매립하여 형성된 금속 전극으로 구비되는 것을 특징으로 하는 고내압 트랜지스터.
- 제1항 있어서, 상기 채널영역은 상기 반도체기판과 동일한 도전형의 불순물을 이온주입하여 형성된 저 농도의 제1채널영역과 고농도의 제2채널영역으로 구성되는 것을 특징으로 하는 고내압 트랜지스터.
- 제2항에 있어서, 상기 드레인영역은 상기 제1채널영역과 인접해 있고, 상기 소오스영역은 제2채널영역과 인접하여 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 제1항에 있어서, 상기 게이트절연층은 얇은 두께의 제2절연층영역과 두께가 두꺼운 제1절연층영역으로 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 제2항 또는 제4항에 있어서, 상기 제1채널영역상에 제1절연층영역이 형성되어 있고, 상기 제2채널 영역상에 제2절연층영역이 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 제1항에 있어서, 상기 드레인영역은 각각 상기 반도체기판과 반대되는 도전형의 불순물로 형성된 얕고, 깊은 저 농도의 제1, 제2불순물영역과 얕은 고 농도의 제3불순물영역으로 구성되는 것을 특징으로 하는 고내압 트랜지스터.
- 제1항에 있어서, 상기 소오스영역은 상기 반도체기판과 반대되는 도전형불순물로 형성된 저 농도의 얕은 제1불순물 영역과 고농도의 얕은 제3불순물영역으로 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 제6항에 있어서, 상기 제2불순물영역이 제3불순물영역을 완전히 포함하는 구조로 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 제6항 또는 제7항에 있어서, 상기 제3불순물영역이 상기 게이트전극과 일정한 거리를 두어 오버랩(overlap)하지 않게 형성된 것을 특징으로 하는 고내압 트랜지스터.
- 반도체기판상에 패드산화막을 형성하는 단계; 상기 패드산화막상에 질화막을 형성하고 채널스톱(stop) 불순물영역을 형성하는 단계; 상기 채널스톱(stop) 불순물영역상에 필드산화막을 형성하는 단계; 상기 반도체기판에 영역별로 다른 불순물농도를 갖는 채널영역을 형성하는 단계; 상기 반도체기판상에 단차를 갖는 게이트절연층을 형성하는 단계; 상기 게이트절연층상에 단차를 갖는 게이트전극을 형성하는 단계; 상기 채널영역 양쪽에 서로 비댕칭적인 저 농도의 불순물분포형태를 갖는 소오스 및 드레인영역을 형성하는 단계; 상기 게이트전극의 측벽에 스페이서 (spacer)를 형성하는 단계; 상기 소오스 및 드레인영역에 고 농도의 불순물을 대칭적으로 주입하는 단계; 상기 반도체기판 전면에 컨택홀을 갖는 층간 절연막을 형성하는 단계; 및 상기 컨택홀에 금속을 매립하여 금속전극을 형성하는 단계를 포함하는 고내압 트랜지스터 제조방법.
- 제10항 있어서, 상기 채널영역은 상기 반도체기판과 동일한 도전형의 불순물을 이온주입하여 형성된 저 농도의 제1채널영역과 고농도의 제2채널영역으로 형성되는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제11항에 있어서, 상기 제1채널영역은 상기 제1채널영역은 상기 드레인영역과 인접하게 형성되고 상기 제2채널영역은 상기 소오스와 인접하게 형성하는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제10항에 있어서, 상기 게이트절연막은 두께가 얇은 제2절연막영역과 두께가 제1절연막영역으로 형성되는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제11항 또는 제13항에 있어서, 상기 제1채널영역상에는 상기 제1절연층영역을 형성하고, 상기 제2채널영역상에는 상기 제2절연층영역을 형성하는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제10항에 있어서, 상기 드레인영역은 각각 상기 반도체기판과 반대되는 도전형이 불순물을 이온주입하여 형성되는 얕고, 깊은 저농도의 제1, 제2불순물영여과 얕은 고 농도의 제3불순물영역으로 형성되는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제15항에 있어서, 상기 제2불순물영역이 상기 제3불순물영역을 완전히 포함하도록 형성하는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제10항에 있어서, 상기 소오스영역은 상기 반도체기판과 반대되는 도전형불순물을 이온주입하여 형성되는 얕은 저 농도의 제1불순물영역과 고 농도의 제3불순물영역으로 형성되는 것을 특징으로 하는 고내압 트랜지스터 제조방법.
- 제15항 또는 제17항에 있어서, 상기 제3불순물영역은 상기 게이트전극과 일정한 간격을 유지하여 오버랩(overlap)하지 않게 형성하는 것을 특징으로 하는 고내압 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (4)
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KR1019950005145A KR0161398B1 (ko) | 1995-03-13 | 1995-03-13 | 고내압 트랜지스터 및 그 제조방법 |
US08/590,748 US5801416A (en) | 1995-03-13 | 1996-01-24 | FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures |
JP04773196A JP4210347B2 (ja) | 1995-03-13 | 1996-03-05 | 高耐圧トランジスタ及びその製造方法 |
US08/763,093 US5956588A (en) | 1995-03-13 | 1996-12-10 | High withstand voltage transistor and method for manufacturing the same |
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KR1019950005145A KR0161398B1 (ko) | 1995-03-13 | 1995-03-13 | 고내압 트랜지스터 및 그 제조방법 |
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KR960036041A true KR960036041A (ko) | 1996-10-28 |
KR0161398B1 KR0161398B1 (ko) | 1998-12-01 |
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KR1019950005145A KR0161398B1 (ko) | 1995-03-13 | 1995-03-13 | 고내압 트랜지스터 및 그 제조방법 |
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JP (1) | JP4210347B2 (ko) |
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- 1995-03-13 KR KR1019950005145A patent/KR0161398B1/ko not_active IP Right Cessation
-
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- 1996-01-24 US US08/590,748 patent/US5801416A/en not_active Expired - Lifetime
- 1996-03-05 JP JP04773196A patent/JP4210347B2/ja not_active Expired - Fee Related
- 1996-12-10 US US08/763,093 patent/US5956588A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR19990060853A (ko) * | 1997-12-31 | 1999-07-26 | 김영환 | 반도체 소자의 트랜지스터 형성 방법 |
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JP4210347B2 (ja) | 2009-01-14 |
JPH08264788A (ja) | 1996-10-11 |
US5956588A (en) | 1999-09-21 |
US5801416A (en) | 1998-09-01 |
KR0161398B1 (ko) | 1998-12-01 |
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