KR960035999A - Semiconductor leadframe - Google Patents

Semiconductor leadframe Download PDF

Info

Publication number
KR960035999A
KR960035999A KR1019950007363A KR19950007363A KR960035999A KR 960035999 A KR960035999 A KR 960035999A KR 1019950007363 A KR1019950007363 A KR 1019950007363A KR 19950007363 A KR19950007363 A KR 19950007363A KR 960035999 A KR960035999 A KR 960035999A
Authority
KR
South Korea
Prior art keywords
mounting plate
lead frame
semiconductor
center
bent portion
Prior art date
Application number
KR1019950007363A
Other languages
Korean (ko)
Other versions
KR100273693B1 (en
Inventor
문두환
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950007363A priority Critical patent/KR100273693B1/en
Publication of KR960035999A publication Critical patent/KR960035999A/en
Application granted granted Critical
Publication of KR100273693B1 publication Critical patent/KR100273693B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 리드프레임에 관한 것이다. 상기 리드프레임의 탑재판은 반도체 칩이 놓이는 탑재판 중심부와 상기 칩으로부터 그라운드 와이어가 본딩되는 탑재판 주변 본딩부로 되어 있는데, 상기 탑재판 중심부와 상기 탑재판 주변 본딩부 사이에 상향절곡부가 형성되어 상기 탑재판 주변 본딩부가 상기 탑재판 중심부보다 높게 배치된다.The present invention relates to a semiconductor leadframe. The mounting plate of the lead frame includes a center portion of the mounting plate on which the semiconductor chip is placed and a peripheral portion of the mounting plate to which the ground wires are bonded from the chip. An upward bent portion is formed between the mounting plate center and the mounting plate peripheral bonding portion. Bonding portion around the mounting plate is disposed higher than the center of the mounting plate.

이러한 구성으로 반도체칩 패드와 리드프레임 탑재판 사이의 와이어 접착력이 증가되며 접착 용이성이 향상된다.This configuration increases the wire adhesion between the semiconductor chip pad and the lead frame mounting plate and improves the ease of adhesion.

Description

반도체 리드프레임Semiconductor leadframe

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 제1 실시예에 따른 와이어 본딩 후의 리드프레임에 대한 평면도, 제4도는 제3도의 A-A′방향 단면도.3 is a plan view of a lead frame after wire bonding according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view along the line A-A 'of FIG.

Claims (5)

반도체 칩이 상부에 놓이는 리드프레임의 탑재판 중심부와 상기 칩으로부터 그라운드 와이어가 본딩되는 탑재판 주변 본딩부를 포함하는 반도체 리드프레임에 있어서, 상기 탑재판은, 상기 탑재판의 주변부 본딩부가 탑재판 중심부에 비해 상부로 절곡되게 하는 상향 절곡부를 갖는 것을 특징으로 하는 반도체 리드 프레임.A semiconductor lead frame comprising a center portion of a mounting plate of a lead frame on which a semiconductor chip is placed and a peripheral portion of a mounting plate on which ground wires are bonded from the chip, wherein the mounting plate has a peripheral portion bonded to the center of the mounting plate. A semiconductor lead frame having an upward bent portion to be bent upwardly. 제1항에 있어서, 상기 상향절곡부는 1개 형성되는 것을 특징으로 하는 반도체 리드프레임.The semiconductor lead frame according to claim 1, wherein one upward bent portion is formed. 제1항 또는 2항중 어느 한 항에 있어서, 상기 상향절곡부가 형성되는 탑재판을 지지하는 타이바에는 하향절곡부가 없이 수평인 것을 특징으로 하는 반도체 리드프레임.The semiconductor lead frame according to claim 1 or 2, wherein the tie bar supporting the mounting plate on which the upward bent portion is formed is horizontal without the downward bent portion. 제1항에 있어서, 상기 상향절곡부는 복수개인 것을 특징으로 하는 반도체 리드프레임.The semiconductor leadframe according to claim 1, wherein the upward bent portion is plural. 제1항에 있어서, 상기 탑재판 주변 본딩부의 높이는 리드의 높이와 동일한 것을 특징으로 하는 반도체 리드프레임.The semiconductor lead frame according to claim 1, wherein a height of the bonding portion around the mounting plate is equal to a height of a lead. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007363A 1995-03-31 1995-03-31 Semiconductor lead frame KR100273693B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007363A KR100273693B1 (en) 1995-03-31 1995-03-31 Semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007363A KR100273693B1 (en) 1995-03-31 1995-03-31 Semiconductor lead frame

Publications (2)

Publication Number Publication Date
KR960035999A true KR960035999A (en) 1996-10-28
KR100273693B1 KR100273693B1 (en) 2000-12-15

Family

ID=19411164

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007363A KR100273693B1 (en) 1995-03-31 1995-03-31 Semiconductor lead frame

Country Status (1)

Country Link
KR (1) KR100273693B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596563A (en) * 1982-07-05 1984-01-13 Nec Corp Integrated circuit device

Also Published As

Publication number Publication date
KR100273693B1 (en) 2000-12-15

Similar Documents

Publication Publication Date Title
KR960036164A (en) Semiconductor lead frame structure and manufacturing method thereof
KR890007410A (en) Semiconductor devices
KR920702549A (en) Semiconductor device and manufacturing method thereof
KR920015525A (en) Semiconductor device
KR960035999A (en) Semiconductor leadframe
KR980006205A (en) Lead Frame Structure and Semiconductor Package Using the Same
KR970024120A (en) Semiconductor chip package wire bonded with center pads
KR970030693A (en) Semiconductor package
KR960043143A (en) Lead Frames for Semiconductor Packages
KR970023917A (en) Semiconductor package to prevent short circuit of wire
JPS62119933A (en) Integrated circuit device
KR970024084A (en) Semiconductor Chip Package Using Substrate Pads
KR970024101A (en) Lead frame with internal leads installed in the slit of the die pad
KR920001686A (en) Package structure using two-step bonding
KR970024121A (en) Lead frame with tie bars of resin
KR930011190A (en) Semiconductor leadframe
KR970024031A (en) Lead On Chip Package With Multiple Semiconductor Chips
KR920007156A (en) Resin Sealed Semiconductor Device
KR970030744A (en) Package with leadframe with internal leads extending across the diepad
KR960035996A (en) Chip Holding Lead-on Chip Type Semiconductor Package
KR970018429A (en) Packing structure in which die pad is adhered on active area of chip and package using the structure
KR970030703A (en) LOC package without bus bar
KR970013266A (en) Leadframe to prevent sweeping wire sweeping
KR970024081A (en) Chip scale package with leadframe
KR910010675A (en) Semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
N231 Notification of change of applicant
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120903

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20130904

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee