KR960030339A - 반도체장치 및 그 제조공정 - Google Patents

반도체장치 및 그 제조공정 Download PDF

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KR960030339A
KR960030339A KR1019960001977A KR19960001977A KR960030339A KR 960030339 A KR960030339 A KR 960030339A KR 1019960001977 A KR1019960001977 A KR 1019960001977A KR 19960001977 A KR19960001977 A KR 19960001977A KR 960030339 A KR960030339 A KR 960030339A
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thin film
refractory metal
semiconductor device
metal thin
silicon substrate
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KR1019960001977A
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다까아끼 미야모또
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이데이 노브유끼
소니 가부시끼가이샤
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract

실리콘계재료층과 실리콘계재료층상에 성막된 적층구조와를 포함하는 반도체장치로, 상기 적층구조는 고융점금속박막 및/또는 고융점규화금속박막으로 이루어지게 되며, 여기서 각각의 고융점금속박막 및/또는 고융점규화금속박막의 할로겐원자함량이 각각의 고융점금속박막 및/또는 고융점규화금속박막의 양을 기초로 중량비 1% 이하에 있다. 본 발명에 따르면, 그러한 반도체장치를 제조하는 공정이 또한 제공된다.

Description

반도체장치 및 그 제조공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 티타늄박막과 질화티타늄박막이 차례로 접촉공동의 내부면상에 배리어금속층으로써 성막되며, 또한 배선층이 상기 배리어금속층상에 성막되는 본 발명에 따르는 반도체웨이퍼의 일실시예를 개략적으로 나타내는 단면도.

Claims (15)

  1. 실리콘계재료층과; 상기 실리콘계재료층상에 형성되는 것으로 고융점금속박막 및/또는 고융점규화금속박막으로 이루어지게 되는 적층구조와;를 포함하며, 여기서 각각의 상기 고융점금속박막 및/또는 상기 고융점규화금속박막의 할로겐원자함량이 각각의 상기 고융점금속박막 및/또는 상기 고융점규화금속박막의 양을 기초로 중량비 1% 이하인 것을 특징으로 하여 구성된 반도체장치.
  2. 제1항에 있어서, 상기 고융점금속박막 및/또는 상기 고융점규화금속박막의 할로겐원자함량이 각각의 상기 고융점금속박막 및/또는 상기 고융점규화금속박막의 양을 기초로 중량비 0.2~0.7%의 범위내에 있는 것을 특징으로 하여 구성된 반도체장치.
  3. 제1항에 있어서, 상기 고융점금속박막 및/또는 상기 고융점규화금속박막상에 성막된 고융점금속컴파운드박막을 더한층 포함하여 구성된 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 상기 실리콘계재료층은 실리콘기판과 그위에 형성된 층간절연층과로 이루어지며, 상기 층간절연층은 상기 실리콘기판과 대향하는 접촉공동을 가지며, 상기 적층구조가 적어도 상기 접촉공동의 저면부에 성막되는 것을 특징으로 하여 구성된 반도체장치.
  5. 제1항에 있어서, 상기 적층구조는 그 표면에 가까운 위치에 선택적으로 부설된 상기 실리콘계재료층의 불순물확산영역 또는 상기 실리콘계재료층에 부설된 게이트전극상에 셀프-어라인(self-aligned)식으로 성막되는 것을 특징으로 하여 구성된 반도체장치.
  6. 제1항에 있어서, 상기 고융점금속박막 및/또는 상기 고융점규화금속박막은 상기 고융점금속으로써는 티타늄을 상기 할로겐원자로써는 염소원자를 포함하는 것을 특징으로 하여 구성된 반도체장치.
  7. 제2항에 있어서, 상기 고융점금속컴파운드박막은 질화티타늄박막인 것을 특징으로 하여 구성된 반도체장치.
  8. 상기 고융점금속박막의 성막시, 수소가스로부터 유도된 제1리액터의 상기 실리콘기판에 대한 흡착반응이 상기 고융점금속할로겐화물에서 유도된 제2리액터의 상기 실리콘기판에 대한 흡착반응과 비교할 때 보다 우선적으로 수행되도록 초과량의 수소가스를 공급함으로써, 고융점금속할로겐화물에서 적어도 하나의 할로겐원자를 제거시킴으로써 얻어진 제3리액터의 성막이 촉진되게 되는 단계를 포함하는 것을 특징으로 하여, 내부실리콘재료층이 그 적어도 한 부분에 노출되어 있는 실리콘기판과, 고융점금속할로겐화물과 수소가스의 혼합물이 사용되는 플라즈마 화학적기상성장(CVD)법을 사용하여 상기 실리콘기판상에 성막된 고융점금속박막과를 포함하여 구성된 반도체장치를 제조하는 공정.
  9. 제8항에 있어서, 상기 고융점금속박막의 성막시 상기 실리콘기판에 바이어스전압을 가하는 것을 특징으로 하는 반도체장치 제조공정.
  10. 제8항에 있어서, 고융점금속박막의 성막 후에 상기 고융점금속박막상에 고융점금속컴파운드박막을 성막시키는 단계를 더한층 포함하는 것을 특징으로 하는 반도체장치 제조공정.
  11. 제8항에 있어서, 상기 내부실리콘재료층이 노출된 영역상에 성막된 상기 고융점금속박막을 실리사이드화 시킴으로써 고융점규화금속박막을 제조하게 되는 단계를 더한층 포함하는 것을 특징으로 하는 반도체장치 제조공정.
  12. 제8항에 있어서, 상기 고융점금속할로겐화물은 4염화티타늄이고 상기 제조된 고융점금속박막은 티타늄박막인 것을 특징으로 하는 반도체장치 제조공정.
  13. 제10항에 있어서, 상기 제조된 고융점금속박막이 질화티타늄박막인 것을 특징으로 하는 반도체장치 제조공정.
  14. 제8항에 있어서, 상기 실리콘기판상에 상기 고융점금속박막을 성막하기에 앞서 상기 실리콘기판의 표면에서 자연산화층을 제거시키는 단계와; 상기 실리콘기판이 대기와 접촉하게 되는 것을 방지하면서 상기 고융점금속박막의 상기 성막을 수행하는 단계와; 를 더한층 포함하는 것을 특징으로 하는 반도체장치 제조공정.
  15. 제14항에 있어서, 상기 자연산화층의 상기 제거는 수소가스와 회토류가스와의 혼합물을 사용하는 플라즈마처리에 의해 수행되는 것을 특징으로 하는 반도체장치 제조공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960001977A 1995-01-31 1996-01-29 반도체장치 및 그 제조공정 KR960030339A (ko)

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JP7014688A JPH08213343A (ja) 1995-01-31 1995-01-31 半導体装置およびその製造方法
JP95-014688 1995-01-31

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