KR960025757A - Operation Mode Selection Circuit of Semiconductor Memory Device - Google Patents

Operation Mode Selection Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR960025757A
KR960025757A KR1019940037368A KR19940037368A KR960025757A KR 960025757 A KR960025757 A KR 960025757A KR 1019940037368 A KR1019940037368 A KR 1019940037368A KR 19940037368 A KR19940037368 A KR 19940037368A KR 960025757 A KR960025757 A KR 960025757A
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KR
South Korea
Prior art keywords
operation mode
selection circuit
mode selection
semiconductor memory
mode setting
Prior art date
Application number
KR1019940037368A
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Korean (ko)
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KR0143025B1 (en
Inventor
이중화
한진만
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019940037368A priority Critical patent/KR0143025B1/en
Publication of KR960025757A publication Critical patent/KR960025757A/en
Application granted granted Critical
Publication of KR0143025B1 publication Critical patent/KR0143025B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

DRAM등이 반도체 메모리에서 사용되는 복수개의 동작 모우드들중 동작 모우드를 선택하기 위한 동작 모우드 선택회로.An operation mode selection circuit for selecting an operation mode among a plurality of operation modes used in a semiconductor memory such as DRAM.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

동작 모우드 선택회로의 전류소모 방지.Prevents current consumption of the operation mode selection circuit.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

전원공급전압 또는 기준전압을 제공하는 모우드 설정소자와 패드 사이에 휴우즈를 제공하고, 전원공급전압을 제공하는 모우드 설정소자가 사용될때 상기 패드와 기준전압이 제공되는 리이드 사이를 와이어 본딩하고 상기 휴우즈를 용단하며, 기준전압이 제공되는 모우드 설정소자가 사용될 때 상기 패드와 전원공급전압이 제공되는 리이드 사이를 와이어 본딩하고상기 슈우즈를 용단함.A fuse is provided between the pad and the mode setting device providing the power supply voltage or reference voltage, and when the mode setting device providing the power supply voltage is used, wire bonding is performed between the pad and the lead provided with the reference voltage. Melting the wood, wire bonding between the pad and the lead provided with the power supply voltage when a mode setting element provided with a reference voltage is used, and melting the shoe.

4. 발명의 중요한 용도4. Important uses of the invention

DRAM등의 반도체 메모리.Semiconductor memory such as DRAM.

Description

반도체 메모리 장치의 동작 모우드 선택회로Operation Mode Selection Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 동작 모우드 선택회로의 회로도.2 is a circuit diagram of an operation mode selection circuit according to an embodiment of the present invention.

Claims (6)

복수개의 동작 모우드들을 수행할 수 있는 회로가 형성되고, 상기 복수개의 동작 모우드들중 적어도 하나의 동작 모우드를 선택하기 위한 동작 모우드 선택회로가 동일 칩상에 형성된 반도체 메모리에 있어서, 적어도 하나의 패드와, 전원공급전압 또는 기준전압을 제공하기 위한 동작 모우드 설정소자와, 상기 동작모우드 설정소자와 상기 패드사이에 접속된 휴우즈와, 상기 동작 모우드 설정소자가 전원공급전압을 제공할때 기준전압이 공급되고, 상기 동작 모우드 설정소자가 기준전압을 제공할때 전원공급전압이 공급되며 상기 회로와 절연이 죄게 상기 칩과 인접하는 리이드와, 상기 휴우즈가 용단되는 경우 상기 패드와 상기 리이드 사이를 접속하는 접속 수단을 가짐을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로,A semiconductor memory having a circuit capable of performing a plurality of operation modes, the operation mode selection circuit for selecting at least one operation mode of the plurality of operation modes formed on the same chip, at least one pad, An operation mode setting element for providing a power supply voltage or a reference voltage, a fuse connected between the operation mode setting element and the pad, a reference voltage is supplied when the operation mode setting element provides a power supply voltage, Connecting means for connecting a lead adjacent to the chip so that the circuit and the insulation are tight when the operating mode setting element provides a reference voltage, and between the pad and the lead when the fuse is blown; Operation mode selection circuit of the semiconductor memory, characterized in that 제1항에 있어서, 상기 동작 모우드 설정소자는 전원공급전압을 제공하기 위한 풀엎 트랜지스터 또는 풀업고저항중 선택된 어느 하나임을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로.The operation mode selection circuit of claim 1, wherein the operation mode setting element is any one selected from a pull-up transistor or a pull-up high resistance for providing a power supply voltage. 제1항에 있어서 상기 동작 모우드 설정소자는 기준전압을 제공하기 위한 풀다운 트랜지스터 또는 풀다운고정항중 선택된 어느 하나임을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로.The operation mode selection circuit of claim 1, wherein the operation mode setting element is any one selected from a pull-down transistor or a pull-down fixed term for providing a reference voltage. 제1항에 있어서, 상기 접속 수단은 와이어 임을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로The operation mode selection circuit of claim 1, wherein the connection means is a wire. 제1항에 있어서, 상기 휴우즈는 레이저 빔으로 용단되는 폴리 실리콘임을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로.The operation mode selection circuit of claim 1, wherein the fuse is polysilicon melted with a laser beam. 제1항에 있어서, 상기 휴우즈는 전류에 의해 용단되는 풀리 실리콘임을 특징으로 하는 반도체 메모리의 동작 모우드 선택회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.The operation mode selection circuit of a semiconductor memory according to claim 1, wherein the fuse is pulled silicon melted by a current. ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the original application.
KR1019940037368A 1994-12-27 1994-12-27 Motive mode selective circuit of semiconductor memory device KR0143025B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037368A KR0143025B1 (en) 1994-12-27 1994-12-27 Motive mode selective circuit of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037368A KR0143025B1 (en) 1994-12-27 1994-12-27 Motive mode selective circuit of semiconductor memory device

Publications (2)

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KR960025757A true KR960025757A (en) 1996-07-20
KR0143025B1 KR0143025B1 (en) 1998-08-17

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100365431B1 (en) * 2000-08-03 2002-12-18 주식회사 하이닉스반도체 Bonding option circuit
KR100474987B1 (en) * 1997-06-30 2005-05-27 삼성전자주식회사 Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101905327B1 (en) 2017-06-29 2018-10-05 현대위아 주식회사 Chip treatment apparatus of machine tool

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474987B1 (en) * 1997-06-30 2005-05-27 삼성전자주식회사 Semiconductor device
KR100365431B1 (en) * 2000-08-03 2002-12-18 주식회사 하이닉스반도체 Bonding option circuit

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Publication number Publication date
KR0143025B1 (en) 1998-08-17

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