KR920022380A - 반도체장치의 소자분리방법 - Google Patents
반도체장치의 소자분리방법 Download PDFInfo
- Publication number
- KR920022380A KR920022380A KR1019910008121A KR910008121A KR920022380A KR 920022380 A KR920022380 A KR 920022380A KR 1019910008121 A KR1019910008121 A KR 1019910008121A KR 910008121 A KR910008121 A KR 910008121A KR 920022380 A KR920022380 A KR 920022380A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- forming
- oxide film
- semiconductor substrate
- device isolation
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000000926 separation method Methods 0.000 title claims 2
- 238000000034 method Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 4
- 238000005468 ion implantation Methods 0.000 claims 3
- 239000000463 material Substances 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/911—Differential oxidation and etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2E도는 본 발명에 따른 소자분리영역의 형성공정을 도시한 일 실시예의 공정순서도.
Claims (6)
- 반도체기판상의 소자분리영역에 트렌치를 형성한 후, 상기 트렌치의 내벽에 산화저지용 물질을 주입하여 상기 트렌치 내부에 필드산화막을 성장시키는 것을 특징으로 하는 반도체장치의 소자분리방법.
- 제1전도형의 반도체기판상에 제1산화막 및 제1질화막을 차례로 형성하는 공정, 상기 제1질화막위에 포토레지스트 패턴을 적용하여 소자 형성영역 및 분리영역을 정의한 후 상기 분리 영역에 대응되는 부분의 상기 제1질화막 및 제1산화막을 차례로 식각하여 상기 반도체기판을 노출시키는 공정, 상기 노출된 반도체기판을 일정깊이 식각하여 트렌치를 형성하는 공정, 상기 트렌치내벽에 산화저지용 물질을 경사이온주입하는 공정, 상기 트렌치 저부에 제1전도형의 불순물을 주입하여 채널스톱층을 형성하는 공정, 그리고 상기 트렌치 내부에 필드산화막을 성장시키는 공정으로 이루어지는 것을 특징으로 하는 반도체장치의 소자분리방법.
- 제2항에 있어서, 상기 반도체장치의 소자분리방법은 상기 트렌치 형성공정후 상기 트렌치 내면에 산화막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 소자분리방법.
- 제2항에 있어서, 상기 산화저지용 물질은 질소인 것을 특징으로 하는 반도체장치의 소자분리방법.
- 제4항에 있어서, 상기 질소의 이온주입 농도는 1×1016이온/cm2이상인 것을 특징으로 하는 반도체장치의 소자분리방법.
- 제2항에 있어서, 상기 경사이온 주입공정의 경사각도는 상기 트렌치의 크기를 고려하여 10°∼60°의 범위로 하는 것을 특징으로 하는 반도체장치의 소자분리방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910008121A KR920022380A (ko) | 1991-05-18 | 1991-05-18 | 반도체장치의 소자분리방법 |
JP3303651A JPH088297B2 (ja) | 1991-05-18 | 1991-11-20 | 半導体装置の素子分離方法 |
US07/845,705 US5372950A (en) | 1991-05-18 | 1992-03-04 | Method for forming isolation regions in a semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910008121A KR920022380A (ko) | 1991-05-18 | 1991-05-18 | 반도체장치의 소자분리방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR920022380A true KR920022380A (ko) | 1992-12-19 |
Family
ID=19314649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910008121A KR920022380A (ko) | 1991-05-18 | 1991-05-18 | 반도체장치의 소자분리방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5372950A (ko) |
JP (1) | JPH088297B2 (ko) |
KR (1) | KR920022380A (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030056213A (ko) * | 2001-12-27 | 2003-07-04 | 동부전자 주식회사 | 반도체 섭스트레이트의 소자 분리 방법 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5416348A (en) * | 1993-07-15 | 1995-05-16 | Micron Semiconductor, Inc. | Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing the floor of the trench |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5811347A (en) * | 1996-04-29 | 1998-09-22 | Advanced Micro Devices, Inc. | Nitrogenated trench liner for improved shallow trench isolation |
US5899727A (en) | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5854121A (en) * | 1997-09-04 | 1998-12-29 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure |
US6002160A (en) * | 1997-12-12 | 1999-12-14 | Advanced Micro Devices, Inc. | Semiconductor isolation process to minimize weak oxide problems |
KR100253078B1 (ko) | 1997-12-23 | 2000-04-15 | 윤종용 | 반도체 장치의 트렌치 격리 형성 방법 |
US6727569B1 (en) | 1998-04-21 | 2004-04-27 | Advanced Micro Devices, Inc. | Method of making enhanced trench oxide with low temperature nitrogen integration |
KR100286736B1 (ko) | 1998-06-16 | 2001-04-16 | 윤종용 | 트렌치 격리 형성 방법 |
US6218720B1 (en) | 1998-10-21 | 2001-04-17 | Advanced Micro Devices, Inc. | Semiconductor topography employing a nitrogenated shallow trench isolation structure |
JP2000133700A (ja) | 1998-10-22 | 2000-05-12 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6245639B1 (en) | 1999-02-08 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Method to reduce a reverse narrow channel effect for MOSFET devices |
US6413826B2 (en) * | 1999-04-07 | 2002-07-02 | Vantis Corporation | Gate insulator process for nanometer MOSFETS |
TW425656B (en) * | 1999-08-12 | 2001-03-11 | Taiwan Semiconductor Mfg | Manufacturing method of device isolation structure |
US6472301B1 (en) * | 1999-10-19 | 2002-10-29 | Infineon Technologies Ag | Method and structure for shallow trench isolation |
US6709930B2 (en) | 2002-06-21 | 2004-03-23 | Siliconix Incorporated | Thicker oxide formation at the trench bottom by selective oxide deposition |
US6780730B2 (en) | 2002-01-31 | 2004-08-24 | Infineon Technologies Ag | Reduction of negative bias temperature instability in narrow width PMOS using F2 implantation |
US7012005B2 (en) * | 2002-06-25 | 2006-03-14 | Siliconix Incorporated | Self-aligned differential oxidation in trenches by ion implantation |
TW200847337A (en) * | 2007-05-16 | 2008-12-01 | Promos Technologies Inc | Method for preparing a shallow trench isolation |
KR101057652B1 (ko) * | 2008-11-07 | 2011-08-18 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US10163679B1 (en) * | 2017-05-31 | 2018-12-25 | Globalfoundries Inc. | Shallow trench isolation formation without planarization |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202426A (ja) * | 1985-03-05 | 1986-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS62142318A (ja) * | 1985-12-17 | 1987-06-25 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4740481A (en) * | 1986-01-21 | 1988-04-26 | Motorola Inc. | Method of preventing hillock formation in polysilicon layer by oxygen implanation |
JPS6372114A (ja) * | 1986-09-16 | 1988-04-01 | Matsushita Electronics Corp | メモリ−セルの製造方法 |
JPS63300518A (ja) * | 1987-05-29 | 1988-12-07 | Fujitsu Ltd | 誘電体膜の形成方法 |
US4923563A (en) * | 1987-06-15 | 1990-05-08 | Ncr Corporation | Semiconductor field oxide formation process using a sealing sidewall of consumable nitride |
JPH01245519A (ja) * | 1988-03-28 | 1989-09-29 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH02267952A (ja) * | 1989-04-08 | 1990-11-01 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH0340431A (ja) * | 1989-07-07 | 1991-02-21 | Fuji Electric Co Ltd | シリコン半導体装置の酸化膜形成方法 |
FR2672731A1 (fr) * | 1991-02-07 | 1992-08-14 | France Telecom | Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant. |
-
1991
- 1991-05-18 KR KR1019910008121A patent/KR920022380A/ko not_active Application Discontinuation
- 1991-11-20 JP JP3303651A patent/JPH088297B2/ja not_active Expired - Fee Related
-
1992
- 1992-03-04 US US07/845,705 patent/US5372950A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030056213A (ko) * | 2001-12-27 | 2003-07-04 | 동부전자 주식회사 | 반도체 섭스트레이트의 소자 분리 방법 |
Also Published As
Publication number | Publication date |
---|---|
JPH04346229A (ja) | 1992-12-02 |
US5372950A (en) | 1994-12-13 |
JPH088297B2 (ja) | 1996-01-29 |
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Legal Events
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WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |