KR920013648A - Chip bonding method of semiconductor device - Google Patents

Chip bonding method of semiconductor device Download PDF

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Publication number
KR920013648A
KR920013648A KR1019900020450A KR900020450A KR920013648A KR 920013648 A KR920013648 A KR 920013648A KR 1019900020450 A KR1019900020450 A KR 1019900020450A KR 900020450 A KR900020450 A KR 900020450A KR 920013648 A KR920013648 A KR 920013648A
Authority
KR
South Korea
Prior art keywords
semiconductor device
bonding method
chip
chip bonding
die pad
Prior art date
Application number
KR1019900020450A
Other languages
Korean (ko)
Other versions
KR940000746B1 (en
Inventor
김진호
안재문
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900020450A priority Critical patent/KR940000746B1/en
Publication of KR920013648A publication Critical patent/KR920013648A/en
Application granted granted Critical
Publication of KR940000746B1 publication Critical patent/KR940000746B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

내용 없음No content

Description

반도체 장치의 칩 본딩 방법Chip bonding method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 이 발명에 따른 반도체장치의 단면구조도, 제4도의 (가)는 이 발명에 따른 칩 본딩 방법을 타낸 분리사시도, (나)는 이 발명에 따라 칩 본딩된 상태의 단면도.3 is a cross-sectional structure diagram of a semiconductor device according to the present invention, (a) is an exploded perspective view showing a chip bonding method according to the present invention, (b) is a cross-sectional view of a chip bonded state according to the present invention.

Claims (1)

다이패드(11)상에 접착제(13)를 도트형태로 부착하여 칩(12)을 본딩시키는 반도체장치의 칩 본딩 방법에 있어서, 상기 반도체장치(17)의 실장시 패키지(16)내의 다이패드(11)저면에서 발행하는 압력을 분산시킬 수 있는 완충공간부(18)가 칩(12)과 다이패드(11)사이에 형성되도록 도트형태의 접착제(13)를 다이패드(11)테두리와 수직, 수평 방향으로만 형성하여 칩(12)을 부착하는 반도체장치의 칩 본딩 방법.In the chip bonding method of the semiconductor device which bonds the chip | tip 12 by attaching the adhesive agent 13 in the shape of a dot on the die pad 11, The die pad in the package 16 when the said semiconductor device 17 is mounted ( 11) the dot-shaped adhesive 13 is perpendicular to the edge of the die pad 11 so that a buffer space portion 18 capable of dispersing the pressure issued from the bottom surface is formed between the chip 12 and the die pad 11. A chip bonding method of a semiconductor device in which the chip 12 is attached only by being formed in the horizontal direction. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900020450A 1990-12-13 1990-12-13 Chip bonding method of semiconductor KR940000746B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020450A KR940000746B1 (en) 1990-12-13 1990-12-13 Chip bonding method of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020450A KR940000746B1 (en) 1990-12-13 1990-12-13 Chip bonding method of semiconductor

Publications (2)

Publication Number Publication Date
KR920013648A true KR920013648A (en) 1992-07-29
KR940000746B1 KR940000746B1 (en) 1994-01-28

Family

ID=19307426

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900020450A KR940000746B1 (en) 1990-12-13 1990-12-13 Chip bonding method of semiconductor

Country Status (1)

Country Link
KR (1) KR940000746B1 (en)

Also Published As

Publication number Publication date
KR940000746B1 (en) 1994-01-28

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