KR870006716A - Digital level detection circuit - Google Patents

Digital level detection circuit Download PDF

Info

Publication number
KR870006716A
KR870006716A KR860010823A KR860010823A KR870006716A KR 870006716 A KR870006716 A KR 870006716A KR 860010823 A KR860010823 A KR 860010823A KR 860010823 A KR860010823 A KR 860010823A KR 870006716 A KR870006716 A KR 870006716A
Authority
KR
South Korea
Prior art keywords
response
level detection
constant
attack
level
Prior art date
Application number
KR860010823A
Other languages
Korean (ko)
Other versions
KR960000841B1 (en
Inventor
히데끼 후까사와
Original Assignee
오오가 노리오
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오오가 노리오, 소니 가부시끼 가이샤 filed Critical 오오가 노리오
Publication of KR870006716A publication Critical patent/KR870006716A/en
Application granted granted Critical
Publication of KR960000841B1 publication Critical patent/KR960000841B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Analogue/Digital Conversion (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

내용 없음.No content.

Description

디지탈 레벨 검출 회로Digital level detection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1, 제3도는 본 발명의 일예의 계통도.1 and 3 are schematic diagrams of an example of the present invention.

제4도는 그 설명을 하기 위한 도면.4 is a diagram for explanation.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

12 : 검출 회로 15,22 : ROM12: detection circuit 15,22: ROM

Claims (1)

입력된 디지털 데이터의 절대치를 검출하는 검출 회로와, 상기 절대치와 레벨 검출 출력과의 비를 구하는 계산 회로와, 어택 응답용의 정수가 기억되어 있는 제1의 메모리와, 홀드 응답용 및 복원 응답용의 정수가 기억되어 있는 제2의 메모리와, 연산 회로를 가지며, 상기 어택 응답용의 정수는 어택 응답시의 시간경과에 따라서 변화하는 값으로 되어, 상기 홀드 응답용 및 복원 응답용의 정수는 0이 아닌 값으로 되어, 상기 제산 회로의 출력에 의거하여 어택 응답 동작과 홀드 응답 동작 및 복원 응답 동작이 전환되어, 상기 어택 응답 동작시에는, 상기 연산 회로에 있어서 상기 어택 응답용의 정수와 상기 레벨 검출 출력 사이에서 승산 및 가산이 행해져서 상기 입력된 디지털 데이타의 레벨을 도시하는 상기 레벨 검출 출력이 인출되어, 상기 홀드 응답 동작 및 복원 응답 동작시에는, 상기 연산 회로에 있어서 상기 홀드 응답용 및 복원 응답용의 정수와 상기 레벨 검출 출력 사이에서 승산 및 가산이 행해져서 상기 입력된 디지털 데이터의 레벨을 도시하는 상기 레벨 검출 출력이 인출되는 디지털 레벨검출 회로.A detection circuit for detecting the absolute value of the input digital data, a calculation circuit for calculating the ratio between the absolute value and the level detection output, a first memory storing an integer for the attack response, a hold response and a restoration response And a second memory having a constant stored therein, and an arithmetic circuit, wherein the constant for the attack response is a value that changes with time in the attack response, and the constant for the hold response and the restore response is 0. Is a value other than 0, and the attack response operation, the hold response operation, and the restoration response operation are switched based on the output of the division circuit, and during the attack response operation, the constant and the level for the attack response in the calculation circuit are used. Multiplication and addition are performed between the detection outputs so that the level detection output showing the level of the input digital data is drawn, and the hold response is obtained. In the operation and restoration response operation, in the calculation circuit, multiplication and addition are performed between the constant for the hold response and the restoration response and the level detection output, so that the level detection output showing the level of the input digital data. This digital level detection circuit is drawn out. ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860010823A 1985-12-17 1986-12-17 Digital level detection circuit KR960000841B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP283263 1985-12-17
JP60283263A JPH0716162B2 (en) 1985-12-17 1985-12-17 Digital level detection circuit

Publications (2)

Publication Number Publication Date
KR870006716A true KR870006716A (en) 1987-07-14
KR960000841B1 KR960000841B1 (en) 1996-01-13

Family

ID=17663188

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860010823A KR960000841B1 (en) 1985-12-17 1986-12-17 Digital level detection circuit

Country Status (2)

Country Link
JP (1) JPH0716162B2 (en)
KR (1) KR960000841B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2681956B2 (en) * 1988-01-19 1997-11-26 ソニー株式会社 Envelope detection method for digital signal processor
JP2681957B2 (en) * 1988-01-19 1997-11-26 ソニー株式会社 Digital signal processor
EP2009786B1 (en) * 2007-06-25 2015-02-25 Harman Becker Automotive Systems GmbH Feedback limiter with adaptive control of time constants

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767323A (en) * 1980-10-15 1982-04-23 Fujitsu Ltd Analogue-digital converting circuit provided with agc function
JPS5966222A (en) * 1982-10-08 1984-04-14 Toshiba Corp Compact type analog-digital converter

Also Published As

Publication number Publication date
KR960000841B1 (en) 1996-01-13
JPH0716162B2 (en) 1995-02-22
JPS62142420A (en) 1987-06-25

Similar Documents

Publication Publication Date Title
KR890012385A (en) Semiconductor integrated circuit
KR860004352A (en) I / O processing unit
JPS57207958A (en) Data correcting device
KR900010544A (en) Reciprocal Operation Circuit with ROM Table
KR970056064A (en) Signal processing method
KR830009529A (en) Galois Computation Circuit
KR890015121A (en) Division calculator
KR830006739A (en) Data processing device
KR850004838A (en) Signal detector
KR920020965A (en) Motion vector detector
KR850003641A (en) Method and device for compensating cutoff of sample signal
KR870006716A (en) Digital level detection circuit
KR840003159A (en) Inverter Control Circuit
KR900002576A (en) Error correction device
KR850002711A (en) Complex capacitive impedance
KR890012220A (en) Code conversion circuit
KR870006713A (en) Digital level detection circuit
KR880002319A (en) Gain control amplifier
KR900016857A (en) Clear blue circuit
KR920003769A (en) Surround control circuit
KR890008672A (en) Error detection prevention of EP ROM data
KR910005150A (en) Calculator and the calculation method used in this calculator
Euler et al. Of the Division of Simple Quantities
KR870006507A (en) Display of binary value below decimal point
JPS5338343A (en) Display device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee