KR920008920A - 반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛 - Google Patents
반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛 Download PDFInfo
- Publication number
- KR920008920A KR920008920A KR1019910018165A KR910018165A KR920008920A KR 920008920 A KR920008920 A KR 920008920A KR 1019910018165 A KR1019910018165 A KR 1019910018165A KR 910018165 A KR910018165 A KR 910018165A KR 920008920 A KR920008920 A KR 920008920A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- integrated circuit
- output unit
- voltage level
- level fluctuation
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 반도체 메모리 장치에 구비된 본 발명에 따른 출력 유닛의 회로 구성을 도시한 회로도.
Claims (1)
- a) 각각 제1채널 도전형의 제1 트랜지스터(Qp11)와, 제1전압선(Vdd)과 상기 반도체 기판에 전기적으로 접속된 제2전압선(GND)사이에 접속된 공통 절점(N11) 및 제2채널 도전형의 제2트랜지스터(Qn12)로 구성된 복수의 출력 반전회로(141, 142, 14n)와; b) 각각 상기 공통 절점들의 하나와 접속되는 복수의 출력 데이타핀(OUT11, OUT12, OUTn)을, 구비하는, 단일한 반도체 기판(11)상에 형성된 집적회로의 출력 유닛에 있어서, c) 상기 제2전압선과 상기 반도체 기판사이에 접속된 저항 수단(R12)을, 더 포함하는 것을 특징으로 하는 출력 유닛.※ 참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2279752A JPH04155693A (ja) | 1990-10-18 | 1990-10-18 | 半導体記憶装置のデータ出力回路 |
JP90-279752 | 1990-10-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920008920A true KR920008920A (ko) | 1992-05-28 |
KR950008449B1 KR950008449B1 (ko) | 1995-07-31 |
Family
ID=17615415
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910018165A KR950008449B1 (ko) | 1990-10-18 | 1991-10-16 | 반도체 기판의 전압 레벨 변동을 방지하기 위한 반도체 집적회로의 출력 유닛 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5357461A (ko) |
EP (1) | EP0481678B1 (ko) |
JP (1) | JPH04155693A (ko) |
KR (1) | KR950008449B1 (ko) |
DE (1) | DE69122203T2 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0583696A (ja) * | 1991-06-07 | 1993-04-02 | Sony Corp | 画像符号化装置 |
JPH05236427A (ja) * | 1992-02-25 | 1993-09-10 | Sony Corp | 画像信号の符号化装置及び符号化方法 |
US5311083A (en) * | 1993-01-25 | 1994-05-10 | Standard Microsystems Corporation | Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads |
EP0896268B1 (en) * | 1997-08-07 | 2001-06-13 | STMicroelectronics S.r.l. | An integrated device for switching systems with filtered reference quantities |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4376986A (en) * | 1981-09-30 | 1983-03-15 | Burroughs Corporation | Double Lambda diode memory cell |
JPS5921128A (ja) * | 1982-07-26 | 1984-02-03 | Nec Ic Microcomput Syst Ltd | 電界効果半導体装置 |
JPH0714051B2 (ja) * | 1986-07-15 | 1995-02-15 | 沖電気工業株式会社 | 半導体装置 |
US4797804A (en) * | 1987-03-09 | 1989-01-10 | International Business Machines Corporation | High density, high performance, single event upset immune data storage cell |
US4862018A (en) * | 1987-11-30 | 1989-08-29 | Texas Instruments Incorporated | Noise reduction for output drivers |
JP2822391B2 (ja) * | 1988-06-27 | 1998-11-11 | 日本電気株式会社 | 半導体記憶装置 |
JP2855701B2 (ja) * | 1989-09-29 | 1999-02-10 | 日本電気株式会社 | Cmos半導体集積回路装置 |
-
1990
- 1990-10-18 JP JP2279752A patent/JPH04155693A/ja active Pending
-
1991
- 1991-10-10 EP EP91309319A patent/EP0481678B1/en not_active Expired - Lifetime
- 1991-10-10 DE DE69122203T patent/DE69122203T2/de not_active Expired - Fee Related
- 1991-10-16 KR KR1019910018165A patent/KR950008449B1/ko not_active IP Right Cessation
- 1991-10-18 US US07/778,653 patent/US5357461A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69122203T2 (de) | 1997-01-30 |
EP0481678A1 (en) | 1992-04-22 |
DE69122203D1 (de) | 1996-10-24 |
US5357461A (en) | 1994-10-18 |
JPH04155693A (ja) | 1992-05-28 |
EP0481678B1 (en) | 1996-09-18 |
KR950008449B1 (ko) | 1995-07-31 |
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